Searched refs:SchedRead (Results 1 – 18 of 18) sorted by relevance
109 def ReadJmp : SchedRead;110 def ReadJalr : SchedRead;111 def ReadCSR : SchedRead;112 def ReadMemBase : SchedRead;113 def ReadFMemBase : SchedRead;114 def ReadStoreData : SchedRead;115 def ReadIALU : SchedRead;116 def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I117 def ReadShiftImm : SchedRead;118 def ReadShiftImm32 : SchedRead; // 32-bit shift by immediate operations on RV64Ix[all …]
32 def ReadSHXADD : SchedRead; // sh1add/sh2add/sh3add33 def ReadSHXADD32 : SchedRead; // sh1add.uw/sh2add.uw/sh3add.uw36 def ReadRotateImm : SchedRead;37 def ReadRotateImm32 : SchedRead;38 def ReadRotateReg : SchedRead;39 def ReadRotateReg32 : SchedRead;40 def ReadCLZ : SchedRead;41 def ReadCLZ32 : SchedRead;42 def ReadCTZ : SchedRead;43 def ReadCTZ32 : SchedRead;[all …]
27 def ReadI : SchedRead; // ALU28 def ReadISReg : SchedRead; // ALU of Shifted-Reg29 def ReadIEReg : SchedRead; // ALU of Extended-Reg31 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair35 def ReadID : SchedRead; // 32/64-bit Divide38 def ReadIM : SchedRead; // 32/64-bit Multiply39 def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate50 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.86 def ReadVLD : SchedRead;
188 // Subtarget-specific SchedRead types.
146 // Subtarget-specific SchedRead types.
173 // Subtarget-specific SchedRead types.
861 // Unused SchedRead types
213 // listed for implicit def operands. SchedRead types may optionally219 // single SchedWrite and single SchedRead in any order.229 class SchedRead : SchedReadWrite;326 // A processor may define a ReadAdvance associated with a SchedRead336 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>338 SchedRead ReadType = read;341 // Directly associate a new SchedRead type with a delay and optional343 class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead,346 // Define SchedRead defaults. Reads seldom need special treatment.347 def ReadDefault : SchedRead;[all …]
61 def ReadALU : SchedRead;67 def ReadALUsr : SchedRead; // Some operands are read later.79 def ReadMUL : SchedRead;86 def ReadMAC : SchedRead;118 def ReadFPMUL : SchedRead; // multiplier read119 def ReadFPMAC : SchedRead; // accumulator read
9 // This file defines the SchedRead/Write data for the ARM Cortex-R52 processor.46 def R52Read_ISS : SchedRead;47 def R52Read_EX1 : SchedRead;48 def R52Read_EX2 : SchedRead;49 def R52Read_WRI : SchedRead;50 def R52Read_F0 : SchedRead; // F0 maps to ISS stage of integer pipe51 def R52Read_F1 : SchedRead;52 def R52Read_F2 : SchedRead;
9 // This file defines the SchedRead/Write data for the ARM Cortex-M4 processor.
9 // This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
775 // def A57ReadVFMA : SchedRead;
15 def ReadAfterLd : SchedRead;16 def ReadAfterVecLd : SchedRead;17 def ReadAfterVecXLd : SchedRead;18 def ReadAfterVecYLd : SchedRead;22 // This SchedRead describes a bypass delay caused by data being moved from the24 def ReadInt2Fpu : SchedRead;48 // The SchedRead to tag register operands than don't need to be ready50 SchedRead ReadAfterFold;54 multiclass X86SchedWritePair<SchedRead ReadAfter = ReadAfterLd> {
817 SchedRead Int2Fpu = ReadDefault> {
109 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,880 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, in FindReadAdvance() argument883 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) in FindReadAdvance()884 return SchedRead.TheDef; in FindReadAdvance()888 for (Record *A : SchedRead.Aliases) { in FindReadAdvance()911 || SchedRead.TheDef == RA->getValueAsDef("ReadType")) { in FindReadAdvance()922 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") { in FindReadAdvance()925 SchedRead.TheDef->getName()); in FindReadAdvance()
35 def RegReadAdv : SchedRead;
27 def MIVGPRRead : SchedRead;28 def MIMFMARead : SchedRead;