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Searched refs:SRL (Results 1 – 25 of 120) sorted by relevance

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/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/sha/asm/
H A Dsha512-mips.pl97 $SRL="dsrl"; # shift right logical
112 $SRL="srl"; # shift right logical
210 $SRL $h,$e,@Sigma1[0]
214 $SRL $tmp0,$e,@Sigma1[1]
218 $SRL $tmp0,$e,@Sigma1[2]
225 $SRL $h,$a,@Sigma0[0]
230 $SRL $tmp0,$a,@Sigma0[1]
234 $SRL $tmp0,$a,@Sigma0[2]
261 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
267 $SRL $tmp3,@X[14],@sigma1[0]
[all …]
H A Dsha512-sparcv9.pl68 $SRL="srlx"; # shift right logical
94 $SRL="srl"; # shift right logical
232 $SRL $e,@Sigma1[0],$h !! $i
236 $SRL $e,@Sigma1[1],$tmp0
240 $SRL $e,@Sigma1[2],$tmp0
247 $SRL $a,@Sigma0[0],$h
252 $SRL $a,@Sigma0[1],$tmp0
256 $SRL $a,@Sigma0[2],$tmp0
/netbsd-src/crypto/external/bsd/openssl/dist/crypto/sha/asm/
H A Dsha512-mips.pl103 $SRL="dsrl"; # shift right logical
118 $SRL="srl"; # shift right logical
216 $SRL $h,$e,@Sigma1[0]
220 $SRL $tmp0,$e,@Sigma1[1]
224 $SRL $tmp0,$e,@Sigma1[2]
231 $SRL $h,$a,@Sigma0[0]
236 $SRL $tmp0,$a,@Sigma0[1]
240 $SRL $tmp0,$a,@Sigma0[2]
267 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
273 $SRL $tmp3,@X[14],@sigma1[0]
[all …]
H A Dsha512-sparcv9.pl70 $SRL="srlx"; # shift right logical
96 $SRL="srl"; # shift right logical
234 $SRL $e,@Sigma1[0],$h !! $i
238 $SRL $e,@Sigma1[1],$tmp0
242 $SRL $e,@Sigma1[2],$tmp0
249 $SRL $a,@Sigma0[0],$h
254 $SRL $a,@Sigma0[1],$tmp0
258 $SRL $a,@Sigma0[2],$tmp0
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h36 SRL = 0x27, enumerator
94 case SRL: in lanaiAluCodeToString()
113 .Case("srl", SRL) in stringToLanaiAluCode()
136 case ISD::SRL: in isdToLanaiAluCode()
137 return AluCode::SRL; in isdToLanaiAluCode()
H A DLanaiMemAluCombiner.cpp222 return LPAC::SRL; in mergedAluCode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp321 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
338 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. in getArithmeticInstrCost()
356 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
380 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. in getArithmeticInstrCost()
511 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
515 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
519 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
530 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. in getArithmeticInstrCost()
533 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. in getArithmeticInstrCost()
[all …]
H A DX86ISelDAGToDAG.cpp694 case ISD::SRL: in IsProfitableToFold()
1019 case ISD::SRL: { in PreprocessISelDAG()
1030 case ISD::SRL: NewOpc = X86ISD::VSRLV; break; in PreprocessISelDAG()
1840 if (Shift.getOpcode() != ISD::SRL || in foldMaskAndShiftToExtract()
1854 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract()
1976 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() || in foldMaskAndShiftToScale()
2035 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); in foldMaskAndShiftToScale()
2064 if (Shift.getOpcode() != ISD::SRL || in foldMaskedShiftToBEXTR()
2090 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); in foldMaskedShiftToBEXTR()
2212 case ISD::SRL: { in matchAddressRecursively()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1456 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1465 Opc = ISD::SRL; in SimplifyDemandedBits()
1499 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
1549 case ISD::SRL: { in SimplifyDemandedBits()
1569 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
1618 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
1652 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); in SimplifyDemandedBits()
1659 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); in SimplifyDemandedBits()
2023 case ISD::SRL: in SimplifyDemandedBits()
2026 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
[all …]
H A DLegalizeIntegerTypes.cpp91 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
408 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
474 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
496 return DAG.getNode(ISD::SRL, dl, NVT, in PromoteIntRes_BITREVERSE()
814 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
877 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
985 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, in PromoteIntRes_DIVFIX()
1166 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRL()
1205 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amount); in PromoteIntRes_FunnelShift()
1207 Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift); in PromoteIntRes_FunnelShift()
[all …]
H A DDAGCombiner.cpp1373 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1651 case ISD::SRL: return visitSRL(N); in visit()
1778 case ISD::SRL: in combine()
2219 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2238 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL; in foldAddSubOfSignBit()
3281 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3284 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3556 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
4219 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike()
4326 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); in visitUDIVLike()
[all …]
H A DLegalizeVectorOps.cpp384 case ISD::SRL: in LegalizeOp()
1139 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) && in ExpandBITREVERSE()
1156 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBITREVERSE()
1257 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) { in ExpandUINT_TO_FLOAT()
1284 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Src, HalfWord); in ExpandUINT_TO_FLOAT()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/netbsd-src/crypto/external/bsd/openssl/dist/crypto/bn/asm/
H A Dmips.pl69 $SRL="dsrl";
84 $SRL="srl";
930 $SRL $at,$a1,$t1
945 $SRL $DH,$a2,4*$BNSZ # bits
954 $SRL $HH,$a0,4*$BNSZ # bits
955 $SRL $QT,4*$BNSZ # q=0xffffffff
962 $SRL $at,$a1,4*$BNSZ # bits
987 $SRL $HH,$a0,4*$BNSZ # bits
988 $SRL $QT,4*$BNSZ # q=0xffffffff
995 $SRL $at,$a1,4*$BNSZ # bits
[all …]
/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/bn/asm/
H A Dmips.pl69 $SRL="dsrl";
84 $SRL="srl";
928 $SRL $at,$a1,$t1
943 $SRL $DH,$a2,4*$BNSZ # bits
952 $SRL $HH,$a0,4*$BNSZ # bits
953 $SRL $QT,4*$BNSZ # q=0xffffffff
960 $SRL $at,$a1,4*$BNSZ # bits
985 $SRL $HH,$a0,4*$BNSZ # bits
986 $SRL $QT,4*$BNSZ # q=0xffffffff
993 $SRL $at,$a1,4*$BNSZ # bits
[all …]
/netbsd-src/sys/external/bsd/sljit/dist/sljit_src/
H A DsljitNativeSPARC_32.c73 …return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)… in emit_single_op()
132 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
H A DsljitNativeMIPS_32.c141 FAIL_IF(push_inst(compiler, SRL | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG)); in emit_single_op()
208 return push_inst(compiler, SRL | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_FLAG); in emit_single_op()
341 return push_inst(compiler, SRL | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_FLAG); in emit_single_op()
405 EMIT_SHIFT(SRL, SRLV); in emit_single_op()
H A DsljitNativeMIPS_64.c232 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_… in emit_single_op()
299 …return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), … in emit_single_op()
432 …return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), … in emit_single_op()
499 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp84 setOperationAction(ISD::SRL, MVT::i8, Custom); in AVRTargetLowering()
87 setOperationAction(ISD::SRL, MVT::i16, Custom); in AVRTargetLowering()
289 case ISD::SRL: in LowerShifts()
327 case ISD::SRL: in LowerShifts()
345 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && in LowerShifts()
356 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { in LowerShifts()
372 case ISD::SRL: in LowerShifts()
385 case ISD::SRL: in LowerShifts()
402 case ISD::SRL: in LowerShifts()
792 case ISD::SRL: in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp804 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
944 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
2348 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
2349 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in lowerFCOPYSIGN32()
2398 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
2399 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
2442 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
2473 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in lowerFABS64()
2580 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, in lowerShiftLeftParts()
2582 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); in lowerShiftLeftParts()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp430 setOperationAction(ISD::SRL, VT, Expand); in AMDGPUTargetLowering()
551 setTargetDAGCombine(ISD::SRL); in AMDGPUTargetLowering()
1957 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
2455 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64, in LowerINT_TO_FP32()
2635 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
2639 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
2648 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
2680 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerFP_TO_FP16()
2688 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
2703 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h649 SRL, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp77 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
80 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
342 case ISD::SRL: in LowerOperation()
983 case ISD::SRL: in LowerShifts()
995 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp242 case LPAC::SRL: in getRrMemoryOpValue()
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/m32r/
H A DChangeLog-2021132 * srl.cgs: Test SRL instruction.

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