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Searched refs:SINT_TO_FP (Results 1 – 25 of 34) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp603 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
606 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
608 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
610 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
612 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
614 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
616 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
618 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
620 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
622 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
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H A DARMISelLowering.cpp173 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
178 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
308 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
907 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
908 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
1034 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
5693 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
5695 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
5713 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
9068 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp662 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
663 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
664 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
670 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
671 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
672 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
678 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
679 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
684 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }, in getCastInstrCost()
685 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp455 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
456 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
457 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
881 setTargetDAGCombine(ISD::SINT_TO_FP); in AArch64TargetLowering()
985 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
994 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32); in AArch64TargetLowering()
995 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32); in AArch64TargetLowering()
998 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v16i8, MVT::v16i32); in AArch64TargetLowering()
1001 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
1003 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom); in AArch64TargetLowering()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1529 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
1530 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
1628 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
1629 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
1630 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, in getCastInstrCost()
1631 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, in getCastInstrCost()
1632 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
1633 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, in getCastInstrCost()
1634 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
1635 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
[all …]
H A DREADME-FPStack.txt49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
H A DX86ISelLowering.cpp245 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in X86TargetLowering()
249 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom); in X86TargetLowering()
252 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in X86TargetLowering()
256 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in X86TargetLowering()
850 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
1027 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in X86TargetLowering()
1029 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in X86TargetLowering()
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom); in X86TargetLowering()
1183 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom); in X86TargetLowering()
1252 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); in X86TargetLowering()
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H A DX86IntrinsicsInfo.h913 X86_INTRINSIC_DATA(avx512_sitofp_round, INTR_TYPE_1OP, ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp475 case ISD::SINT_TO_FP: in LegalizeOp()
575 case ISD::SINT_TO_FP: in Promote()
1253 if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, VT) == in ExpandUINT_TO_FLOAT()
1316 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), HI); in ExpandUINT_TO_FLOAT()
1318 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), LO); in ExpandUINT_TO_FLOAT()
H A DLegalizeDAG.cpp1001 case ISD::SINT_TO_FP: in LegalizeOp()
2297 Node->getOpcode() == ISD::SINT_TO_FP); in ExpandLegalINT_TO_FP()
2425 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or); in ExpandLegalINT_TO_FP()
2427 Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2450 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2515 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP || in PromoteLegalINT_TO_FP()
2520 unsigned SIntOp = IsStrict ? ISD::STRICT_SINT_TO_FP : ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
2928 case ISD::SINT_TO_FP: in ExpandNode()
4063 SDValue Exponent = DAG.getNode(ISD::SINT_TO_FP, SDLoc(Node), in ConvertNodeToLibcall()
4164 case ISD::SINT_TO_FP: in ConvertNodeToLibcall()
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H A DLegalizeFloatTypes.cpp133 case ISD::SINT_TO_FP: in SoftenFloatResult()
749 bool Signed = N->getOpcode() == ISD::SINT_TO_FP || in SoftenFloatRes_XINT_TO_FP()
1244 case ISD::SINT_TO_FP: in ExpandFloatResult()
1645 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP || in ExpandFloatRes_XINT_TO_FP()
2268 case ISD::SINT_TO_FP: in PromoteFloatResult()
2631 case ISD::SINT_TO_FP: in SoftPromoteHalfResult()
H A DSelectionDAGDumper.cpp346 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
H A DLegalizeVectorTypes.cpp103 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
612 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
996 case ISD::SINT_TO_FP: in SplitVectorResult()
2183 case ISD::SINT_TO_FP: in SplitVectorOperand()
3094 case ISD::SINT_TO_FP: in WidenVectorResult()
4554 case ISD::SINT_TO_FP: in WidenVectorOperand()
H A DFastISel.cpp313 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1777 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
H A DSelectionDAG.cpp4323 case ISD::SINT_TO_FP: in isKnownNeverNaN()
4619 case ISD::SINT_TO_FP: { in getNode()
4623 Opcode==ISD::SINT_TO_FP, in getNode()
4765 case ISD::SINT_TO_FP: in getNode()
4829 case ISD::SINT_TO_FP: in getNode()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DConstrainedOps.def58 DAG_INSTRUCTION(SIToFP, 1, 1, experimental_constrained_sitofp, SINT_TO_FP)
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp153 setTargetDAGCombine(ISD::SINT_TO_FP); in WebAssemblyTargetLowering()
221 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
2135 if (N->getOpcode() == ISD::SINT_TO_FP || N->getOpcode() == ISD::UINT_TO_FP) { in performVectorConvertLowCombine()
2154 unsigned Op = N->getOpcode() == ISD::SINT_TO_FP in performVectorConvertLowCombine()
2168 if (IntToFP.getOpcode() != ISD::SINT_TO_FP && in performVectorConvertLowCombine()
2180 unsigned Op = IntToFP->getOpcode() == ISD::SINT_TO_FP in performVectorConvertLowCombine()
2245 case ISD::SINT_TO_FP: in PerformDAGCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h729 SINT_TO_FP, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp236 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
237 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
259 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
485 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
499 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
637 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
645 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
668 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
678 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
864 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1513 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1515 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3028 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3378 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3385 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp399 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
434 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
1257 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1679 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2496 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2558 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext); in LowerSINT_TO_FP()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1773 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1774 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1775 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp411 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
412 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
431 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
432 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
650 setTargetDAGCombine(ISD::SINT_TO_FP); in SystemZTargetLowering()
6718 case ISD::SINT_TO_FP: in PerformDAGCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1786 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp358 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); in addMSAIntType()
1875 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()

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