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Searched refs:SETUGE (Results 1 – 25 of 50) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1354 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
1381 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp49 case ISD::SETUGE: in intCondCode2Icc()
93 case ISD::SETUGE: in fpCondCode2Fcc()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DAnalysis.cpp203 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
219 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
234 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td83 defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
H A DWebAssemblyISelLowering.cpp105 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
216 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td690 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
697 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
705 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
713 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGTU", SETUGE,
H A DRISCVInstrInfoVSDPatterns.td452 defm : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>;
455 defm : VPatIntegerSetCCSDNode_VIPlus1<SETUGE, "PseudoVMSGTU",
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3276 case ISD::SETUGE: in get32BitZExtCompare()
3449 case ISD::SETUGE: in get32BitSExtCompare()
3608 case ISD::SETUGE: in get64BitZExtCompare()
3771 case ISD::SETUGE: in get64BitSExtCompare()
4049 case ISD::SETUGE: in SelectCC()
4076 case ISD::SETUGE: in SelectCC()
4130 case ISD::SETUGE: in getPredicateForSetCC()
4155 case ISD::SETUGE: in getCRIdxForSetCC()
4189 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
4233 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
H A DPPCInstrInfo.td3733 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
4017 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
4034 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
4046 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
4063 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
4076 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
4148 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)),
4175 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)),
4214 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
4240 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
[all …]
H A DPPCInstrSPE.td850 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
871 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1429 case ISD::SETUGE: in combineFMinMaxLegacy()
1885 ISD::SETUGE); in LowerUDIVREM64()
1887 ISD::SETUGE); in LowerUDIVREM64()
1907 ISD::SETUGE); in LowerUDIVREM64()
1909 ISD::SETUGE); in LowerUDIVREM64()
1967 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
1973 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
2021 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
2028 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
H A DAMDGPUInstructions.td284 def COND_UGE : PatFrag<(ops), (OtherVT SETUGE)>;
H A DSIWholeQuadMode.cpp809 case ISD::SETUGE: in lowerKillF32()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp507 case ISD::SETUGE: in intCCToAVRCC()
620 CC = ISD::SETUGE; in getAVRCmp()
628 CC = ISD::SETUGE; in getAVRCmp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp265 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
270 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
366 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
402 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
963 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
H A DMipsDSPInstrInfo.td1431 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1444 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td95 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
115 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
H A DBPFISelLowering.cpp789 SET_NEWCC(SETUGE, JUGE); in EmitInstrWithCustomInserter()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp395 case ISD::SETUGE: in softenSetCCOperands()
3245 } else if (Cond == ISD::CondCode::SETUGE) { in optimizeSetCCOfSignedTruncationCheck()
3710 case ISD::SETUGE: in SimplifySetCC()
3735 case ISD::SETUGE: in SimplifySetCC()
3901 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
4053 (Cond == ISD::SETUGE && C1.isMinSignedValue())) in SimplifySetCC()
4129 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
4142 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
4191 case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break; in SimplifySetCC()
4360 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
[all …]
H A DSelectionDAGDumper.cpp449 case ISD::SETUGE: return "setuge"; in getOperationName()
H A DLegalizeIntegerTypes.cpp1618 case ISD::SETUGE: in PromoteSetCCOperands()
4286 case ISD::SETUGE: LowCC = ISD::SETUGE; break; in IntegerExpandSetCCOperands()
4318 CCCode == ISD::SETUGE || CCCode == ISD::SETULE); in IntegerExpandSetCCOperands()
4352 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break; in IntegerExpandSetCCOperands()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp46 case ISD::SETUGE: in ISDCCtoARCCC()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1499 case ISD::SETUGE: in TranslateIntegerM68kCC()
1549 case ISD::SETUGE: in TranslateM68kCC()
1578 case ISD::SETUGE: // flipped in TranslateM68kCC()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td728 def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">;
1334 (setcc node:$lhs, node:$rhs, SETUGE)>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp846 case ISD::SETUGE: in IntCondCCodeToICC()

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