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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h47 Register Addr;
48 Register Base;
49 Register Offset;
55 Register Base;
59 Register Reg;
66 Register LogicNonShiftReg;
115 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
120 Register ToReg) const;
156 bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
157 bool applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
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H A DUtils.h85 Register constrainRegToClass(MachineRegisterInfo &MRI,
87 const RegisterBankInfo &RBI, Register Reg,
98 Register constrainOperandRegClass(const MachineFunction &MF,
117 Register constrainOperandRegClass(const MachineFunction &MF,
141 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
165 Optional<APInt> getConstantVRegVal(Register VReg,
170 Optional<int64_t> getConstantVRegSExtVal(Register VReg,
177 Register VReg;
189 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
193 const ConstantInt *getConstantIntVRegVal(Register VReg,
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H A DCallLowering.h62 SmallVector<Register, 4> Regs;
66 SmallVector<Register, 2> OrigRegs;
74 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
87 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue,
111 Register SwiftErrorVReg;
133 Register DemoteRegister;
239 virtual Register getStackAddress(uint64_t Size, int64_t Offset,
254 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
260 virtual void assignValueToAddress(Register ValVReg, Register Addr,
268 Register Addr, uint64_t Size, in assignValueToAddress()
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H A DGISelKnownBits.h36 SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
57 virtual void computeKnownBitsImpl(Register R, KnownBits &Known,
61 unsigned computeNumSignBits(Register R, const APInt &DemandedElts,
63 unsigned computeNumSignBits(Register R, unsigned Depth = 0);
66 KnownBits getKnownBits(Register R);
67 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
72 APInt getKnownZeroes(Register R);
73 APInt getKnownOnes(Register R);
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H A DLegalizationArtifactCombiner.h53 SmallVectorImpl<Register> &UpdatedDefs) { in tryCombineAnyExt()
57 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
58 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
61 Register TruncSrc; in tryCombineAnyExt()
71 Register ExtSrc; in tryCombineAnyExt()
101 SmallVectorImpl<Register> &UpdatedDefs, in tryCombineZExt()
106 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
107 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
111 Register TruncSrc; in tryCombineZExt()
112 Register SextSrc; in tryCombineZExt()
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H A DLegalizerHelper.h117 Register coerceToScalar(Register Val);
162 Register widenWithUnmerge(LLT WideTy, Register OrigReg);
183 void extractParts(Register Reg, LLT Ty, int NumParts,
184 SmallVectorImpl<Register> &VRegs);
187 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
189 SmallVectorImpl<Register> &VRegs,
190 SmallVectorImpl<Register> &LeftoverVRegs);
201 void insertParts(Register DstReg, LLT ResultTy,
202 LLT PartTy, ArrayRef<Register> PartRegs,
203 LLT LeftoverTy = LLT(), ArrayRef<Register> LeftoverRegs = {});
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H A DMachineIRBuilder.h61 Register Reg;
68 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp()
99 Register getReg() const { in getReg()
122 Register Reg;
129 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp()
171 Register getReg() const { in getReg()
391 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
397 MachineInstrBuilder buildIndirectDbgValue(Register Reg,
482 Optional<MachineInstrBuilder> materializePtrAdd(Register &Res, Register Op0,
755 MachineInstrBuilder buildBrIndirect(Register Tgt);
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h60 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
101 IndexedMap<std::pair<Register, SmallVector<Register, 4>>,
110 MachineOperand *&getRegUseDefListHead(Register RegNo) { in getRegUseDefListHead()
116 MachineOperand *getRegUseDefListHead(Register RegNo) const { in getRegUseDefListHead()
146 std::vector<std::pair<MCRegister, Register>> LiveIns;
217 bool shouldTrackSubRegLiveness(Register VReg) const { in shouldTrackSubRegLiveness()
256 void verifyUseList(Register Reg) const;
281 reg_iterator reg_begin(Register RegNo) const { in reg_begin()
286 inline iterator_range<reg_iterator> reg_operands(Register Reg) const { in reg_operands()
294 reg_instr_iterator reg_instr_begin(Register RegNo) const { in reg_instr_begin()
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H A DVirtRegMap.h52 IndexedMap<Register, VirtReg2IndexFunctor> Virt2PhysMap;
100 bool hasPhys(Register virtReg) const { in hasPhys()
106 MCRegister getPhys(Register virtReg) const { in getPhys()
113 void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
117 bool hasShape(Register virtReg) const { in hasShape()
121 ShapeT getShape(Register virtReg) const { in getShape()
126 void assignVirt2Shape(Register virtReg, ShapeT shape) { in assignVirt2Shape()
132 void clearVirt(Register virtReg) { in clearVirt()
146 bool hasPreferredPhys(Register VirtReg) const;
151 bool hasKnownPreference(Register VirtReg) const;
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H A DFunctionLoweringInfo.h70 Register DemoteRegister;
78 DenseMap<const Value *, Register> ValueMap;
85 DenseMap<Register, const Value*> VirtReg2Value;
89 const Value *getValueFromVirtualReg(Register Vreg);
92 DenseMap<const Value *, Register> CatchPadExceptionPointers;
111 Register Reg;
139 DenseMap<Register, Register> RegFixups;
141 DenseSet<Register> RegsWithFixups;
199 Register CreateReg(MVT VT, bool isDivergent = false);
201 Register CreateRegs(const Value *V);
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H A DLiveVariables.h108 bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
151 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
156 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
157 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
163 MachineInstr *FindLastRefOrPartRef(Register Reg);
168 MachineInstr *FindLastPartialDef(Register Reg,
186 bool RegisterDefIsDead(MachineInstr &MI, Register Reg) const;
193 void replaceKillInstruction(Register Reg, MachineInstr &OldMI,
200 void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI,
210 bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI) { in removeVirtualRegisterKilled()
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H A DLiveRangeEdit.h60 virtual bool LRE_CanEraseVirtReg(Register) { return true; } in LRE_CanEraseVirtReg() argument
63 virtual void LRE_WillShrinkVirtReg(Register) {} in LRE_WillShrinkVirtReg() argument
67 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} in LRE_DidCloneVirtReg()
72 SmallVectorImpl<Register> &NewRegs;
118 void MRI_NoteNewVirtualRegister(Register VReg) override;
125 LiveInterval &createEmptyIntervalFrom(Register OldReg, bool createSubRanges);
139 LiveRangeEdit(LiveInterval *parent, SmallVectorImpl<Register> &newRegs,
156 Register getReg() const { return getParent().reg(); } in getReg()
159 using iterator = SmallVectorImpl<Register>::const_iterator;
164 Register get(unsigned idx) const { return NewRegs[idx + FirstNew]; } in get()
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H A DRegister.h19 class Register {
23 constexpr Register(unsigned Val = 0): Reg(Val) {} in Reg()
24 constexpr Register(MCRegister Val): Reg(Val) {} in Register() function
52 static int stackSlot2Index(Register Reg) { in stackSlot2Index()
58 static Register index2StackSlot(int FI) { in index2StackSlot()
60 return Register(FI + MCRegister::FirstStackSlot); in index2StackSlot()
77 static unsigned virtReg2Index(Register Reg) { in virtReg2Index()
84 static Register index2VirtReg(unsigned Index) { in index2VirtReg()
129 bool operator==(const Register &Other) const { return Reg == Other.Reg; }
130 bool operator!=(const Register &Other) const { return Reg != Other.Reg; }
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H A DFastISel.h90 Register ResultReg;
95 SmallVector<Register, 16> OutRegs;
97 SmallVector<Register, 4> InRegs;
201 DenseMap<const Value *, Register> LocalValueMap;
268 Register getRegForValue(const Value *V);
273 Register lookUpRegForValue(const Value *V);
277 Register getRegForGEPIndex(const Value *Idx);
368 Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm,
383 Register fastEmitInst_(unsigned MachineInstOpcode,
388 Register fastEmitInst_r(unsigned MachineInstOpcode,
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H A DTailDuplicator.h53 SmallVector<Register, 16> SSAUpdateVRs;
57 using AvailableValsTy = std::vector<std::pair<MachineBasicBlock *, Register>>;
59 DenseMap<Register, AvailableValsTy> SSAUpdateVals;
101 void addSSAUpdateEntry(Register OrigReg, Register NewReg,
105 DenseMap<Register, RegSubRegPair> &LocalVRMap,
106 SmallVectorImpl<std::pair<Register, RegSubRegPair>> &Copies,
107 const DenseSet<Register> &UsedByPhi, bool Remove);
110 DenseMap<Register, RegSubRegPair> &LocalVRMap,
111 const DenseSet<Register> &UsedByPhi);
118 const DenseSet<Register> &RegsUsedByPhi,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h49 Register SrcReg,
50 DenseMap<SDValue, Register> &VRBaseMap);
56 DenseMap<SDValue, Register> &VRBaseMap);
60 Register getVR(SDValue Op,
61 DenseMap<SDValue, Register> &VRBaseMap);
70 DenseMap<SDValue, Register> &VRBaseMap,
81 DenseMap<SDValue, Register> &VRBaseMap,
87 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
92 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
100 DenseMap<SDValue, Register> &VRBaseMap);
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp37 using AvailableValsTy = DenseMap<MachineBasicBlock *, Register>;
63 void MachineSSAUpdater::Initialize(Register V) { in Initialize()
75 void MachineSSAUpdater::AddAvailableValue(MachineBasicBlock *BB, Register V) { in AddAvailableValue()
81 Register MachineSSAUpdater::GetValueAtEndOfBlock(MachineBasicBlock *BB) { in GetValueAtEndOfBlock()
86 Register LookForIdenticalPHI(MachineBasicBlock *BB, in LookForIdenticalPHI()
87 SmallVectorImpl<std::pair<MachineBasicBlock *, Register>> &PredValues) { in LookForIdenticalPHI()
89 return Register(); in LookForIdenticalPHI()
93 return Register(); in LookForIdenticalPHI()
101 Register SrcReg = I->getOperand(i).getReg(); in LookForIdenticalPHI()
112 return Register(); in LookForIdenticalPHI()
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H A DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass()
63 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass()
85 MachineRegisterInfo::constrainRegClass(Register Reg, in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs()
93 Register ConstrainingReg, in constrainRegAttrs()
122 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass()
146 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { in createIncompleteVirtualRegister()
147 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister()
157 Register
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H A DTwoAddressInstructionPass.cpp114 DenseMap<Register, Register> SrcRegMap;
119 DenseMap<Register, Register> DstRegMap;
121 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
123 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
125 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131 bool isProfitableToConv3Addr(Register RegA, Register RegB);
134 MachineBasicBlock::iterator &nmi, Register RegA,
135 Register RegB, unsigned Dist);
137 bool isDefTooClose(Register Reg, unsigned Dist, MachineInstr *MI);
140 MachineBasicBlock::iterator &nmi, Register Reg);
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H A DRegAllocFast.cpp90 Register VirtReg; ///< Virtual register number.
96 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
99 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
109 DenseMap<Register, MCPhysReg> BundleVirtRegsMap;
231 Register Reg) const;
244 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg()
245 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
248 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
249 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
253 void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp121 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith()
122 Register ToReg) const { in replaceRegWith()
135 Register ToReg) const { in replaceRegOpWith()
154 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
155 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
159 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
160 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
167 SmallVector<Register, 4> Ops; in tryCombineConcatVectors()
176 SmallVectorImpl<Register> &Ops) { in matchCombineConcatVectors()
186 Register Reg = MO.getReg(); in matchCombineConcatVectors()
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H A DLegalizerHelper.cpp147 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, in extractParts()
148 SmallVectorImpl<Register> &VRegs) { in extractParts()
154 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, in extractParts()
156 SmallVectorImpl<Register> &VRegs, in extractParts()
157 SmallVectorImpl<Register> &LeftoverRegs) { in extractParts()
184 Register NewReg = MRI.createGenericVirtualRegister(MainTy); in extractParts()
191 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); in extractParts()
199 void LegalizerHelper::insertParts(Register DstReg, in insertParts()
201 ArrayRef<Register> PartRegs, in insertParts()
203 ArrayRef<Register> LeftoverRegs) { in insertParts()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.h338 Register TIDReg = AMDGPU::NoRegister;
342 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
346 Register FrameOffsetReg = AMDGPU::FP_REG;
351 Register StackPtrOffsetReg = AMDGPU::SP_REG;
442 Register VGPR;
446 SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
454 Register VGPR;
460 SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
470 MapVector<Register, Optional<int>> WWMReservedRegs;
494 Register SGPRForFPSaveRestoreCopy;
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H A DAMDGPURegisterBankInfo.h48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
51 SmallSet<Register, 4> &SGPROperandRegs,
59 SmallSet<Register, 4> &SGPROperandRegs,
87 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
88 Register Reg) const;
90 std::pair<Register, unsigned>
91 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
100 Register Ptr) const;
105 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
109 const ValueMapping *getSGPROpMapping(Register Reg,
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H A DSIOptimizeExecMaskingPreRA.cpp42 Register optimizeVcndVcmpPair(MachineBasicBlock &MBB);
91 LiveIntervals *LIS, Register Reg, in isDefBetween()
123 Register
130 return Register(); in optimizeVcndVcmpPair()
136 return Register(); in optimizeVcndVcmpPair()
139 Register CmpReg = AndCC->getReg(); in optimizeVcndVcmpPair()
141 if (CmpReg == Register(ExecReg)) { in optimizeVcndVcmpPair()
145 } else if (And->getOperand(2).getReg() != Register(ExecReg)) { in optimizeVcndVcmpPair()
146 return Register(); in optimizeVcndVcmpPair()
153 return Register(); in optimizeVcndVcmpPair()
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