| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | InfoByHwMode.cpp | 120 RegSize = R->getValueAsInt("RegSize"); in RegSizeInfo()
126 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
127 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
131 return RegSize <= I.RegSize && in isSubClassOf()
137 OS << "[R=" << RegSize << ",S=" << SpillSize in writeToStream()
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| H A D | InfoByHwMode.h | 149 unsigned RegSize; member
157 return std::tie(RegSize, SpillSize, SpillAlignment) ==
158 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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| H A D | RegisterInfoEmitter.cpp | 1080 uint32_t RegSize = 0; in runMCDesc() local
1082 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1087 << ", " << RegSize << ", " << RC.CopyCost << ", " in runMCDesc()
1289 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
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| H A D | CodeGenRegisters.cpp | 792 RI.RegSize = RI.SpillSize = Size ? Size in CodeGenRegisterClass()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
128 Size = alignTo(Size + RegSize, RegSize); in estimateStackSize()
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| H A D | MipsCallLowering.cpp | 470 unsigned RegSize = 4; in lowerFormalArguments() local
472 VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize); in lowerFormalArguments()
476 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
480 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
483 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
487 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I])); in lowerFormalArguments()
488 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
493 MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize)); in lowerFormalArguments()
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| H A D | MipsSEFrameLowering.cpp | 78 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
80 unsigned MFLoOpc, unsigned RegSize);
198 unsigned RegSize) { in expandLoadACC() argument
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC() argument
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TileConfig.cpp | 174 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY() local
175 if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16)) in INITIALIZE_PASS_DEPENDENCY()
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| H A D | X86InstrInfo.cpp | 5767 unsigned RegSize = TRI.getRegSizeInBits(*RC); in isNonFoldablePartialRegisterLoad() local
5772 RegSize > 32) { in isNonFoldablePartialRegisterLoad()
5881 RegSize > 64) { in isNonFoldablePartialRegisterLoad()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate() argument
216 (RegSize != 64 && in processLogicalImmediate()
217 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) in processLogicalImmediate()
221 unsigned Size = RegSize; in processLogicalImmediate()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfExpression.cpp | 138 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
144 SmallBitVector Coverage(RegSize, false); in addMachineReg()
155 SmallBitVector CurSubReg(RegSize, false); in addMachineReg()
179 if (CurPos < RegSize) in addMachineReg()
181 -1, RegSize - CurPos, "no DWARF register encoding")); in addMachineReg()
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/Basic/Targets/ |
| H A D | X86.h | 202 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
208 HasSizeMismatch = RegSize != 32; in validateGlobalRegisterVariable()
742 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
748 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
753 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, in validateGlobalRegisterVariable()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 511 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; in getRegSizeInBits() local
514 if (RegSize) in getRegSizeInBits()
515 return RegSize; in getRegSizeInBits()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 236 unsigned RegSize, SpillSize, SpillAlignment; member
275 return getRegClassInfo(RC).RegSize; in getRegSizeInBits()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 905 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
907 explicit operator bool() const { return RegSize; } in operator bool()
909 unsigned RegSize = 0; member
954 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
956 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
958 if (And.RegSize == 64) { in convertToThreeAddress()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1652 unsigned RegSize; in emitLogicalOp_ri() local
1663 RegSize = 32; in emitLogicalOp_ri()
1669 RegSize = 64; in emitLogicalOp_ri()
1673 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1678 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
4022 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4069 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4125 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4173 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4241 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
[all …]
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| H A D | AArch64FrameLowering.cpp | 2802 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
2805 SVECSStackSize += RegSize; in determineCalleeSaves()
2807 CSStackSize += RegSize; in determineCalleeSaves()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 264 int RegSize; in sizeOfSPAdjustment() local
267 RegSize = 8; in sizeOfSPAdjustment()
271 RegSize = 4; in sizeOfSPAdjustment()
284 count += RegSize; in sizeOfSPAdjustment()
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| /netbsd-src/external/apache2/llvm/dist/clang/include/clang/Basic/ |
| H A D | TargetInfo.h | 1045 unsigned RegSize, in validateGlobalRegisterVariable() argument
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | TargetInfo.cpp | 4774 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); in EmitVAArg() local
4776 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
4779 RegAddr.getAlignment().alignmentOfArrayElement(RegSize)); in EmitVAArg()
5913 int RegSize = IsIndirect ? 8 : TySize.getQuantity(); in EmitAAPCSVAArg() local
5919 RegSize = llvm::alignTo(RegSize, 8); in EmitAAPCSVAArg()
5925 RegSize = 16 * NumRegs; in EmitAAPCSVAArg()
5966 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); in EmitAAPCSVAArg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 269 unsigned RegSize = Ty.getSizeInBits(); in isLoadStoreSizeLegal() local
287 if (MemSize != RegSize && RegSize != 32) in isLoadStoreSizeLegal()
312 assert(RegSize >= MemSize); in isLoadStoreSizeLegal()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 4203 unsigned RegSize = Ty.getSizeInBits(); in emitTST() local
4204 bool Is32Bit = (RegSize == 32); in emitTST()
4213 if (AArch64_AM::isLogicalImmediate(Imm, RegSize)) { in emitTST()
4215 TstMI.addImm(AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitTST()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 860 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments() local
861 assert(RegSize == 32 || RegSize == 64 || in LowerFormalArguments()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 160 unsigned RegSize = RegTy.getSizeInBits(); in extractParts() local
162 unsigned NumParts = RegSize / MainSize; in extractParts()
163 unsigned LeftoverSize = RegSize - NumParts * MainSize; in extractParts()
189 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; in extractParts()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 852 unsigned RegSize = RegisterVT.getScalarSizeInBits(); in getCopyFromRegs() local
856 if (NumZeroBits == RegSize) { in getCopyFromRegs()
869 FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits); in getCopyFromRegs()
873 EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1); in getCopyFromRegs()
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