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Searched refs:RegMask (Results 1 – 25 of 55) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DRegUsageInfoPropagate.cpp64 static void setRegMask(MachineInstr &MI, ArrayRef<uint32_t> RegMask) { in setRegMask() argument
65 assert(RegMask.size() == in setRegMask()
72 MO.setRegMask(RegMask.data()); in setRegMask()
125 const ArrayRef<uint32_t> RegMask = PRUI->getRegUsageInfo(F); in runOnMachineFunction() local
126 if (RegMask.empty()) in runOnMachineFunction()
128 setRegMask(MI, RegMask); in runOnMachineFunction()
H A DRegUsageInfoCollector.cpp123 std::vector<uint32_t> RegMask; in runOnMachineFunction() local
129 RegMask.resize(RegMaskSize, ~((uint32_t)0)); in runOnMachineFunction()
142 auto SetRegAsDefined = [&RegMask] (unsigned Reg) { in runOnMachineFunction()
143 RegMask[Reg / 32] &= ~(1u << Reg % 32); in runOnMachineFunction()
183 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) in runOnMachineFunction()
190 PRUI.storeUpdateRegUsageInfo(F, RegMask); in runOnMachineFunction()
H A DRegisterUsageInfo.cpp60 const Function &FP, ArrayRef<uint32_t> RegMask) { in storeUpdateRegUsageInfo() argument
61 RegMasks[&FP] = RegMask; in storeUpdateRegUsageInfo()
78 for (const auto &RegMask : RegMasks) in print() local
79 FPRMPairVector.push_back(&RegMask); in print()
H A DLiveRegUnits.cpp22 void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) { in removeRegsNotPreserved() argument
25 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) in removeRegsNotPreserved()
31 void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) { in addRegsInMask() argument
34 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) in addRegsInMask()
H A DMachineOperand.cpp317 const uint32_t *RegMask = getRegMask(); in isIdenticalTo() local
319 if (RegMask == OtherRegMask) in isIdenticalTo()
328 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask); in isIdenticalTo()
896 const uint32_t *RegMask = getRegLiveOut(); in print() local
903 if (RegMask[Reg / 32] & (1U << (Reg % 32))) { in print()
H A DMachineCopyPropagation.cpp667 const MachineOperand *RegMask = nullptr; in ForwardCopyPropagateBlock() local
670 RegMask = &MO; in ForwardCopyPropagateBlock()
690 if (RegMask) { in ForwardCopyPropagateBlock()
699 if (!RegMask->clobbersPhysReg(Reg)) { in ForwardCopyPropagateBlock()
H A DMIRPrinter.cpp252 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, in printCustomRegMask() argument
254 assert(RegMask && "Can't print an empty register mask"); in printCustomRegMask()
260 if (RegMask[I / 32] & (1u << (I % 32))) { in printCustomRegMask()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineOperand.h174 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut. member
617 static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) { in clobbersPhysReg() argument
620 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); in clobbersPhysReg()
632 return Contents.RegMask; in getRegMask()
643 return Contents.RegMask; in getRegLiveOut()
700 Contents.RegMask = RegMaskPtr; in setRegMask()
889 Op.Contents.RegMask = Mask; in CreateRegMask()
895 Op.Contents.RegMask = Mask; in CreateRegLiveOut()
H A DLiveRegUnits.h109 void removeRegsNotPreserved(const uint32_t *RegMask);
113 void addRegsInMask(const uint32_t *RegMask);
H A DRegisterUsageInfo.h52 ArrayRef<uint32_t> RegMask);
H A DMachineRegisterInfo.h866 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { in addPhysRegsUsedFromRegMask() argument
867 UsedPhysRegMask.setBitsNotInMask(RegMask); in addPhysRegsUsedFromRegMask()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp490 static void handleRegMaskClobber(const uint32_t *RegMask, MCPhysReg Reg, in handleRegMaskClobber() argument
492 if (!MachineOperand::clobbersPhysReg(RegMask, Reg)) in handleRegMaskClobber()
503 const uint32_t *RegMask = MO.getRegMask(); in handleNormalInst() local
505 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst()
507 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst()
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Di386-opc.tbl57 #define RegMask Class=RegMask
2166 …0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2167 …0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2168 …0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2169 …0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2170 …0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2172 …W0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Word|Unspecified|BaseIndex, RegMask…
2173 …|Vex=1|Space0F|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Word|Unspecified…
2174 …, D|Modrm|Vex=1|Space0F|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
2176 …, Modrm|Vex=1|Space0F|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
[all …]
H A Di386-reg.tbl97 k0, Class=RegMask, 0, 0, 93, 118
98 k1, Class=RegMask, 0, 1, 94, 119
99 k2, Class=RegMask, 0, 2, 95, 120
100 k3, Class=RegMask, 0, 3, 96, 121
101 k4, Class=RegMask, 0, 4, 97, 122
102 k5, Class=RegMask, 0, 5, 98, 123
103 k6, Class=RegMask, 0, 6, 99, 124
104 k7, Class=RegMask, 0, 7, 100, 125
H A Di386-opc.h788 RegMask, /* Vector Mask register */ enumerator
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Di386-opc.tbl61 #define RegMask Class=RegMask
2217 …, 0x<bw:kpfx>41, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
2218 …, 0x<bw:kpfx>42, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
2219 …, 0x<bw:kpfx>45, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
2220 …, 0x<bw:kpfx>46, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
2221 …, 0x<bw:kpfx>47, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
2223 …kcpu>), Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { RegMask|<bw:elem>|Unspecified|BaseIndex, RegMa…
2224 kmov<bw>, 0x<bw:kpfx>91, APX_F(<bw:kcpu>), Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { RegMask, <bw…
2225 …w>, 0x<bw:kpfx>92, APX_F(<bw:kcpu>), D|Modrm|Vex128|EVex128|Space0F|VexW0|NoSuf, { Reg32, RegMask }
2227 knot<bw>, 0x<bw:kpfx>44, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask }
[all …]
H A Di386-reg.tbl164 k0, Class=RegMask, 0, 0, 93, 118
165 k1, Class=RegMask, 0, 1, 94, 119
166 k2, Class=RegMask, 0, 2, 95, 120
167 k3, Class=RegMask, 0, 3, 96, 121
168 k4, Class=RegMask, 0, 4, 97, 122
169 k5, Class=RegMask, 0, 5, 98, 123
170 k6, Class=RegMask, 0, 6, 99, 124
171 k7, Class=RegMask, 0, 7, 100, 125
H A Di386-opc.h818 RegMask, /* Vector Mask register */ enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp152 const uint32_t *RegMask = getCallPreservedMask(MF, CC); in getReservedRegs() local
153 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) in getReservedRegs()
H A DM68kFrameLowering.cpp178 [Reg](MachineBasicBlock::RegisterMaskPair RegMask) { in isRegLiveIn() argument
179 return RegMask.PhysReg == Reg; in isRegLiveIn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp647 const uint32_t *RegMask; in fuseCompareOperations() local
649 RegMask = MBBI->getOperand(3).getRegMask(); in fuseCompareOperations()
687 MIB.addRegMask(RegMask); in fuseCompareOperations()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp1319 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked() argument
1327 if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue; in CheckForLiveRegDefMasked()
1407 if (const uint32_t *RegMask = getNodeRegMask(Node)) in DelayForLiveRegsBottomUp() local
1408 CheckForLiveRegDefMasked(SU, RegMask, in DelayForLiveRegsBottomUp()
2846 const uint32_t *RegMask = getNodeRegMask(SU->getNode()); in canClobberReachingPhysRegUse() local
2847 if(!ImpDefs && !RegMask) in canClobberReachingPhysRegUse()
2856 if (RegMask && in canClobberReachingPhysRegUse()
2857 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp994 for (const MachineBasicBlock::RegisterMaskPair &RegMask : ExitBB->liveins()) { in ValidateLiveOuts() local
997 if (RegMask.PhysReg == ARM::VPR) in ValidateLiveOuts()
1001 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
1002 if (auto *MI = RDA.getLocalLiveOutMIDef(Header, RegMask.PhysReg)) in ValidateLiveOuts()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ExpandPseudo.cpp248 const uint32_t *RegMask = in expandCALL_RVMARKER() local
252 .addRegMask(RegMask) in expandCALL_RVMARKER()
H A DX86RegisterInfo.cpp562 const uint32_t *RegMask = getCallPreservedMask(MF, CC); in getReservedRegs() local
563 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) in getReservedRegs()

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