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Searched refs:RegC (Results 1 – 17 of 17) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp125 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
439 Register RegC, in isProfitableToCommute() argument
463 if (!isPlainlyKilled(MI, RegC, LIS)) in isProfitableToCommute()
479 MCRegister FromRegC = getMappedReg(RegC, SrcRegMap); in isProfitableToCommute()
500 if (!noUseAfterLastDef(RegC, Dist, LastDefC)) in isProfitableToCommute()
524 if (isRevCopyChain(RegC, RegA, MaxDataFlowEdge)) in isProfitableToCommute()
542 Register RegC = MI->getOperand(RegCIdx).getReg(); in commuteInstruction() local
557 MCRegister FromRegC = getMappedReg(RegC, SrcRegMap); in commuteInstruction()
H A DTargetInstrInfo.cpp848 Register RegC = OpC.getReg(); in reassociateOps() local
858 if (Register::isVirtualRegister(RegC)) in reassociateOps()
859 MRI.constrainRegClass(RegC, RC); in reassociateOps()
878 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC) in reassociateOps()
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Di386-reg.tbl23 cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
65 ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
81 rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
H A Di386-opc.h799 RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ enumerator
H A Di386-gen.c767 INSTANCE (RegC),
H A Di386-opc.tbl35 #define RegC Instance=RegC
39 #define ShiftCount RegC|Byte
1268 monitor, 0xf01c8, None, CpuSSE3, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
1270 monitor, 0xf01c8, None, CpuSSE3|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
1274 …ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword }
2069 invlpga, 0xf01df, None, CpuSVME, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegC|Dword }
3295 invlpgb, 0xf01fe, None, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword…
3315 monitorx, 0xf01fa, None, CpuMWAITX, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword…
3317 monitorx, 0xf01fa, None, CpuMWAITX|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qword, RegC|Qword, RegD|Qwor…
3321 …bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|D…
[all …]
H A DChangeLog-2019486 * i386-opc.tbl (RegC, RegD, RegB): Define.
491 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Di386-reg.tbl26 cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
100 ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
132 rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
H A Di386-opc.h829 RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ enumerator
H A Di386-opc.tbl39 #define RegC Instance=RegC
43 #define ShiftCount RegC|Byte
1368 monitor, 0xf01c8, MONITOR, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
1370 monitor, 0xf01c8, MONITOR&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
1374 mwait, 0xf01c9, MONITOR, CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Q…
2069 invlpga, 0xf01df, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword }
3041 invlpgb, 0xf01fe, INVLPGB, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
3061 monitorx, 0xf01fa, MWAITX, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
3063 monitorx, 0xf01fa, MWAITX&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
3067 mwaitx, 0xf01fb, MWAITX, CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Q…
[all …]
H A Di386-gen.c522 INSTANCE (RegC),
H A DChangeLog-2019486 * i386-opc.tbl (RegC, RegD, RegB): Define.
491 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp803 Register RegC = OpC.getReg(); in reassociateFMA() local
804 const TargetRegisterClass *RC = MRI.getRegClass(RegC); in reassociateFMA()
805 MRI.constrainRegClass(RegC, RC); in reassociateFMA()
943 get(FMAOpIdxInfo[Idx][InfoArrayIdxFAddInst]), RegC) in reassociateFMA()
985 get(FMAOpIdxInfo[Idx][InfoArrayIdxFAddInst]), RegC) in reassociateFMA()
1023 NewCRegPressure = BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), RegC) in reassociateFMA()
/netbsd-src/external/gpl3/gdb.old/dist/opcodes/
H A DChangeLog-2019486 * i386-opc.tbl (RegC, RegD, RegB): Define.
491 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
/netbsd-src/external/gpl3/gdb/dist/opcodes/
H A DChangeLog-2019486 * i386-opc.tbl (RegC, RegD, RegB): Define.
491 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
/netbsd-src/external/gpl3/binutils.old/dist/gas/config/
H A Dtc-i386.c7398 && (i.tm.operand_types[0].bitfield.instance == RegC in process_suffix()
8164 || (i.types[0].bitfield.instance == RegC in build_modrm_byte()
8167 || (i.types[0].bitfield.instance == RegC in build_modrm_byte()
/netbsd-src/external/gpl3/binutils/dist/gas/config/
H A Dtc-i386.c3450 { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" },
9504 && (i.tm.operand_types[0].bitfield.instance == RegC in process_suffix()