| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 636 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
651 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
670 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2165 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing() argument
2174 if (Reg2 == AArch64::FP) in invalidateWindowsRegisterPairing()
2178 if (Reg2 == Reg1 + 1) in invalidateWindowsRegisterPairing()
2186 (Reg1 - AArch64::X19) % 2 == 0 && Reg2 == AArch64::LR && !IsFirst) in invalidateWindowsRegisterPairing()
2195 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing() argument
2199 return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI, IsFirst); in invalidateRegisterPairing()
2204 return Reg2 == AArch64::LR; in invalidateRegisterPairing()
2213 unsigned Reg2 = AArch64::NoRegister; member
2220 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
2305 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
[all …]
|
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 198 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
201 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitStore()
211 MIB.addReg(Reg2) in emitStore()
221 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
224 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitLoad()
234 MIB.addReg(Reg2, getDefRegState(true)) in emitLoad()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 418 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
990 bool &HaveReg2, Register &Reg2, in parseAddress() argument
1065 if (parseIntegerRegister(Reg2, RegGR)) in parseAddress()
1068 if (isParsingATT() && parseRegister(Reg2)) in parseAddress()
1101 Register Reg1, Reg2; in parseAddress() local
1108 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, in parseAddress()
1147 if (parseAddressRegister(Reg2)) in parseAddress()
1149 Base = Regs[Reg2.Num]; in parseAddress()
1155 if (parseAddressRegister(Reg2)) in parseAddress()
1157 Base = Regs[Reg2.Num]; in parseAddress()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
|
| H A D | MipsAsmPrinter.cpp | 876 unsigned Reg2) { in EmitInstrRegReg() argument
885 Reg1 = Reg2; in EmitInstrRegReg()
886 Reg2 = Temp; in EmitInstrRegReg()
890 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
896 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
900 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
907 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
911 Reg1 = Reg2; in EmitMovFPIntPair()
912 Reg2 = temp; in EmitMovFPIntPair()
915 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
|
| H A D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
388 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
|
| H A D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
293 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
|
| H A D | MipsTargetStreamer.h | 134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
|
| H A D | Mips16InstrInfo.h | 120 unsigned Reg1, unsigned Reg2) const;
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
193 && Reg2 != OldFMAReg) { in processBlock()
|
| H A D | PPCVSXSwapRemoval.cpp | 897 Register Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
898 MI->getOperand(1).setReg(Reg2); in handleSpecialSwappables()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) { in addRegReg() argument
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 186 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
201 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2) in commuteInstructionImpl()
209 Reg0 = Reg2; in commuteInstructionImpl()
211 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
232 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
245 if (Register::isPhysicalRegister(Reg2)) in commuteInstructionImpl()
|
| H A D | AggressiveAntiDepBreaker.h | 105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
|
| H A D | AggressiveAntiDepBreaker.cpp | 89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
95 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 760 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
763 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
765 if (Reg0 != Reg2) { in ReduceTo2Addr()
795 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
796 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
|
| H A D | A15SDOptimizer.cpp | 83 unsigned Reg2);
448 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
456 .addReg(Reg2) in createRegSequence()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 100 bool contains(Register Reg1, Register Reg2) const { in contains() argument
103 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
105 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 221 unsigned Reg2, SMLoc IDLoc, in emitRRR() argument
223 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
227 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
233 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 78 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
79 return contains(Reg1) && contains(Reg2); in contains()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCDwarf.cpp | 1348 unsigned Reg2 = Instr.getRegister2(); in emitCFIInstruction() local
1351 Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); in emitCFIInstruction()
1355 Streamer.emitULEB128IntValue(Reg2); in emitCFIInstruction()
|
| /netbsd-src/games/warp/ |
| H A D | config.h.SH | 214 * This symbol, along with Reg2, Reg3, etc. is either the word "register"
|
| /netbsd-src/sys/arch/hpc/stand/hpcboot/arm/ |
| H A D | arm.asm | 225 ; Reg2 Translation table base (R/W)
|
| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1396 CodeGenRegister *Reg2 = I1.second; in computeComposites() local
1398 if (&Reg1 == Reg2) in computeComposites()
1400 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1406 if (Reg2 == Reg3) in computeComposites()
|