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Searched refs:RC1 (Results 1 – 16 of 16) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonPatternsV65.td40 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
44 ModRegs:$Mu, RC1:$Vv),
49 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
53 ModRegs:$Mu, RC1:$Vv),
58 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
62 ModRegs:$Mu, RC1:$Vv),
H A DHexagonGenInsert.cpp341 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
342 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
344 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i]; in operator ()()
358 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); in operator ()() local
360 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
374 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2]; in operator ()()
H A DHexagonBitSimplify.cpp203 static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
314 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual() argument
319 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0) in isEqual()
324 if (RC1[B1+i] != RC2[B2+i]) in isEqual()
/netbsd-src/external/bsd/file/dist/magic/magdir/
H A Dvorbis94 # Post-RC1 Ogg files have the second header packet (and thus the version)
109 >>>>>>>(84.b+120) string <20010615 (beta4-RC1)
110 >>>>>>(84.b+120) string 20010615 (1.0 RC1)
124 >>>>>>(84.b+117) string 20040629 (1.1.0 RC1)
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dmt-opc.c562 …,', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (RC1), ',', '#', OP (CBR…
568 …{ { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (RC1), ',', '#', OP …
622 … ',', OP (FRSR2), ',', '#', OP (BALL2), ',', '#', OP (BRC2), ',', '#', OP (RC1), ',', '#', OP (CBR…
628 …, '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBR…
634 … '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBR…
664 …',', '#', OP (RBBC), ',', OP (FRSR1), ',', '#', OP (COLNUM), ',', '#', OP (RC1), ',', '#', OP (CBR…
670 …{ { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (INCAMT), ',', '#', OP (RC1), ',', '#…
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dmt-opc.c562 …,', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (RC1), ',', '#', OP (CBR…
568 …{ { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (RC1), ',', '#', OP …
622 … ',', OP (FRSR2), ',', '#', OP (BALL2), ',', '#', OP (BRC2), ',', '#', OP (RC1), ',', '#', OP (CBR…
628 …, '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBR…
634 … '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBR…
664 …',', '#', OP (RBBC), ',', OP (FRSR1), ',', '#', OP (COLNUM), ',', '#', OP (RC1), ',', '#', OP (CBR…
670 …{ { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (INCAMT), ',', '#', OP (RC1), ',', '#…
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp2142 CodeGenRegisterClass *RC1 = RC; in inferCommonSubClass() local
2144 if (RC1 == RC2) in inferCommonSubClass()
2148 const CodeGenRegister::Vec &Memb1 = RC1->getMembers(); in inferCommonSubClass()
2162 if (RC2->RSI.hasStricterSpillThan(RC1->RSI)) in inferCommonSubClass()
2163 std::swap(RC1, RC2); in inferCommonSubClass()
2165 getOrCreateSubClass(RC1, &Intersection, in inferCommonSubClass()
2166 RC1->getName() + "_and_" + RC2->getName()); in inferCommonSubClass()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DRegAllocFast.cpp1191 const TargetRegisterClass &RC1 = *MRI->getRegClass(Reg1); in allocateInstruction() local
1196 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in allocateInstruction()
1199 bool SmallClass1 = ClassSize1 < RegClassDefCounts[RC1.getID()]; in allocateInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DReleaseProcess.rst42 fixed between RC1 and RC2, but not so much at the end of it.
H A DHowToReleaseLLVM.rst296 #. *Before RC1* Patches should be limited to bug fixes, important optimization
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp864 auto RC1 = MRI.getRegClass(SrcReg1); in PPCEmitCmp() local
885 if (isVSSRCRegClass(RC1)) in PPCEmitCmp()
905 } else if (isVSFRCRegClass(RC1) || (RC2 && isVSFRCRegClass(RC2))) { in PPCEmitCmp()
/netbsd-src/external/bsd/ntp/dist/
H A DREADME.leapsmear258 version="ntpd 4.2.8p3-RC1@1.3349-o Mon Jun 22 14:24:09 UTC 2015 (26)",
/netbsd-src/sys/external/isc/libsodium/dist/
H A DChangeLog344 * Version 0.7.0 (1.0 RC1)
/netbsd-src/external/apache2/llvm/dist/clang/lib/Sema/
H A DSemaOverload.cpp9779 Expr *RC1 = Cand1.Function->getTrailingRequiresClause(); in isBetterOverloadCandidate() local
9781 if (RC1 && RC2) { in isBetterOverloadCandidate()
9783 if (S.IsAtLeastAsConstrained(Cand1.Function, {RC1}, Cand2.Function, in isBetterOverloadCandidate()
9786 {RC1}, AtLeastAsConstrained2)) in isBetterOverloadCandidate()
9790 } else if (RC1 || RC2) { in isBetterOverloadCandidate()
9791 return RC1 != nullptr; in isBetterOverloadCandidate()
/netbsd-src/crypto/external/bsd/heimdal/dist/
H A DChangeLog.1999462 SSPI Code' in Windows 2000 RC1 SDK.
H A DChangeLog.2006426 * configure.in: heimdal 0.8-RC1