| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 248 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
249 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitPrologue()
253 .addReg(OffsetReg); in emitPrologue()
300 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
301 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitEpilogue()
309 .addReg(OffsetReg); in emitEpilogue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 51 unsigned OffsetReg,
57 unsigned OffsetReg,
247 unsigned OffsetReg) const;
255 unsigned OffsetReg) const;
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| H A D | R600InstrInfo.cpp | 1018 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1019 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1024 OffsetReg); in expandPostRAPseudo()
1032 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1033 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1039 OffsetReg); in expandPostRAPseudo()
1094 unsigned OffsetReg) const { in buildIndirectWrite()
1095 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1101 unsigned OffsetReg, in buildIndirectWrite() argument
1112 R600::AR_X, OffsetReg); in buildIndirectWrite()
[all …]
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| H A D | AMDGPUCallLowering.cpp | 203 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress() local
205 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
408 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr() local
410 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| H A D | SIRegisterInfo.cpp | 694 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
700 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
707 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
713 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
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| H A D | AMDGPUInstructionSelector.cpp | 3434 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSmrdSgpr() local
3435 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg) in selectSmrdSgpr()
3439 [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); } in selectSmrdSgpr()
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| H A D | AMDGPURegisterBankInfo.cpp | 1558 Register OffsetReg = MI.getOperand(3).getReg(); in applyMappingBFEIntrinsic() local
1568 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask); in applyMappingBFEIntrinsic()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 132 unsigned OffsetReg; member
178 return Mem.OffsetReg; in getMemOffsetReg()
618 Op->Mem.OffsetReg = 0; in MorphToMemImm()
626 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
630 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
642 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | X86ISelLowering.cpp | 32161 unsigned OffsetReg = 0; in EmitVAARGWithCustomInserter() local
32215 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); in EmitVAARGWithCustomInserter()
32216 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) in EmitVAARGWithCustomInserter()
32226 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
32237 assert(OffsetReg != 0); in EmitVAARGWithCustomInserter()
32257 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
32267 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
32274 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| H A D | ARMCallLowering.cpp | 103 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | Thumb2InstrInfo.cpp | 611 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
612 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 248 unsigned OffsetReg; member
339 return Mem.OffsetReg; in getMemOffsetReg()
528 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
537 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
549 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 269 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
271 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | MipsSEInstrInfo.cpp | 895 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
909 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); in expandEhReturn()
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| H A D | MipsISelLowering.cpp | 2545 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
2547 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
2550 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 166 Register OffsetReg = MI.getOperand(2).getReg(); in canRemoveAddasl() local
171 if (OffsetReg == RR.Reg) { in canRemoveAddasl()
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| H A D | HexagonISelLowering.cpp | 3101 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
3107 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); in LowerEH_RETURN()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 255 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress() local
257 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | AArch64InstructionSelector.cpp | 5252 Register OffsetReg = OffsetInst->getOperand(1).getReg(); in selectExtendedSHL() local
5262 std::swap(OffsetReg, ConstantReg); in selectExtendedSHL()
5295 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
5304 OffsetReg = ExtInst->getOperand(1).getReg(); in selectExtendedSHL()
5309 OffsetReg = moveScalarRegClass(OffsetReg, AArch64::GPR32RegClass, MIB); in selectExtendedSHL()
5315 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); }, in selectExtendedSHL()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 94 unsigned OffsetReg = 0; member in __anona45ed14d0111::AArch64FastISel::Address
120 OffsetReg = Reg; in setOffsetReg()
124 return OffsetReg; in getOffsetReg()
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