| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 143 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
144 void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
149 bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
150 void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
156 bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
157 bool applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
241 bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
242 bool applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
245 bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
246 bool applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPreLegalizerCombiner.cpp | 51 ClampI64ToI16MatchInfo &MatchInfo);
54 const ClampI64ToI16MatchInfo &MatchInfo);
59 ClampI64ToI16MatchInfo &MatchInfo) { in matchClampI64ToI16() argument
73 auto IsApplicableForCombine = [&MatchInfo]() -> bool { in matchClampI64ToI16()
74 const auto Cmp1 = MatchInfo.Cmp1; in matchClampI64ToI16()
75 const auto Cmp2 = MatchInfo.Cmp2; in matchClampI64ToI16()
93 m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) { in matchClampI64ToI16()
95 m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) { in matchClampI64ToI16()
101 m_GSMax(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) { in matchClampI64ToI16()
103 m_GSMin(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) { in matchClampI64ToI16()
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| H A D | AMDGPURegBankCombiner.cpp | 64 bool matchIntMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
65 void applyMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
109 MachineInstr &MI, Med3MatchInfo &MatchInfo) { in matchIntMinMaxToMed3() argument
130 MatchInfo = {OpcodeTriple.Med, Val, K0, K1}; in matchIntMinMaxToMed3()
135 Med3MatchInfo &MatchInfo) { in applyMed3() argument
137 B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)}, in applyMed3()
138 {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2}, MI.getFlags()); in applyMed3()
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| H A D | AMDGPUPostLegalizerCombiner.cpp | 66 bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo);
68 const CvtF32UByteMatchInfo &MatchInfo);
205 MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo) { in matchCvtF32UByteN() argument
223 MatchInfo.CvtVal = Src0; in matchCvtF32UByteN()
224 MatchInfo.ShiftOffset = ShiftOffset; in matchCvtF32UByteN()
233 MachineInstr &MI, const CvtF32UByteMatchInfo &MatchInfo) { in applyCvtF32UByteN() argument
235 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN()
238 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN()
239 LLT SrcTy = MRI.getType(MatchInfo.CvtVal); in applyCvtF32UByteN()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 219 ShuffleVectorPseudo &MatchInfo) { in matchREV() argument
235 MatchInfo = ShuffleVectorPseudo(AArch64::G_REV64, Dst, {Src}); in matchREV()
248 ShuffleVectorPseudo &MatchInfo) { in matchTRN() argument
259 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchTRN()
269 ShuffleVectorPseudo &MatchInfo) { in matchUZP() argument
280 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchUZP()
285 ShuffleVectorPseudo &MatchInfo) { in matchZip() argument
296 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2}); in matchZip()
303 ShuffleVectorPseudo &MatchInfo) { in matchDupFromInsertVectorElt() argument
334 MatchInfo = ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), in matchDupFromInsertVectorElt()
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| H A D | AArch64PostLegalizerCombiner.cpp | 52 std::tuple<unsigned, LLT, Register> &MatchInfo) { in matchExtractVecEltPairwiseAdd() argument
85 std::get<0>(MatchInfo) = TargetOpcode::G_FADD; in matchExtractVecEltPairwiseAdd()
86 std::get<1>(MatchInfo) = DstTy; in matchExtractVecEltPairwiseAdd()
87 std::get<2>(MatchInfo) = Other->getOperand(0).getReg(); in matchExtractVecEltPairwiseAdd()
95 std::tuple<unsigned, LLT, Register> &MatchInfo) { in applyExtractVecEltPairwiseAdd() argument
96 unsigned Opc = std::get<0>(MatchInfo); in applyExtractVecEltPairwiseAdd()
99 LLT Ty = std::get<1>(MatchInfo); in applyExtractVecEltPairwiseAdd()
100 Register Src = std::get<2>(MatchInfo); in applyExtractVecEltPairwiseAdd()
246 std::function<void(MachineIRBuilder &)> &MatchInfo) { in matchBitfieldExtractFromSExtInReg() argument
263 MatchInfo = [=](MachineIRBuilder &B) { in matchBitfieldExtractFromSExtInReg()
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| H A D | AArch64PreLegalizerCombiner.cpp | 65 GISelKnownBits *KB, Register &MatchInfo) { in matchICmpRedundantTrunc() argument
89 MatchInfo = WideReg; in matchICmpRedundantTrunc()
117 std::pair<uint64_t, uint64_t> &MatchInfo) { in matchFoldGlobalOffset() argument
178 MatchInfo = std::make_pair(NewOffset, MinOffset); in matchFoldGlobalOffset()
185 std::pair<uint64_t, uint64_t> &MatchInfo) { in applyFoldGlobalOffset() argument
207 std::tie(Offset, MinOffset) = MatchInfo; in applyFoldGlobalOffset()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 691 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in matchSextInRegOfLoad() argument
721 MatchInfo = std::make_tuple(LoadDef->getOperand(0).getReg(), NewSizeBits); in matchSextInRegOfLoad()
726 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in applySextInRegOfLoad() argument
730 std::tie(LoadReg, ScalarSizeBits) = MatchInfo; in applySextInRegOfLoad()
881 IndexedLoadStoreMatchInfo MatchInfo; in tryCombineIndexedLoadStore() local
882 if (matchCombineIndexedLoadStore(MI, MatchInfo)) { in tryCombineIndexedLoadStore()
883 applyCombineIndexedLoadStore(MI, MatchInfo); in tryCombineIndexedLoadStore()
889 …binerHelper::matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) { in matchCombineIndexedLoadStore() argument
900 MatchInfo.IsPre = findPreIndexCandidate(MI, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()
901 MatchInfo.Offset); in matchCombineIndexedLoadStore()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/FileCheck/ |
| H A D | FileCheck.cpp | 1289 SmallVector<StringRef, 4> MatchInfo; in match() local
1293 if (!Regex(RegExToMatch, Flags).match(Buffer, &MatchInfo)) in match()
1297 assert(!MatchInfo.empty() && "Didn't get any match"); in match()
1298 StringRef FullMatch = MatchInfo[0]; in match()
1302 assert(VariableDef.second < MatchInfo.size() && "Internal paren error"); in match()
1304 MatchInfo[VariableDef.second]; in match()
1320 assert(CaptureParenGroup < MatchInfo.size() && "Internal paren error"); in match()
1324 StringRef MatchedValue = MatchInfo[CaptureParenGroup]; in match()
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| /netbsd-src/external/public-domain/sqlite/dist/ |
| H A D | sqlite3.c | 200776 typedef struct MatchInfo MatchInfo;
200777 struct MatchInfo {
201553 MatchInfo *p /* Matchinfo context */
201591 MatchInfo *p
201638 MatchInfo *p = (MatchInfo *)pCtx;
201655 MatchInfo *p = (MatchInfo *)pCtx;
201693 static size_t fts3MatchinfoSize(MatchInfo *pInfo, char cArg){
201829 static int fts3MatchinfoLcs(Fts3Cursor *pCsr, MatchInfo *pInfo){
201920 MatchInfo *pInfo, /* Matchinfo context object */
202044 MatchInfo sInfo;
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