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Searched refs:MCRegister (Results 1 – 25 of 157) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCRegisterInfo.h68 bool contains(MCRegister Reg) const { in contains()
78 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains()
158 MCRegister RAReg; // Return address register
159 MCRegister PCReg; // Program counter register
185 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
186 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
215 MCRegister advance() { in advance()
227 MCRegister operator*() const { return Val; }
252 mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList) { in mc_difflist_iterator()
290 mc_subreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI) in mc_subreg_iterator()
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H A DMCRegister.h22 class MCRegister {
23 friend hash_code hash_value(const MCRegister &);
27 constexpr MCRegister(unsigned Val = 0): Reg(Val) {} in Reg()
65 static MCRegister from(unsigned Val) { in from()
67 return MCRegister(Val); in from()
77 bool operator==(const MCRegister &Other) const { return Reg == Other.Reg; }
78 bool operator!=(const MCRegister &Other) const { return Reg != Other.Reg; }
94 template<> struct DenseMapInfo<MCRegister> {
101 static unsigned getHashValue(const MCRegister &Val) {
104 static bool isEqual(const MCRegister &LHS, const MCRegister &RHS) {
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegister.h24 constexpr Register(MCRegister Val): Reg(Val) {} in Register()
45 return MCRegister::isStackSlot(Reg); in isStackSlot()
49 bool isStack() const { return MCRegister::isStackSlot(Reg); } in isStack()
54 return int(Reg - MCRegister::FirstStackSlot); in stackSlot2Index()
60 return Register(FI + MCRegister::FirstStackSlot); in index2StackSlot()
66 return MCRegister::isPhysicalRegister(Reg); in isPhysicalRegister()
72 return Reg & MCRegister::VirtualRegFlag && !isStackSlot(Reg); in isVirtualRegister()
79 return Reg & ~MCRegister::VirtualRegFlag; in virtReg2Index()
86 return Index | MCRegister::VirtualRegFlag; in index2VirtReg()
113 operator MCRegister() const { in MCRegister() function
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H A DReachingDefAnalysis.h142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
146 MCRegister PhysReg) const;
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
155 MCRegister PhysReg) const;
160 MCRegister PhysReg) const;
172 bool hasLocalDefBefore(MachineInstr *MI, MCRegister PhysReg) const;
176 bool isRegUsedAfter(MachineInstr *MI, MCRegister PhysReg) const;
179 bool isRegDefinedAfter(MachineInstr *MI, MCRegister PhysReg) const;
183 int getClearance(MachineInstr *MI, MCRegister PhysReg) const;
187 void getReachingLocalUses(MachineInstr *MI, MCRegister PhysReg,
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H A DLiveRegMatrix.h107 InterferenceKind checkInterference(LiveInterval &VirtReg, MCRegister PhysReg);
114 bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);
119 void assign(LiveInterval &VirtReg, MCRegister PhysReg);
127 bool isPhysRegUsed(MCRegister PhysReg) const;
140 MCRegister PhysReg = MCRegister::NoRegister);
145 bool checkRegUnitInterference(LiveInterval &VirtReg, MCRegister PhysReg);
151 LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit);
H A DTargetRegisterInfo.h85 MCRegister getRegister(unsigned i) const { in getRegister()
327 const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
334 const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg,
359 bool isInAllocatableClass(MCRegister RegNo) const { in isInAllocatableClass()
433 bool hasRegUnit(MCRegister Reg, Register RegUnit) const { in hasRegUnit()
534 MCRegister PhysReg) const { in isAsmClobberable()
546 virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; } in isConstantPhysReg()
558 virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, in isCallerPreservedPhysReg()
565 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
575 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
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H A DCallingConvLower.h277 bool isAllocated(MCRegister Reg) const { in isAllocated()
328 bool IsShadowAllocatedReg(MCRegister Reg) const;
351 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg()
353 return MCRegister(); in AllocateReg()
359 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg()
361 return MCRegister(); in AllocateReg()
373 return MCRegister(); // Didn't find the reg. in AllocateReg()
411 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
414 return MCRegister(); // Didn't find the reg. in AllocateReg()
417 MCRegister Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg()
H A DMachineRegisterInfo.h146 std::vector<std::pair<MCRegister, Register>> LiveIns;
235 void disableCalleeSavedRegister(MCRegister Reg);
620 bool isConstantPhysReg(MCRegister PhysReg) const;
826 void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, in updateDbgUsersToReg()
828 SmallSet<MCRegister, 4> OldRegUnits; in updateDbgUsersToReg()
856 bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
862 bool isPhysRegUsed(MCRegister PhysReg) const;
897 bool canReserveReg(MCRegister PhysReg) const { in canReserveReg()
915 bool isReserved(MCRegister PhysReg) const { in isReserved()
933 bool isAllocatable(MCRegister PhysReg) const { in isAllocatable()
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H A DRegisterClassInfo.h116 MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const { in getLastCalleeSavedAlias()
119 return MCRegister::NoRegister; in getLastCalleeSavedAlias()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp91 SmallVector<MCRegister, 4> DefRegs;
95 DenseMap<MCRegister, CopyInfo> Copies;
100 void markRegsUnavailable(ArrayRef<MCRegister> Regs, in markRegsUnavailable()
102 for (MCRegister Reg : Regs) { in markRegsUnavailable()
113 void invalidateRegister(MCRegister Reg, const TargetRegisterInfo &TRI) { in invalidateRegister()
117 SmallSet<MCRegister, 8> RegsToInvalidate; in invalidateRegister()
130 for (MCRegister InvalidReg : RegsToInvalidate) in invalidateRegister()
136 void clobberRegister(MCRegister Reg, const TargetRegisterInfo &TRI) { in clobberRegister()
157 MCRegister Def = MI->getOperand(0).getReg().asMCReg(); in trackCopy()
158 MCRegister Src = MI->getOperand(1).getReg().asMCReg(); in trackCopy()
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H A DLiveRegMatrix.cpp81 LiveInterval &VRegInterval, MCRegister PhysReg, in foreachUnit()
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) { in assign()
138 bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const { in isPhysRegUsed()
147 MCRegister PhysReg) { in checkRegMaskInterference()
165 MCRegister PhysReg) { in checkRegUnitInterference()
179 MCRegister RegUnit) { in query()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, MCRegister PhysReg) { in checkInterference()
200 [&](MCRegister Unit, const LiveRange &LR) { in checkInterference()
210 MCRegister PhysReg) { in checkInterference()
246 return MCRegister::NoRegister; in getOneVReg()
H A DReachingDefAnalysis.cpp33 static bool isValidRegUseOf(const MachineOperand &MO, MCRegister PhysReg) { in isValidRegUseOf()
41 static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg) { in isValidRegDefOf()
258 MCRegister PhysReg) const { in getReachingDef()
279 MCRegister PhysReg) const { in getReachingLocalMIDef()
286 MCRegister PhysReg) const { in hasSameReachingDef()
315 MCRegister PhysReg) const { in getClearance()
321 MCRegister PhysReg) const { in hasLocalDefBefore()
326 MCRegister PhysReg, in getReachingLocalUses()
351 MCRegister PhysReg, in getLiveInUses()
369 void ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, MCRegister PhysReg, in getGlobalUses()
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H A DRegAllocGreedy.cpp295 std::pair<Register /* evictor */, MCRegister /* physreg */>;
319 void addEviction(MCRegister PhysReg, Register Evictor, Register Evictee) { in addEviction()
353 MCRegister PhysReg;
365 void reset(InterferenceCache &Cache, MCRegister Reg) { in reset()
426 MCRegister selectOrSplit(LiveInterval &,
446 MCRegister selectOrSplitImpl(LiveInterval &, SmallVectorImpl<Register> &,
470 void calcGapWeights(MCRegister, SmallVectorImpl<float> &);
473 bool canEvictInterference(LiveInterval &, MCRegister, bool, EvictionCost &,
476 MCRegister PhysReg, SlotIndex Start,
478 MCRegister getCheapestEvicteeWeight(const AllocationOrder &Order,
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H A DInterferenceCache.h47 MCRegister PhysReg = 0;
105 PhysReg = MCRegister::NoRegister; in clear()
111 MCRegister getPhysReg() const { return PhysReg; } in getPhysReg()
123 void reset(MCRegister physReg, LiveIntervalUnion *LIUArray,
155 Entry *get(MCRegister PhysReg);
208 void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) { in setPhysReg()
H A DRegAllocBasic.cpp103 MCRegister selectOrSplit(LiveInterval &VirtReg,
122 bool spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
209 bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg, in spillInterferences()
261 MCRegister RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
264 SmallVector<MCRegister, 8> PhysRegSpillCands; in selectOrSplit()
269 for (MCRegister PhysReg : Order) { in selectOrSplit()
289 for (MCRegister &PhysReg : PhysRegSpillCands) { in selectOrSplit()
H A DMachineRegisterInfo.cpp437 for (const std::pair<MCRegister, Register> &LI : liveins()) in isLiveIn()
445 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { in getLiveInPhysReg()
446 for (const std::pair<MCRegister, Register> &LI : liveins()) in getLiveInPhysReg()
449 return MCRegister(); in getLiveInPhysReg()
454 Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const { in getLiveInVirtReg()
455 for (const std::pair<MCRegister, Register> &LI : liveins()) in getLiveInVirtReg()
513 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { in isConstantPhysReg()
570 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, in isPhysRegModified()
585 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg) const { in isPhysRegUsed()
597 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { in disableCalleeSavedRegister()
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H A DRegAllocPBQP.cpp415 MCRegister PRegN = NRegs[I]; in createInterferenceEdge()
417 MCRegister PRegM = MRegs[J]; in createInterferenceEdge()
510 MCRegister PReg1 = Allowed1[I]; in addVirtRegCoalesce()
512 MCRegister PReg2 = Allowed2[J]; in addVirtRegCoalesce()
580 static bool isACalleeSavedRegister(MCRegister Reg, in isACalleeSavedRegister()
601 std::map<Register, std::vector<MCRegister>> VRegAllowedMap; in initializeGraph()
624 std::vector<MCRegister> VRegAllowed; in initializeGraph()
627 MCRegister PReg(RawPRegOrder[I]); in initializeGraph()
738 MCRegister PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOpt - 1]; in mapPBQPToRegAlloc()
769 for (MCRegister CandidateReg : RawPRegOrder) { in finalizeAlloc()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCRegisterInfo.cpp23 MCRegister
24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg()
44 unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg, in getSubRegIndex()
45 MCRegister SubReg) const { in getSubRegIndex()
68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum()
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const { in getSEHRegNum()
110 const DenseMap<MCRegister, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
115 int MCRegisterInfo::getCodeViewRegNum(MCRegister RegNum) const { in getCodeViewRegNum()
118 const DenseMap<MCRegister, int>::const_iterator I = L2CVRegs.find(RegNum); in getCodeViewRegNum()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h48 void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
63 MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
133 StringRef getRegAsmName(MCRegister Reg) const override;
136 unsigned getHWRegIndex(MCRegister Reg) const { in getHWRegIndex()
151 const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const;
222 MCRegister findUnusedRegister(const MachineRegisterInfo &MRI,
235 bool isConstantPhysReg(MCRegister PhysReg) const override;
260 MCRegister getReturnAddressReg(const MachineFunction &MF) const;
292 MCRegister getVCC() const;
355 MCRegister ScratchOffsetReg, int64_t InstrOffset,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.h29 class MCRegister; variable
120 MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false);
124 MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp73 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRRegisterClass()
84 MCRegister Reg = RISCV::F0_H + RegNo; in DecodeFPR16RegisterClass()
95 MCRegister Reg = RISCV::F0_F + RegNo; in DecodeFPR32RegisterClass()
106 MCRegister Reg = RISCV::F8_F + RegNo; in DecodeFPR32CRegisterClass()
117 MCRegister Reg = RISCV::F0_D + RegNo; in DecodeFPR64RegisterClass()
128 MCRegister Reg = RISCV::F8_D + RegNo; in DecodeFPR64CRegisterClass()
159 MCRegister Reg = RISCV::X8 + RegNo; in DecodeGPRCRegisterClass()
170 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass()
187 MCRegister Reg = in DecodeVRM2RegisterClass()
207 MCRegister Reg = in DecodeVRM4RegisterClass()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h37 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
95 MCRegister PhysReg) const override;
96 bool isConstantPhysReg(MCRegister PhysReg) const override;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.h52 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.h41 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h34 MCRegister PhysReg) const override;
36 bool isConstantPhysReg(MCRegister PhysReg) const override;

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