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Searched refs:LoadedVT (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1580 EVT LoadedVT = LD->getMemoryVT(); in tryARMIndexedLoad() local
1585 if (LoadedVT == MVT::i32 && isPre && in tryARMIndexedLoad()
1589 } else if (LoadedVT == MVT::i32 && !isPre && in tryARMIndexedLoad()
1593 } else if (LoadedVT == MVT::i32 && in tryARMIndexedLoad()
1598 } else if (LoadedVT == MVT::i16 && in tryARMIndexedLoad()
1604 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { in tryARMIndexedLoad()
1655 EVT LoadedVT = LD->getMemoryVT(); in tryT1IndexedLoad() local
1658 LoadedVT.getSimpleVT().SimpleTy != MVT::i32) in tryT1IndexedLoad()
1686 EVT LoadedVT = LD->getMemoryVT(); in tryT2IndexedLoad() local
1693 switch (LoadedVT.getSimpleVT().SimpleTy) { in tryT2IndexedLoad()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp843 EVT LoadedVT = LD->getMemoryVT(); in tryLoad() local
850 if (!LoadedVT.isSimple()) in tryLoad()
885 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad()
894 assert(LoadedVT == MVT::v2f16 && "Unexpected vector type"); in tryLoad()
1000 EVT LoadedVT = MemSD->getMemoryVT(); in tryLoadVector() local
1002 if (!LoadedVT.isSimple()) in tryLoadVector()
1023 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp71 EVT LoadedVT = LD->getMemoryVT(); in SelectIndexedLoad() local
78 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc); in SelectIndexedLoad()
80 assert(LoadedVT.isSimple()); in SelectIndexedLoad()
81 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectIndexedLoad()
152 assert(LoadedVT.getSizeInBits() <= 32); in SelectIndexedLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5123 EVT LoadedVT = LD->getMemoryVT(); in Select() local
5142 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5143 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5154 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5155 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5179 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5180 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5191 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
5193 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp7466 EVT LoadedVT = LD->getMemoryVT(); in expandUnalignedLoad() local
7471 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in expandUnalignedLoad()
7472 if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) { in expandUnalignedLoad()
7474 LoadedVT.isVector()) { in expandUnalignedLoad()
7483 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in expandUnalignedLoad()
7484 if (LoadedVT != VT) in expandUnalignedLoad()
7494 unsigned LoadedBytes = LoadedVT.getStoreSize(); in expandUnalignedLoad()
7499 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
7550 LoadedVT); in expandUnalignedLoad()
7556 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && in expandUnalignedLoad()
[all …]
H A DDAGCombiner.cpp5199 EVT LoadedVT = LoadN->getMemoryVT(); in isAndLoadExtLoad() local
5201 if (ExtVT == LoadedVT && in isAndLoadExtLoad()
5215 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()