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Searched refs:Latency (Results 1 – 25 of 129) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td14 // Latency: #cyc
26 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
27 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
28 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
29 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
30 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
32 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
34 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
36 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
38 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
[all …]
H A DARMScheduleM7.td36 // ReadAdvance<0> (the default) for their source operands and Latency = 1.
56 def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
59 let Latency = 1 in {
66 def : WriteRes<WriteCMP, [M7UnitALU]> { let Latency = 1; }
67 def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
68 def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
71 let Latency = 2 in {
79 let Latency = 2 in {
82 def : WriteRes<WriteMAC64Lo, [M7UnitMAC]> { let Latency = 2; }
89 let Latency = 7;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedA57WriteRes.td14 // Latency: #cyc
29 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
30 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
31 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
32 def A57Write_5cyc_1V_FP_Forward : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
33 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
34 def A57Write_5cyc_1W_Mul_Forward : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
35 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
36 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
38 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
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H A DAArch64SchedKryoDetails.td16 let Latency = 3; let NumMicroOps = 2;
23 let Latency = 3; let NumMicroOps = 2;
30 let Latency = 4; let NumMicroOps = 3;
36 let Latency = 4; let NumMicroOps = 4;
42 let Latency = 3; let NumMicroOps = 4;
48 let Latency = 3; let NumMicroOps = 2;
54 let Latency = 3; let NumMicroOps = 2;
60 let Latency = 3; let NumMicroOps = 2;
66 let Latency = 3; let NumMicroOps = 2;
72 let Latency = 3; let NumMicroOps = 2;
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H A DAArch64SchedKryo.td64 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
65 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
67 { let Latency = 2; let NumMicroOps = 2; }
69 { let Latency = 2; let NumMicroOps = 2; }
71 { let Latency = 2; let NumMicroOps = 2; }
72 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
74 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
76 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
77 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
78 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }
[all …]
H A DAArch64SchedExynosM4.td134 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
135 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
137 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
140 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
141 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
142 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
145 M4UnitC]> { let Latency = 2;
149 M4UnitC]> { let Latency = 3;
152 M4UnitC]> { let Latency = 2;
154 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
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H A DAArch64SchedExynosM3.td109 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
111 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
114 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
115 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
118 M3UnitC]> { let Latency = 1;
122 M3UnitC]> { let Latency = 2;
125 M3UnitC]> { let Latency = 2;
127 def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; }
128 def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; }
145 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
[all …]
H A DAArch64SchedExynosM5.td134 def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
135 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
137 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
140 def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
141 def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
142 def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
144 def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
148 M5UnitE]> { let Latency = 2;
152 M5UnitC]> { let Latency = 3;
155 M5UnitC]> { let Latency = 2;
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H A DAArch64SchedTSV110.td54 def : WriteRes<WriteImm, [TSV110UnitALUAB]> { let Latency = 1; }
55 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
56 def : WriteRes<WriteISReg, [TSV110UnitMDU]> { let Latency = 2; }
57 def : WriteRes<WriteIEReg, [TSV110UnitMDU]> { let Latency = 2; }
58 def : WriteRes<WriteExtr, [TSV110UnitALUAB]> { let Latency = 1; }
59 def : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; }
62 def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
64 def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
66 def : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; }
67 def : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; }
[all …]
H A DAArch64SchedA55.td63 def : WriteRes<WriteImm, [CortexA55UnitALU]> { let Latency = 3; } // MOVN, MOVZ
64 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
65 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
66 def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg
67 def : WriteRes<WriteExtr, [CortexA55UnitALU]> { let Latency = 3; } // EXTR from a reg pair
68 def : WriteRes<WriteIS, [CortexA55UnitALU]> { let Latency = 3; } // Shift/Scale
71 def : WriteRes<WriteIM32, [CortexA55UnitMAC]> { let Latency = 4; } // 32-bit Multiply
72 def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; } // 64-bit Multiply
76 let Latency = 8; let ResourceCycles = [8];
79 let Latency = 8; let ResourceCycles = [8];
[all …]
H A DAArch64SchedThunderX.td50 def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; }
51 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
52 def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
53 def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
54 def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
55 def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
59 let Latency = 4;
64 let Latency = 4;
70 let Latency = 12;
75 let Latency = 14;
[all …]
H A DAArch64SchedA53.td59 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
60 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
61 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
63 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
64 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
67 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
68 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
71 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
72 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCScheduleE5500.td52 [5, 2, 2], // Latency = 1
57 [5, 2, 2], // Latency = 1
62 [5, 2, 2, 2], // Latency = 1
68 [6, 2, 2], // Latency = 1 or 2
74 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
80 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
85 [11], // Latency = 7, Repeat rate = 1
89 [11, 2, 2], // Latency = 7, Repeat rate = 7
94 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
100 [8, 2, 2], // Latency = 4, Repeat rate = 1
[all …]
H A DPPCScheduleE500mc.td48 [4, 1, 1], // Latency = 1
53 [4, 1, 1], // Latency = 1
58 [4, 1, 1, 1], // Latency = 1
64 [5, 1, 1], // Latency = 1 or 2
70 [17, 1, 1], // Latency=4..35, Repeat= 4..35
75 [11], // Latency = 8
79 [11, 1, 1], // Latency = 8
83 [7, 1, 1], // Latency = 4, Repeat rate = 1
88 [7, 1, 1], // Latency = 4, Repeat rate = 1
93 [7, 1, 1], // Latency = 4, Repeat rate = 1
[all …]
H A DPPCScheduleE500.td43 [4, 1, 1], // Latency = 1
48 [4, 1, 1], // Latency = 1
53 [4, 1, 1, 1], // Latency = 1
59 [5, 1, 1], // Latency = 1 or 2
65 [17, 1, 1], // Latency=4..35, Repeat= 4..35
70 [7, 1, 1], // Latency = 4, Repeat rate = 1
75 [7, 1, 1], // Latency = 4, Repeat rate = 1
80 [7, 1, 1], // Latency = 4, Repeat rate = 1
85 [4, 1, 1], // Latency = 1
90 [4, 1, 1], // Latency = 1
[all …]
H A DPPCScheduleP9.td140 let Latency = 1;
147 let Latency = 1;
154 let Latency = 1;
160 let Latency = 1;
165 let Latency = 1;
171 let Latency = 1;
176 let Latency = 1;
181 let Latency = 1;
186 let Latency = 1;
196 let Latency = 2;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86SchedSkylakeClient.td96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
164 let Latency = 2;
415 let Latency = 2;
420 let Latency = 6;
426 let Latency = 3;
430 let Latency = 2;
480 let Latency = 10;
485 let Latency = 16;
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H A DX86SchedHaswell.td102 let Latency = Lat;
110 let Latency = !add(Lat, LoadLat);
144 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
171 let Latency = 2;
467 let Latency = 2;
472 let Latency = 6;
478 let Latency = 2;
482 let Latency = 2;
490 let Latency = 11;
495 let Latency = 17;
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H A DX86SchedBroadwell.td97 let Latency = Lat;
105 let Latency = !add(Lat, LoadLat);
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
167 let Latency = 2;
425 let Latency = 2;
430 let Latency = 6;
435 let Latency = 2;
439 let Latency = 2;
489 let Latency = 11;
494 let Latency = 16;
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H A DX86SchedSkylakeServer.td96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
165 let Latency = 2;
416 let Latency = 2;
421 let Latency = 6;
427 let Latency = 3;
431 let Latency = 2;
481 let Latency = 10;
486 let Latency = 16;
[all …]
H A DX86SchedSandyBridge.td92 let Latency = Lat;
100 let Latency = !add(Lat, LoadLat);
112 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; }
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
166 let Latency = 2;
436 let Latency = 2;
440 let Latency = 7;
445 let Latency = 3;
449 let Latency = 5;
471 let Latency = 11;
[all …]
H A DX86ScheduleAtom.td62 let Latency = RRLat;
68 let Latency = RMLat;
117 let Latency = 2;
121 let Latency = 2;
190 def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; }
191 def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; }
456 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
457 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
459 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
489 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
[all …]
H A DX86ScheduleZnver2.td90 // 4 Cycles load-to use Latency is captured
93 // 7 Cycles vector load-to use Latency is captured
137 let Latency = Lat;
145 let Latency = !add(Lat, LoadLat);
158 let Latency = Lat;
166 let Latency = !add(Lat, LoadLat);
179 def : WriteRes<WriteLoad, [Zn2AGU]> { let Latency = 8; }
243 let Latency = 4;
439 let Latency = 2;
443 let Latency = 5;
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/sh/
H A Dsh4a.md57 ;; Latency when taken: 2
65 ;; Latency: 3
73 ;; Latency: 3
81 ;; Latency: 0
89 ;; Latency: 1
97 ;; Latency: 0
107 ;; Latency: 3
120 ;; Latency: 0
130 ;; Latency: 3
138 ;; Latency: 2
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/sh/
H A Dsh4a.md57 ;; Latency when taken: 2
65 ;; Latency: 3
73 ;; Latency: 3
81 ;; Latency: 0
89 ;; Latency: 1
97 ;; Latency: 0
107 ;; Latency: 3
120 ;; Latency: 0
130 ;; Latency: 3
138 ;; Latency: 2
[all …]

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