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Searched refs:LWR (Results 1 – 12 of 12) sorted by relevance

/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/mips/
H A Dr6-removed.csv24 LWR,0x98000000
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp230 case Mips::LWR: in isBasePlusOffsetMemoryAccess()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp225 case MipsISD::LWR: return "MipsISD::LWR"; in getTargetNodeName()
2698 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD() local
2710 return LWR; in lowerLOAD()
2723 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); in lowerLOAD()
2725 SDValue Ops[] = { SRL, LWR.getValue(1) }; in lowerLOAD()
4762 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_W()
4831 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_D()
4842 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_D()
H A DMipsISelLowering.h246 LWR, enumerator
H A DMipsInstructionSelector.cpp487 if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), in select()
H A DMipsScheduleP5600.td140 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
H A DMipsScheduleGeneric.td569 def : InstRW<[GenericWriteLoad], (instrs LWL, LWR)>;
H A DMipsInstrInfo.td140 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
2124 def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
/netbsd-src/sys/arch/mips/mips/
H A Dbds_emul.S119 PTR_WORD _C_LABEL(mips_emul_lwr) # 046 LWR
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4520 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; in expandUxw()
/netbsd-src/share/misc/
H A Dairport4490 LWR:Leeuwarden, Netherlands
/netbsd-src/external/gpl3/gcc/dist/gcc/
H A DChangeLog-2014328 (mips_expand_block_move): Disable inline move when LWL/LWR are removed.