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Searched refs:LSBase (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp222 auto *LSBase = cast<LSBaseSDNode>(Base.getNode()); in matchLSNode() local
224 if (LSBase->isIndexed() && Base.getResNo() == IndexResNo) in matchLSNode()
225 if (auto *C = dyn_cast<ConstantSDNode>(LSBase->getOffset())) { in matchLSNode()
227 if (LSBase->getAddressingMode() == ISD::PRE_DEC || in matchLSNode()
228 LSBase->getAddressingMode() == ISD::POST_DEC) in matchLSNode()
232 Base = DAG.getTargetLoweringInfo().unwrapAddress(LSBase->getBasePtr()); in matchLSNode()
/netbsd-src/external/gpl3/gdb.old/dist/sim/arm/
H A Darmemu.h354 #define LSBase state->Reg[LHSReg] macro
/netbsd-src/external/gpl3/gdb/dist/sim/arm/
H A Darmsupp.c942 LSBase = state->Base; in ARMul_LDC()
1008 LSBase = state->Base; in ARMul_STC()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14604 LSBaseSDNode *LSBase, in combineVReverseMemOP() argument
14606 assert((ISD::isNormalLoad(LSBase) || ISD::isNormalStore(LSBase)) && in combineVReverseMemOP()
14638 if (LSBase->getOpcode() == ISD::LOAD) { in combineVReverseMemOP()
14642 for (SDNode::use_iterator UI = LSBase->use_begin(), UE = LSBase->use_end(); in combineVReverseMemOP()
14647 SDLoc dl(LSBase); in combineVReverseMemOP()
14648 SDValue LoadOps[] = {LSBase->getChain(), LSBase->getBasePtr()}; in combineVReverseMemOP()
14651 LSBase->getMemoryVT(), LSBase->getMemOperand()); in combineVReverseMemOP()
14654 if (LSBase->getOpcode() == ISD::STORE) { in combineVReverseMemOP()
14661 SDLoc dl(LSBase); in combineVReverseMemOP()
14662 SDValue StoreOps[] = {LSBase->getChain(), SVN->getOperand(0), in combineVReverseMemOP()
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H A DPPCISelLowering.h1334 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,