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Searched refs:FalseReg (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp715 Register FalseReg = in convertCmovInstsToBranches() local
719 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
722 FalseReg = FRIt->second; in convertCmovInstsToBranches()
724 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
H A DX86InstrInfo.h352 Register FalseReg) const override;
H A DX86InstrInfo.cpp3309 Register FalseReg, int &CondCycles, in canInsertSelect() argument
3323 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
3347 Register FalseReg) const { in insertSelect()
3355 .addReg(FalseReg) in insertSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
532 FalseReg.setImplicit(); in optimizeSelect()
533 NewMI.add(FalseReg); in optimizeSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1534 Register FalseReg, int &CondCycles, in canInsertSelect() argument
1547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1573 Register FalseReg) const { in insertSelect()
1580 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1632 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1633 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3108 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3115 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3117 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3119 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
H A DPPCInstrInfo.h429 Register FalseReg) const override;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp920 unsigned FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
921 if (FalseReg == 0) in selectSelect()
925 std::swap(TrueReg, FalseReg); in selectSelect()
964 .addReg(FalseReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp409 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
414 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
447 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
451 .addReg(FalseReg) in LowerFPToInt()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp536 Register FalseReg, int &CondCycles, in canInsertSelect() argument
548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
572 Register FalseReg) const { in insertSelect()
592 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
594 FalseReg = FReg; in insertSelect()
605 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZInstrInfo.h244 Register FalseReg) const override;
H A DSystemZISelLowering.cpp7133 Register FalseReg = MI->getOperand(2).getReg(); in createPHIsForSelects() local
7139 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
7144 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end()) in createPHIsForSelects()
7145 FalseReg = RegRewriteTable[FalseReg].second; in createPHIsForSelects()
7150 .addReg(FalseReg).addMBB(FalseMBB); in createPHIsForSelects()
7153 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h304 Register TrueReg, Register FalseReg, int &CondCycles,
310 Register TrueReg, Register FalseReg) const override;
315 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1049 Register FalseReg) const { in insertVectorSelect()
1062 .addReg(FalseReg) in insertVectorSelect()
1077 .addReg(FalseReg) in insertVectorSelect()
1091 .addReg(FalseReg) in insertVectorSelect()
1105 .addReg(FalseReg) in insertVectorSelect()
1121 .addReg(FalseReg) in insertVectorSelect()
1137 .addReg(FalseReg) in insertVectorSelect()
1155 .addReg(FalseReg) in insertVectorSelect()
2495 Register FalseReg, int &CondCycles, in canInsertSelect() argument
2502 if (MRI.getRegClass(FalseReg) != RC) in canInsertSelect()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp788 auto FalseReg = MIB.getReg(3); in selectSelect() local
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
795 .addUse(FalseReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2343 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
2345 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
2375 FalseReg.setImplicit(); in optimizeSelect()
2376 NewMI.add(FalseReg); in optimizeSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h863 Register TrueReg, Register FalseReg, in canInsertSelect() argument
887 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h219 Register FalseReg) const override;
H A DAArch64InstrInfo.cpp614 Register FalseReg, int &CondCycles, in canInsertSelect() argument
620 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
642 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
664 Register TrueReg, Register FalseReg) const { in insertSelect()
772 TrueReg = FalseReg; in insertSelect()
774 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
778 FalseReg = NewVReg; in insertSelect()
787 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
792 .addReg(FalseReg) in insertSelect()