| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 56 DAG_INSTRUCTION(FRem, 2, 1, experimental_constrained_frem, FREM)
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 375 FREM, enumerator
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| H A D | TargetLowering.h | 2470 case ISD::FREM: in isBinOp()
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| /netbsd-src/sys/arch/m68k/m68k/ |
| H A D | db_disasm.h | 366 #define FREM ENCFT(1,0,0,1,0,1) macro
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| H A D | db_disasm.c | 1456 case FREM: in opcode_fpu()
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| /netbsd-src/sys/arch/m68k/fpe/ |
| H A D | README | 70 FMOVECR, FLOGNP1, FLOGN, FLOG10, FLOG2, FMOD, FREM,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 697 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
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| H A D | SelectionDAGDumper.cpp | 263 case ISD::FREM: return "frem"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 111 case ISD::FREM: R = SoftenFloatRes_FREM(N); break; in SoftenFloatResult()
1247 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break; in ExpandFloatResult()
2255 case ISD::FREM: in PromoteFloatResult()
2620 case ISD::FREM: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 378 case ISD::FREM: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 136 case ISD::FREM: in ScalarizeVectorResult()
1033 case ISD::FREM: in SplitVectorResult()
3042 case ISD::FREM: in WidenVectorResult()
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| H A D | FastISel.cpp | 1706 return selectBinaryOp(I, ISD::FREM); in selectOperator()
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| H A D | SelectionDAG.cpp | 4287 case ISD::FREM: in isKnownNeverNaN()
5404 case ISD::FREM: in foldConstantFPMath()
5433 case ISD::FREM: in foldConstantFPMath()
5604 case ISD::FREM: in getNode()
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| H A D | LegalizeDAG.cpp | 4115 case ISD::FREM: in ConvertNodeToLibcall()
4676 case ISD::FREM: in PromoteNode()
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| /netbsd-src/sys/arch/m68k/fpsp/ |
| H A D | srem_mod.sa | 50 * FREM(X,Y) or FMOD(X,Y), depending on entry point.
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| H A D | do_func.sa | 358 * FREM
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 315 setOperationAction(ISD::FREM, MVT::f16, Custom); in AMDGPUTargetLowering()
316 setOperationAction(ISD::FREM, MVT::f32, Custom); in AMDGPUTargetLowering()
317 setOperationAction(ISD::FREM, MVT::f64, Custom); in AMDGPUTargetLowering()
471 setOperationAction(ISD::FREM, VT, Expand); in AMDGPUTargetLowering()
634 case ISD::FREM: in hasSourceMods()
1244 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
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| H A D | AMDGPUTargetTransformInfo.cpp | 657 case ISD::FREM: in getArithmeticInstrCost()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1628 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1633 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1638 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 348 setOperationAction(ISD::FREM, VT, Expand); in AArch64TargetLowering()
404 setOperationAction(ISD::FREM, MVT::f32, Expand); in AArch64TargetLowering()
405 setOperationAction(ISD::FREM, MVT::f64, Expand); in AArch64TargetLowering()
406 setOperationAction(ISD::FREM, MVT::f80, Expand); in AArch64TargetLowering()
426 setOperationAction(ISD::FREM, MVT::f128, Expand); in AArch64TargetLowering()
573 setOperationAction(ISD::FREM, MVT::f16, Promote); in AArch64TargetLowering()
574 setOperationAction(ISD::FREM, MVT::v4f16, Expand); in AArch64TargetLowering()
575 setOperationAction(ISD::FREM, MVT::v8f16, Expand); in AArch64TargetLowering()
968 setOperationAction(ISD::FREM, MVT::v1f64, Expand); in AArch64TargetLowering()
1403 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/mmix/ |
| H A D | mmix.md | 257 "FREM %0,%1,%2")
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/mmix/ |
| H A D | mmix.md | 281 "FREM %0,%1,%2")
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1766 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1593 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1638 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 109 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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