| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 73 DAG_FUNCTION(cos, 1, 1, experimental_constrained_cos, FCOS)
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 861 FCOS, enumerator
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| H A D | BasicTTIImpl.h | 1532 ISDs.push_back(ISD::FCOS); in getTypeBasedIntrinsicInstrCost()
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| /netbsd-src/sys/arch/m68k/m68k/ |
| H A D | db_disasm.h | 350 #define FCOS ENCFT(0,1,1,1,0,1) macro
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| H A D | db_disasm.c | 1411 case FCOS: in opcode_fpu()
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| /netbsd-src/sys/arch/m68k/fpe/ |
| H A D | README | 71 FCOSH, FSINH, FTANH, FCOS, FSIN, FTAN, FSINCOS,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 116 setOperationAction(ISD::FCOS, MVT::f32, Custom); in R600TargetLowering()
459 case ISD::FCOS: in LowerOperation()
749 case ISD::FCOS: in LowerTrig()
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| H A D | SIISelLowering.cpp | 487 setOperationAction(ISD::FCOS, MVT::f32, Custom); in SITargetLowering()
548 setOperationAction(ISD::FCOS, MVT::f16, Custom); in SITargetLowering()
4489 case ISD::FCOS: in LowerOperation()
8725 case ISD::FCOS: in LowerTrig()
9366 case ISD::FCOS: in fp16SrcZerosHighBits()
9563 case ISD::FCOS: in isCanonicalized()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 200 case ISD::FCOS: return "fcos"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 79 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break; in SoftenFloatResult()
1198 case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break; in ExpandFloatResult()
2229 case ISD::FCOS: in PromoteFloatResult()
2593 case ISD::FCOS: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2210 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3155 case ISD::FCOS: { in ExpandNode()
3164 if (Node->getOpcode() == ISD::FCOS) in ExpandNode()
3967 case ISD::FCOS: in ConvertNodeToLibcall()
4737 case ISD::FCOS: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 417 case ISD::FCOS: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 83 case ISD::FCOS: in ScalarizeVectorResult()
976 case ISD::FCOS: in SplitVectorResult()
3108 case ISD::FCOS: in WidenVectorResult()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 892 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 748 def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1626 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1631 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1636 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 351 setOperationAction(ISD::FCOS, VT, Expand); in AArch64TargetLowering()
420 setOperationAction(ISD::FCOS, MVT::f128, Expand); in AArch64TargetLowering()
562 setOperationAction(ISD::FCOS, MVT::f32, Expand); in AArch64TargetLowering()
563 setOperationAction(ISD::FCOS, MVT::f64, Expand); in AArch64TargetLowering()
582 setOperationAction(ISD::FCOS, MVT::f16, Promote); in AArch64TargetLowering()
583 setOperationAction(ISD::FCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
584 setOperationAction(ISD::FCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
960 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
1365 setOperationAction(ISD::FCOS, VT, Expand); in addTypeForNEON()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1593 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1639 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 109 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 367 setOperationAction(ISD::FCOS, VT, Expand); in addMVEVectorTypes()
842 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); in ARMTargetLowering()
863 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); in ARMTargetLowering()
879 setOperationAction(ISD::FCOS, MVT::v2f32, Expand); in ARMTargetLowering()
1022 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1386 setOperationAction(ISD::FCOS, MVT::f32, Expand); in ARMTargetLowering()
1387 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1469 setOperationAction(ISD::FCOS, MVT::f16, Promote); in ARMTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 435 setOperationAction(ISD::FCOS, MVT::f32, Expand); in MipsTargetLowering()
436 setOperationAction(ISD::FCOS, MVT::f64, Expand); in MipsTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 242 setOperationAction(ISD::FCOS, VT, Expand); in initSPUActions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 479 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 366 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
371 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
801 setOperationAction(ISD::FCOS, VT, Expand); in PPCTargetLowering()
1129 setOperationAction(ISD::FCOS, MVT::f128, Expand); in PPCTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 556 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, in NVPTXTargetLowering()
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