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Searched refs:DefI (Results 1 – 17 of 17) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp234 MachineInstr *DefI = MRI->getVRegDef(Reg.R); in processPredicateGPR() local
235 DefI->eraseFromParent(); in processPredicateGPR()
256 MachineInstr *DefI = MRI->getVRegDef(Reg.R); in getPredRegFor() local
257 assert(DefI); in getPredRegFor()
258 unsigned Opc = DefI->getOpcode(); in getPredRegFor()
260 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
261 RegisterSubReg PR = DefI->getOperand(1); in getPredRegFor()
267 MachineBasicBlock &B = *DefI->getParent(); in getPredRegFor()
268 DebugLoc DL = DefI->getDebugLoc(); in getPredRegFor()
274 if (isConvertibleToPredForm(DefI)) { in getPredRegFor()
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H A DHexagonExpandCondsets.cpp343 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start); in updateKillFlags() local
344 if (HII->isPredicated(*DefI)) in updateKillFlags()
420 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); in updateDeadsInRange() local
421 Defs.insert(DefI->getParent()); in updateDeadsInRange()
422 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
474 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); in updateDeadsInRange() local
475 for (auto &Op : DefI->operands()) { in updateDeadsInRange()
491 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); in updateDeadsInRange() local
492 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
498 for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) { in updateDeadsInRange()
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H A DHexagonVExtract.cpp149 MachineInstr *DefI = MRI.getVRegDef(VecR); in runOnMachineFunction() local
150 MachineBasicBlock::iterator At = std::next(DefI->getIterator()); in runOnMachineFunction()
151 MachineBasicBlock &DefB = *DefI->getParent(); in runOnMachineFunction()
155 Register AddrR = EmitAddr(DefB, At, DefI->getDebugLoc(), FI, 0); in runOnMachineFunction()
156 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc)) in runOnMachineFunction()
H A DHexagonSplitDouble.cpp235 MachineInstr *DefI = MRI->getVRegDef(R); in partitionRegisters() local
239 if (!DefI || isFixedInstr(DefI)) in partitionRegisters()
404 const MachineInstr *DefI = MRI->getVRegDef(Reg); in profit() local
405 switch (DefI->getOpcode()) { in profit()
413 return profit(DefI); in profit()
426 MachineInstr *DefI = MRI->getVRegDef(DR); in isProfitable() local
427 int32_t P = profit(DefI); in isProfitable()
1136 MachineInstr *DefI = MRI->getVRegDef(DR); in splitPartition() local
1137 SplitIns.insert(DefI); in splitPartition()
H A DHexagonGenInsert.cpp1025 const MachineInstr *DefI = MRI->getVRegDef(R); in findRemovableRegisters() local
1026 assert(DefI); in findRemovableRegisters()
1030 if (DefI->isPHI()) in findRemovableRegisters()
1032 getInstrUses(DefI, Regs[OtherS]); in findRemovableRegisters()
1161 const MachineInstr *DefI = MRI->getVRegDef(IR); in pruneUsesTooFar() local
1164 unsigned DIV = distance(DefI, DefV, RPO, M); in pruneUsesTooFar()
1347 const MachineInstr *DefI = MRI->getVRegDef(I->first); in selectCandidates() local
1348 getInstrUses(DefI, Us); in selectCandidates()
1445 MachineInstr *DefI = MRI->getVRegDef(I->first); in generateInserts() local
1447 DefI->eraseFromParent(); in generateInserts()
H A DHexagonEarlyIfConv.cpp408 const MachineInstr *DefI = MRI->getVRegDef(R); in usesUndefVReg() local
410 assert(DefI && "Expecting a reaching def in MRI"); in usesUndefVReg()
411 if (DefI->isImplicitDef()) in usesUndefVReg()
H A DHexagonConstExtenders.cpp1504 const MachineInstr *DefI = Rs.isVReg() ? MRI->getVRegDef(Rs.Reg) : nullptr; in calculatePlacement() local
1508 assert(!DefI || MDT->dominates(DefI->getParent(), DomB)); in calculatePlacement()
H A DHexagonBitSimplify.cpp2298 MachineInstr *DefI = MRI.getVRegDef(Op0.getReg()); in genBitSplit() local
2299 assert(DefI != nullptr); in genBitSplit()
2300 if (!MDT.dominates(DefI, &*At)) in genBitSplit()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp317 const MachineInstr *DefI = Def->getParent(); in isSafeToMove() local
319 assert(DefI->getParent() == Insert->getParent()); in isSafeToMove()
333 if (Def != DefI->defs().begin()) in isSafeToMove()
340 for (const auto &SubsequentDef : drop_begin(DefI->defs())) { in isSafeToMove()
350 const MachineBasicBlock *MBB = DefI->getParent(); in isSafeToMove()
351 auto NextI = std::next(MachineBasicBlock::const_iterator(DefI)); in isSafeToMove()
359 if (WebAssembly::isCatch(DefI->getOpcode())) in isSafeToMove()
364 for (const MachineOperand &MO : DefI->operands()) { in isSafeToMove()
394 query(*DefI, AA, Read, Write, Effects, StackPointer); in isSafeToMove()
403 MachineBasicBlock::const_iterator D(DefI), I(Insert); in isSafeToMove()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMIRCanonicalizerPass.cpp239 MachineBasicBlock::iterator DefI = BBE; in rescheduleCanonically() local
244 if (DefI != BBE && UseI != BBE) in rescheduleCanonically()
248 DefI = BBI; in rescheduleCanonically()
258 if (DefI == BBE || UseI == BBE) in rescheduleCanonically()
263 DefI->dump(); in rescheduleCanonically()
270 MBB->splice(UseI, MBB, DefI); in rescheduleCanonically()
H A DMachineTraceMetrics.cpp639 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg); in DataDep() local
640 assert(!DefI.atEnd() && "Register has no defs"); in DataDep()
641 DefMI = DefI->getParent(); in DataDep()
642 DefOp = DefI.getOperandNo(); in DataDep()
643 assert((++DefI).atEnd() && "Register has multiple defs"); in DataDep()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.cpp819 MachineInstr *DefI = Def->getInstr(); in adjustSchedDependency() local
822 if (DefI->isBundle()) { in adjustSchedDependency()
825 MachineBasicBlock::const_instr_iterator I(DefI->getIterator()); in adjustSchedDependency()
826 MachineBasicBlock::const_instr_iterator E(DefI->getParent()->instr_end()); in adjustSchedDependency()
840 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI); in adjustSchedDependency()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
H A DLoopInfo.h1188 auto *DefI = dyn_cast<Instruction>(U.get()); in movementPreservesLCSSAForm() local
1189 if (!DefI) in movementPreservesLCSSAForm()
1195 auto *DefBlock = DefI->getParent(); in movementPreservesLCSSAForm()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp1157 auto *DefI = dyn_cast<Instruction>(Def); in getInsertPointForUses() local
1158 if (!DefI) in getInsertPointForUses()
1161 assert(DT->dominates(DefI, InsertPt) && "def does not dominate all uses"); in getInsertPointForUses()
1163 auto *L = LI->getLoopFor(DefI->getParent()); in getInsertPointForUses()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DDeadStoreElimination.cpp1737 Instruction *DefI = Def->getMemoryInst(); in eliminateDeadWritesAtEndOfFunction() local
1739 auto DefLoc = getLocForWriteEx(DefI); in eliminateDeadWritesAtEndOfFunction()
1756 deleteDeadInstruction(DefI); in eliminateDeadWritesAtEndOfFunction()
/netbsd-src/external/apache2/llvm/dist/clang/utils/TableGen/
H A DNeonEmitter.cpp1403 DefInit *DefI = cast<DefInit>(DI->getOperator()); in emitDag() local
1404 std::string Op = DefI->getAsString(); in emitDag()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/TableGen/
H A DRecord.cpp2158 if (DefInit *DefI = dyn_cast<DefInit>(Val)) in getOperatorAsDef() local
2159 return DefI->getDef(); in getOperatorAsDef()