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Searched refs:CTX (Results 1 – 25 of 114) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineModuleInfo.cpp21 LLVMContext &CTX = MMI.getModule()->getContext(); in AMDGPUMachineModuleInfo() local
22 AgentSSID = CTX.getOrInsertSyncScopeID("agent"); in AMDGPUMachineModuleInfo()
23 WorkgroupSSID = CTX.getOrInsertSyncScopeID("workgroup"); in AMDGPUMachineModuleInfo()
24 WavefrontSSID = CTX.getOrInsertSyncScopeID("wavefront"); in AMDGPUMachineModuleInfo()
26 CTX.getOrInsertSyncScopeID("one-as"); in AMDGPUMachineModuleInfo()
28 CTX.getOrInsertSyncScopeID("agent-one-as"); in AMDGPUMachineModuleInfo()
30 CTX.getOrInsertSyncScopeID("workgroup-one-as"); in AMDGPUMachineModuleInfo()
32 CTX.getOrInsertSyncScopeID("wavefront-one-as"); in AMDGPUMachineModuleInfo()
34 CTX.getOrInsertSyncScopeID("singlethread-one-as"); in AMDGPUMachineModuleInfo()
/netbsd-src/crypto/external/bsd/openssl/dist/test/
H A Dcmp_ctx_test.c513 #define DEFINE_SET_GET_TEST(OSSL_CMP, CTX, N, M, DUP, FIELD, TYPE) \ argument
514 DEFINE_SET_GET_BASE_TEST(OSSL_CMP##_##CTX, set##N, get##M, DUP, FIELD, \
517 #define DEFINE_SET_GET_SK_TEST_DEFAULT(OSSL_CMP, CTX, N, M, FIELD, ELEM_TYPE, \ argument
519 DEFINE_SET_GET_BASE_TEST(OSSL_CMP##_##CTX, set##N, get##M, 1, FIELD, \
521 #define DEFINE_SET_GET_SK_TEST(OSSL_CMP, CTX, N, M, FIELD, T) \ argument
522 DEFINE_SET_GET_SK_TEST_DEFAULT(OSSL_CMP, CTX, N, M, FIELD, T, \
524 #define DEFINE_SET_GET_SK_X509_TEST(OSSL_CMP, CTX, N, M, FNAME) \ argument
525 DEFINE_SET_GET_SK_TEST_DEFAULT(OSSL_CMP, CTX, N, M, FNAME, X509, \
529 #define DEFINE_SET_GET_TEST_DEFAULT(OSSL_CMP, CTX, N, M, DUP, FIELD, TYPE, \ argument
531 DEFINE_SET_GET_BASE_TEST(OSSL_CMP##_##CTX, set##N, get##M, DUP, FIELD, \
[all …]
/netbsd-src/crypto/external/bsd/openssl/dist/providers/implementations/include/prov/
H A Ddigestcommon.h51 name, CTX, blksize, dgstsize, flags, upd, fin) \ argument
57 CTX *ctx = ossl_prov_is_running() ? OPENSSL_zalloc(sizeof(*ctx)) : NULL; \
62 CTX *ctx = (CTX *)vctx; \
67 CTX *in = (CTX *)ctx; \
68 CTX *ret = ossl_prov_is_running() ? OPENSSL_malloc(sizeof(*ret)) : NULL; \
88 name, CTX, blksize, dgstsize, flags, init, upd, fin) \ argument
95 PROV_DISPATCH_FUNC_DIGEST_CONSTRUCT_START(name, CTX, blksize, dgstsize, flags, \
101 name, CTX, blksize, dgstsize, flags, init, upd, fin, \ argument
110 PROV_DISPATCH_FUNC_DIGEST_CONSTRUCT_START(name, CTX, blksize, dgstsize, flags, \
/netbsd-src/crypto/external/bsd/openssl/dist/crypto/sha/asm/
H A Dsha1-c64xplus.pl37 ($CTX,$INP,$NUM) = ("A4","B4","A6"); # arguments
72 [A0] LDW *${CTX}[0],$A ; load A-E...
74 [A0] LDW *${CTX}[1],$B
76 [A0] LDW *${CTX}[2],$C
78 [A0] LDW *${CTX}[3],$D
80 [A0] LDW *${CTX}[4],$E
321 STW $A,*${CTX}[0] ; emit A-E...
323 STW $B,*${CTX}[1]
325 STW $C,*${CTX}[2]
326 STW $D,*${CTX}[3]
[all …]
/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/sha/asm/
H A Dsha1-c64xplus.pl38 ($CTX,$INP,$NUM) = ("A4","B4","A6"); # arguments
73 [A0] LDW *${CTX}[0],$A ; load A-E...
75 [A0] LDW *${CTX}[1],$B
77 [A0] LDW *${CTX}[2],$C
79 [A0] LDW *${CTX}[3],$D
81 [A0] LDW *${CTX}[4],$E
322 STW $A,*${CTX}[0] ; emit A-E...
324 STW $B,*${CTX}[1]
326 STW $C,*${CTX}[2]
327 STW $D,*${CTX}[3]
[all …]
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/rs6000/
H A Daix-unwind.h41 #define MD_FROB_UPDATE_CONTEXT(CTX, FS) \ argument
47 _Unwind_GetGR ((CTX), R_LR); \
49 _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 40); \
53 #define MD_FROB_UPDATE_CONTEXT(CTX, FS) \ argument
59 _Unwind_GetGR ((CTX), R_LR); \
61 _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 20); \
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/rs6000/
H A Daix-unwind.h41 #define MD_FROB_UPDATE_CONTEXT(CTX, FS) \ argument
47 _Unwind_GetGR ((CTX), R_LR); \
49 _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 40); \
53 #define MD_FROB_UPDATE_CONTEXT(CTX, FS) \ argument
59 _Unwind_GetGR ((CTX), R_LR); \
61 _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 20); \
/netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
H A DDWARFDebugAranges.cpp45 void DWARFDebugAranges::generate(DWARFContext *CTX) { in generate() argument
47 if (!CTX) in generate()
51 DWARFDataExtractor ArangesData(CTX->getDWARFObj().getArangesSection(), in generate()
52 CTX->isLittleEndian(), 0); in generate()
53 extract(ArangesData, CTX->getRecoverableErrorHandler()); in generate()
58 for (const auto &CU : CTX->compile_units()) { in generate()
63 CTX->getRecoverableErrorHandler()(CURanges.takeError()); in generate()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
H A Ddmub_reg.h53 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
56 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
61 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
88 dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)
115 dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
H A Damdgpu_dmub_dcn21.c40 #define CTX dmub macro
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp52 MCContext &CTX; member in __anonfa29a22a0111::ARMMCCodeEmitter
57 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { in ARMMCCodeEmitter()
557 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); in getMachineOpValue()
597 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in EncodeAddrModeOpValues()
932 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue()
933 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
991 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrModeImm12OpValue()
997 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrModeImm12OpValue()
1068 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeRQOpValue()
1069 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg()); in getMveAddrModeRQOpValue()
[all …]
/netbsd-src/sys/external/bsd/compiler_rt/dist/lib/asan/scripts/
H A Dasan_device_setup412 CTX=u:object_r:system_file:s0
414 CTX=u:object_r:zygote_exec:s0
422 install "$TMPDIR/app_process32" /system/bin 755 $CTX
423 install "$TMPDIR/app_process32.real" /system/bin 755 $CTX
424 install "$TMPDIR/app_process64" /system/bin 755 $CTX
425 install "$TMPDIR/app_process64.real" /system/bin 755 $CTX
435 install "$TMPDIR/app_process32" /system/bin 755 $CTX
436 install "$TMPDIR/app_process.wrap" /system/bin 755 $CTX
437 install "$TMPDIR/asanwrapper" /system/bin 755 $CTX
447 adb_shell chcon $CTX /system/bin/sh-from-zygote
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
H A Dreg_helper.h42 dm_read_reg(CTX, REG(reg_name))
45 dm_write_reg(CTX, REG(reg_name), value)
57 generic_reg_set_ex(CTX, \
159 generic_reg_get(CTX, REG(reg_name), \
163 generic_reg_get2(CTX, REG(reg_name), \
168 generic_reg_get3(CTX, REG(reg_name), \
174 generic_reg_get4(CTX, REG(reg_name), \
181 generic_reg_get5(CTX, REG(reg_name), \
189 generic_reg_get6(CTX, REG(reg_name), \
198 generic_reg_get7(CTX, REG(reg_name), \
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/libcpp/
H A Ducnid.h119 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0300 },
120 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0301 },
121 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0302 },
122 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0303 },
123 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0304 },
125 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0306 },
126 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0307 },
127 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0308 },
128 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x0309 },
129 { 0| 0| 0|C11|N11|CID|NFC|NKC|CTX, 230, 0x030a },
[all …]
/netbsd-src/external/gpl3/gcc/dist/libcc1/
H A Dgdbctx.hh338 template<typename CTX, typename R, const char *&NAME, typename... Arg>
339 R rpc (CTX *s, Arg... rest) in rpc()
341 base_gdb_plugin<CTX> *self = (base_gdb_plugin<CTX> *) s; in rpc()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiMCInstLower.h31 LanaiMCInstLower(MCContext &CTX, AsmPrinter &AP) : Ctx(CTX), Printer(AP) {} in LanaiMCInstLower() argument
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddm_services.h361 #define PERF_TRACE() trace_amdgpu_dc_performance(CTX->perf_trace->read_count,\
362 CTX->perf_trace->write_count, &CTX->perf_trace->last_entry_read,\
363 &CTX->perf_trace->last_entry_write, __func__, __LINE__)
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_link_encoder.c42 #define CTX \ macro
272 dm_read_reg(CTX, AUX_REG(reg_name))
275 dm_write_reg(CTX, AUX_REG(reg_name), val)
H A Damdgpu_dcn20_vmid.c39 #define CTX \ macro
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.h27 const MCContext &CTX; variable
32 : MCII(mcii), CTX(ctx), in PPCMCCodeEmitter()
/netbsd-src/external/gpl3/gcc/dist/libcpp/
H A Ducnid.h124 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 230, 0x0304 },
126 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 230, 0x030c },
128 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 230, 0x030f },
130 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 230, 0x0311 },
132 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 230, 0x0314 },
136 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 216, 0x031b },
139 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 220, 0x0326 },
140 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 202, 0x0328 },
142 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 220, 0x032e },
144 { 0| 0| 0|C11|N11|CXX23|NXX23|CID|NFC|NKC|CTX, 220, 0x0331 },
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_link_encoder.c45 #define CTX \ macro
1346 dm_read_reg(CTX, HPD_REG(reg_name))
1349 generic_reg_update_ex(CTX, \
1378 dm_read_reg(CTX, AUX_REG(reg_name))
1381 generic_reg_update_ex(CTX, \
H A Damdgpu_dcn10_ipp.c44 #define CTX \ macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
H A Damdgpu_bios_parser_helper.c53 #define CTX \ macro
/netbsd-src/sys/dev/videomode/
H A Dediddevs50 vendor CTX CTX

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