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Searched refs:CSR_READ (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/sys/dev/ic/
H A Dpca9564.c59 #define CSR_READ(sc, r) (*sc->sc_ios.read_byte)(sc->sc_dev, r) macro
126 control = CSR_READ(sc, PCA9564_I2CCON); in pca9564_acquire_bus()
144 control = CSR_READ(sc, PCA9564_I2CCON); in pca9564_release_bus()
156 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); in pca9564_wait()
158 if (CSR_READ(sc, PCA9564_I2CCON) & I2CCON_SI) in pca9564_wait()
162 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); in pca9564_wait()
176 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); in pca9564_send_start()
177 control = CSR_READ(sc, PCA9564_I2CCON); in pca9564_send_start()
181 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); in pca9564_send_start()
192 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); in pca9564_send_stop()
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H A Ddp83932.c582 isr = CSR_READ(sc, SONIC_ISR) & sc->sc_imr; in sonic_intr()
1080 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP | CR_RXEN | CR_ST)) == 0) in sonic_stop()
1084 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP | CR_RXEN | CR_ST)) != 0) in sonic_stop()
1265 if ((CSR_READ(sc, SONIC_CR) & CR_LCAM) == 0) in sonic_set_filter()
1269 if (CSR_READ(sc, SONIC_CR) & CR_LCAM) in sonic_set_filter()
H A Ddp83932var.h207 #define CSR_READ(sc, reg) \ macro
/netbsd-src/sys/arch/cobalt/stand/boot/
H A Dns16550.c39 #define CSR_READ(base, reg) (*(volatile uint8_t *)((base) + (reg))) macro
71 while ((CSR_READ(com_port, com_lsr) & LSR_TXRDY) == 0) in com_putc()
82 while ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0) in com_getc()
85 return CSR_READ(com_port, com_data); in com_getc()
93 if ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0) in com_scankbd()
96 return CSR_READ(com_port, com_data); in com_scankbd()
H A Dtlp.c56 #define CSR_READ(l, r) (*(volatile uint32_t *)((l)->csr + (r))) macro
197 val = CSR_READ(l, TLP_BMR); in tlp_init()
202 (void)CSR_READ(l, TLP_BMR); in tlp_init()
423 ret = (ret << 1) | !!(CSR_READ(l, TLP_APROM) & VV); in read_srom()
H A Dlcd.c40 #define CSR_READ(base, reg) \
/netbsd-src/sys/arch/mmeye/stand/boot/
H A Dcom.c102 #define CSR_READ(base, reg) (*(volatile uint8_t *)((base) + (reg))) macro
162 while ((CSR_READ(com_port, com_lsr) & LSR_TXRDY) == 0) in com_putc()
173 while ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0) in com_getc()
176 return CSR_READ(com_port, com_data); in com_getc()
184 if ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0) in com_scankbd()
187 return CSR_READ(com_port, com_data); in com_scankbd()
/netbsd-src/sys/dev/pci/
H A Dif_wm.c791 #define CSR_READ(sc, reg) \ macro
796 (void)CSR_READ((sc), WMREG_STATUS)
1874 if (CSR_READ(sc, reg) & SCTL_CTL_READY) in wm_82575_write_8bit_ctlr_reg()
2303 sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS) in wm_attach()
2349 reg = CSR_READ(sc, WMREG_STATUS); in wm_attach()
2423 CSR_READ(sc, WMREG_COLC); in wm_attach()
2424 CSR_READ(sc, WMREG_RXERRC); in wm_attach()
2450 reg = CSR_READ(sc, WMREG_EECD); in wm_attach()
2466 reg = CSR_READ(sc, WMREG_EECD); in wm_attach()
2592 (((CSR_READ(s in wm_attach()
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H A Dif_dge.c365 #define CSR_READ(sc, reg) \ macro
756 reg = CSR_READ(sc, DGE_STATUS);
1525 icr = CSR_READ(sc, DGE_ICR);
1822 status = CSR_READ(sc, DGE_STATUS);
1856 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0)
1861 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST)
1990 reg = CSR_READ(sc, DGE_RXCSUM);
2278 hash = CSR_READ(sc, DGE_MTA + (reg << 2));
2326 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK | EECD_DI | EECD_CS);
2362 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_SK);
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/netbsd-src/sys/arch/sandpoint/stand/altboot/
H A Dsme.c47 #define CSR_READ(l, r) in32rb((l)->csr+(r)) macro
132 mac32 = CSR_READ(l, ADDRL); in sme_init()
133 mac16 = CSR_READ(l, ADDRH); in sme_init()
281 ctl = CSR_READ(l, MIIADDR); in mii_read()
286 ctl = CSR_READ(l, MIIADDR); in mii_read()
288 return CSR_READ(l, MIIDATA); in mii_read()
297 ctl = CSR_READ(l, MIIADDR); in mii_write()
H A Dtlp.c47 #define CSR_READ(l, r) in32rb((l)->csr+(r)) macro
144 } while (i-- > 0 && (CSR_READ(l, PAR_CSR0) & PAR_SWR) != 0); in tlp_init()
153 val = CSR_READ(l, PAR0_CSR25); in tlp_init()
158 val = CSR_READ(l, PAR1_CSR26); in tlp_init()
169 val = CSR_READ(l, AN_OMODE); in tlp_init()
315 rv = (rv << 1) | !!(CSR_READ(l, SPR_CSR9) & MII_MDI); in mii_read()
H A Dwm.c49 #define CSR_READ(l, r) in32rb((l)->csr+(r)) macro
312 v = CSR_READ(l, WMREG_EECD) & ~(EECD_SK | EECD_DI); in read_srom()
338 data = (data << 1) | !!(CSR_READ(l, WMREG_EECD) & EECD_DO); in read_srom()
343 v = CSR_READ(l, WMREG_EECD) & ~EECD_CS; in read_srom()
361 data = CSR_READ(l, WMREG_MDIC); in mii_read()
374 data = CSR_READ(l, WMREG_MDIC); in mii_write()
H A Dsip.c47 #define CSR_READ(l, r) in32rb((l)->csr+(r)) macro
154 val = CSR_READ(l, SIP_CR); in sip_init()
187 val = CSR_READ(l, SIP_CFG); in sip_init()
328 data = (data << 1) | !!(CSR_READ(l, SIP_MEAR) & MEAR_EEDO); in read_eeprom()
361 val = CSR_READ(l, SIP_BMCR + (reg << 2)); in mii_read()
/netbsd-src/sys/arch/mac68k/obio/
H A Dif_sn_obio.c209 i = CSR_READ(sc, SONIC_CAP2); in sn_obio_getaddr_kludge()
215 i = CSR_READ(sc, SONIC_CAP1); in sn_obio_getaddr_kludge()
221 i = CSR_READ(sc, SONIC_CAP0); in sn_obio_getaddr_kludge()
/netbsd-src/sys/arch/sandpoint/sandpoint/
H A Dsatmgr.c188 #define CSR_READ(t,r) bus_space_read_1((t)->sc_iot, (t)->sc_ioh, (r)) macro
458 lsr = CSR_READ(sc, LSR); in send_sat_len()
646 iir = CSR_READ(sc, IIR) & IIR_IMASK; in hwintr()
664 iir = CSR_READ(sc, IIR) & IIR_IMASK; in hwintr()
675 lsr = CSR_READ(sc, LSR); in rxintr()
681 (void) CSR_READ(sc, RBR); in rxintr()
683 lsr = CSR_READ(sc, LSR); in rxintr()
686 ch = CSR_READ(sc, RBR); in rxintr()
693 lsr = CSR_READ(sc, LSR); in rxintr()
/netbsd-src/sys/arch/arm/sociox/
H A Dif_scx.c544 #define CSR_READ(sc,off) \ macro
605 val = CSR_READ(sc, reg); in wait_for_bits()
622 return CSR_READ(sc, MACDATA); in mac_read()
882 which = CSR_READ(sc, HWVER); /* Socionext version 5.xx */ in scx_attach_i()
1533 status = CSR_READ(sc, xINTSR); /* not W1C */ in scx_intr()
1534 enable = CSR_READ(sc, xINTAEN); in scx_intr()
1540 status = CSR_READ(sc, RXISR); in scx_intr()
1546 (void)CSR_READ(sc, RXAVAILCNT); /* clear IRQ_RX ? */ in scx_intr()
1549 status = CSR_READ(sc, TXISR); in scx_intr()
1555 (void)CSR_READ(sc, TXDONECNT); /* clear IRQ_TX ? */ in scx_intr()
[all …]
H A Dsni_i2c.c137 #define CSR_READ(sc, reg) \ macro
/netbsd-src/sys/arch/evbarm/stand/boot2440/
H A Dmain.c44 #define CSR_READ(reg) \ macro
123 socmodel = CSR_READ(S3C2440_GPIO_BASE + GPIO_GSTATUS1); in main()
472 stat = CSR_READ(S3C2440_UART_BASE(0) + SSCOM_UTRSTAT); in putchar()