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Searched refs:CCR (Results 1 – 25 of 92) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrControl.td90 let Uses = [CCR] in {
93 [(set i8:$dst, (MxSetCC !cast<PatLeaf>("MxCOND"#CC), CCR))],
100 [(store (MxSetCC !cast<PatLeaf>("MxCOND"#CC), CCR), MEMPat:$dst)],
149 let isBranch = 1, isTerminator = 1, Uses = [CCR] in
168 def : Pat<(MxBrCond bb:$target, !cast<PatLeaf>("MxCOND"#cc), CCR),
276 let Uses = [CCR], Defs = [CCR], isPseudo = 1 in {
281 [(set MxDRD8:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
283 [(set MxDRD16:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
285 [(set MxXRD32:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
286 } // Uses = [CCR], Defs = [CCR], isPseudo = 1
[all …]
H A DM68kInstrBits.td51 let Defs = [CCR] in {
54 [(set CCR, (MxBt TYPE.VT:$dst, TYPE.VT:$bitno))],
59 [(set CCR, (MxBt TYPE.VT:$dst, TYPE.IPat:$bitno))],
65 [(set CCR, (MxBt (TYPE.Load MEMPat:$dst), TYPE.VT:$bitno))],
71 [(set CCR, (MxBt (TYPE.Load MEMPat:$dst), TYPE.IPat:$bitno))],
73 } // Defs = [CCR]
H A DM68kInstrArithmetic.td87 let Defs = [CCR] in {
94 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
110 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
119 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
131 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
141 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))],
150 // FIXME MxBiArOp_FMR/FMI cannot consume CCR from MxAdd/MxSub which leads for
173 } // Defs = [CCR]
275 // operations do not produce CCR we should not match them against Mx nodes that
298 // NOTE These naturally produce CCR
[all …]
H A DM68kInstrCompiler.td57 let usesCustomInserter = 1, Uses = [CCR] in
61 (TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>;
76 // sub / add which can clobber CCR.
77 let Defs = [SP, CCR], Uses = [SP] in {
123 let Defs = [SP, CCR], Uses = [SP] in
H A DM68kInstrInfo.td37 /* CCR */ SDTCisVT<1, i8>,
41 // RES, CCR <- op LHS, RHS
44 /* CCR */ SDTCisVT<1, i8>,
49 // RES, CCR <- op LHS, RHS, CCR
52 /* CCR */ SDTCisVT<1, i8>,
55 /* CCR */ SDTCisSameAs<1, 4>
58 // RES1, RES2, CCR <- op LHS, RHS
62 /* CCR */ SDTCisVT<1, i8>,
68 /* CCR */ SDTCisVT<0, i8>,
76 /* CCR */ SDTCisVT<4, i8>
[all …]
H A DM68kISelLowering.cpp1961 SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG); in LowerSETCC() local
1963 DAG.getConstant(M68kCC, DL, MVT::i8), CCR); in LowerSETCC()
2913 if (mi.readsRegister(M68k::CCR)) in checkAndUpdateCCRKill()
2915 if (mi.definesRegister(M68k::CCR)) in checkAndUpdateCCRKill()
2923 if (SBB->isLiveIn(M68k::CCR)) in checkAndUpdateCCRKill()
2928 SelectItr->addRegisterKilled(M68k::CCR, TRI); in checkAndUpdateCCRKill()
3028 Jcc1MBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3041 if (!LastCCRSUser->killsRegister(M68k::CCR) && in EmitLoweredSelect()
3043 Copy0MBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3044 SinkMBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
[all …]
H A DM68kInstrShiftRotate.td71 let Defs = [CCR] in {
83 } // Defs = [CCR]
H A DM68kInstrData.td59 let Defs = [CCR] in
482 // MOVE to/from SR/CCR
484 // A special care must be taken working with to/from CCR since it is basically
486 // instructions. Plus the original M68000 does not support moves from CCR. So in
487 // order to use CCR effectively one MUST use proper byte-size pseudo instructi-
497 let Defs = [CCR] in
514 /// Move from CCR
521 let Uses = [CCR] in
589 let Defs = [CCR] in {
H A DM68kRegisterInfo.td76 def CCR : MxPseudoReg<"ccr">;
107 def CCRC : MxRegClass<[i8], 16, (add CCR)>;
/netbsd-src/external/apache2/llvm/dist/clang/lib/AST/
H A DComparisonCategories.cpp204 using CCR = ComparisonCategoryResult; in getPossibleResultsForType() typedef
205 std::vector<CCR> Values; in getPossibleResultsForType()
208 Values.push_back(IsStrong ? CCR::Equal : CCR::Equivalent); in getPossibleResultsForType()
209 Values.push_back(CCR::Less); in getPossibleResultsForType()
210 Values.push_back(CCR::Greater); in getPossibleResultsForType()
212 Values.push_back(CCR::Unordered); in getPossibleResultsForType()
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/AST/
H A DComparisonCategories.h152 using CCR = ComparisonCategoryResult; in makeWeakResult() local
153 if (!isStrong() && Res == CCR::Equal) in makeWeakResult()
154 return CCR::Equivalent; in makeWeakResult()
/netbsd-src/sys/arch/dreamcast/dreamcast/
H A Dlocore.S57 mov.l _L.CCR, r0
84 _L.CCR: .long SH4_CCR
/netbsd-src/sys/arch/evbsh3/evbsh3/
H A Dlocore.S188 MOV (CCR, r3)
230 REG_SYMBOL(CCR)
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64RegisterBanks.td19 def CCRegBank : RegisterBank<"CC", [CCR]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td60 def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
/netbsd-src/external/gpl3/binutils/dist/gas/config/
H A Dm68k-parse.h85 CCR, /* Condition code Reg */ enumerator
/netbsd-src/external/gpl3/binutils.old/dist/gas/config/
H A Dm68k-parse.h85 CCR, /* Condition code Reg */ enumerator
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dh8300.h78 CCR = 0x4000, enumerator
1252 {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
1422 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ …
1424 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, …
1426 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | …
1428 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | …
1430 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | …
1432 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | …
1434 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, I…
1436 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, I…
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dh8300.h78 CCR = 0x4000, enumerator
1252 {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
1422 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ …
1424 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, …
1426 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | …
1428 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | …
1430 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | …
1432 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | …
1434 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, I…
1436 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, I…
[all …]
/netbsd-src/crypto/external/bsd/openssl.old/lib/libcrypto/arch/sparc/
H A Dvis3-mont.S207 subcc %g0, %l0, %g0 ! move upmost overflow to CCR.xcc
220 subcc %i5, 8, %l4 ! cnt=num-1 and clear CCR.xcc
/netbsd-src/crypto/external/bsd/openssl/lib/libcrypto/arch/sparc64/
H A Dvis3-mont.S210 subcc %g0, %l0, %g0 ! move upmost overflow to CCR.xcc
223 subcc %i5, 8, %l4 ! cnt=num-1 and clear CCR.xcc
/netbsd-src/crypto/external/bsd/openssl/lib/libcrypto/arch/sparc/
H A Dvis3-mont.S210 subcc %g0, %l0, %g0 ! move upmost overflow to CCR.xcc
223 subcc %i5, 8, %l4 ! cnt=num-1 and clear CCR.xcc
/netbsd-src/crypto/external/bsd/openssl.old/lib/libcrypto/arch/sparc64/
H A Dvis3-mont.S207 subcc %g0, %l0, %g0 ! move upmost overflow to CCR.xcc
220 subcc %i5, 8, %l4 ! cnt=num-1 and clear CCR.xcc
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dh8300-dis.c298 else if ((x & MODE) == CCR) in print_one_arg()
506 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) in bfd_h8_disassemble()
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dh8300-dis.c298 else if ((x & MODE) == CCR) in print_one_arg()
506 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) in bfd_h8_disassemble()

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