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Searched refs:BasePtr (Results 1 – 25 of 55) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp51 BasePtr = M68k::A4; in M68kRegisterInfo()
182 unsigned BasePtr; in eliminateFrameIndex() local
184 BasePtr = (FIndex < 0 ? FramePtr : getBaseRegister()); in eliminateFrameIndex()
186 BasePtr = (FIndex < 0 ? FramePtr : StackPtr); in eliminateFrameIndex()
188 BasePtr = StackPtr; in eliminateFrameIndex()
190 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr); in eliminateFrameIndex()
192 Base.ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
206 if (BasePtr == StackPtr) in eliminateFrameIndex()
255 return MRI->canReserveReg(BasePtr); in canRealignStack()
H A DM68kRegisterInfo.h42 unsigned BasePtr; variable
101 unsigned getBaseRegister() const { return BasePtr; } in getBaseRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp68 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
73 BasePtr = X86::ESI; in X86RegisterInfo()
568 Register BasePtr = getX86SubSuperRegister(getBaseRegister(), 64); in getReservedRegs() local
569 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs()
679 return MRI->canReserveReg(BasePtr); in canRealignStack()
697 Register BasePtr = MI.getOperand(1).getReg(); in tryOptimizeLEAtoMOV() local
702 BasePtr = getX86SubSuperRegister(BasePtr, 32); in tryOptimizeLEAtoMOV()
706 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr, in tryOptimizeLEAtoMOV()
738 Register BasePtr; in eliminateFrameIndex() local
744 TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed(); in eliminateFrameIndex()
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H A DX86RegisterInfo.h49 unsigned BasePtr; variable
139 Register getBaseRegister() const { return BasePtr; } in getBaseRegister()
H A DX86FrameLowering.cpp1345 Register BasePtr = TRI->getBaseRegister(); in emitPrologue() local
1834 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr) in emitPrologue()
1857 assert(UsedReg == BasePtr); in emitPrologue()
2671 Register BasePtr = TRI->getBaseRegister(); in determineCalleeSaves() local
2673 BasePtr = getX86SubSuperRegister(BasePtr, 64); in determineCalleeSaves()
2674 SavedRegs.set(BasePtr); in determineCalleeSaves()
3406 Register BasePtr = TRI->getBaseRegister(); in restoreWin32EHStackPointers() local
3439 } else if (UsedReg == BasePtr) { in restoreWin32EHStackPointers()
3441 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr), in restoreWin32EHStackPointers()
3449 assert(UsedReg == BasePtr); in restoreWin32EHStackPointers()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMVEGatherScatterLowering.cpp126 Value *tryCreateIncrementingGatScat(IntrinsicInst *I, Value *BasePtr,
132 Value *tryCreateIncrementingWBGatScat(IntrinsicInst *I, Value *BasePtr,
481 Value *BasePtr = in tryCreateMaskedGatherOffset() local
483 if (!BasePtr) in tryCreateMaskedGatherOffset()
487 Value *Load = tryCreateIncrementingGatScat(I, BasePtr, Offsets, GEP, Builder); in tryCreateMaskedGatherOffset()
492 BasePtr->getType()->getPointerElementType()->getPrimitiveSizeInBits(), in tryCreateMaskedGatherOffset()
502 {ResultTy, BasePtr->getType(), Offsets->getType(), Mask->getType()}, in tryCreateMaskedGatherOffset()
503 {BasePtr, Offsets, Builder.getInt32(OriginalTy->getScalarSizeInBits()), in tryCreateMaskedGatherOffset()
508 {ResultTy, BasePtr->getType(), Offsets->getType()}, in tryCreateMaskedGatherOffset()
509 {BasePtr, Offsets, Builder.getInt32(OriginalTy->getScalarSizeInBits()), in tryCreateMaskedGatherOffset()
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H A DARMBaseRegisterInfo.h105 unsigned BasePtr = ARM::R6;
182 Register getBaseRegister() const { return BasePtr; } in getBaseRegister()
H A DARMBaseRegisterInfo.cpp202 markSuperRegs(Reserved, BasePtr); in getReservedRegs()
239 markSuperRegs(Reserved, BasePtr); in isInlineAsmReadOnlyReg()
453 return MRI->canReserveReg(BasePtr); in canRealignStack()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCLoopInstrFormPrep.cpp254 static bool IsPtrInBounds(Value *BasePtr) { in IsPtrInBounds() argument
255 Value *StrippedBasePtr = BasePtr; in IsPtrInBounds()
508 Value *BasePtr = GetPointerOperand(MemI); in rewriteLoadStores() local
509 assert(BasePtr && "No pointer operand"); in rewriteLoadStores()
513 BasePtr->getType()->getPointerAddressSpace()); in rewriteLoadStores()
572 cast<GetElementPtrInst>(PtrInc)->setIsInBounds(IsPtrInBounds(BasePtr)); in rewriteLoadStores()
579 if (PtrInc->getType() != BasePtr->getType()) in rewriteLoadStores()
581 PtrInc, BasePtr->getType(), in rewriteLoadStores()
600 cast<GetElementPtrInst>(PtrInc)->setIsInBounds(IsPtrInBounds(BasePtr)); in rewriteLoadStores()
605 if (NewPHI->getType() != BasePtr->getType()) in rewriteLoadStores()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp296 Register BasePtr; in eliminateFrameIndex() local
298 (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed() + in eliminateFrameIndex()
303 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false); in eliminateFrameIndex()
310 Ops, TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed()); in eliminateFrameIndex()
327 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
350 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
358 .addReg(BasePtr).addImm(HighOffset).addReg(0); in eliminateFrameIndex()
364 .addReg(BasePtr, RegState::Kill).addImm(0).addReg(ScratchReg); in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DShadowStackGCLowering.cpp82 Type *Ty, Value *BasePtr, int Idx1,
85 Type *Ty, Value *BasePtr, int Idx1, int Idx2,
262 Value *BasePtr, int Idx, in CreateGEP() argument
268 Value *Val = B.CreateGEP(Ty, BasePtr, Indices, Name); in CreateGEP()
276 IRBuilder<> &B, Type *Ty, Value *BasePtr, in CreateGEP() argument
280 Value *Val = B.CreateGEP(Ty, BasePtr, Indices, Name); in CreateGEP()
H A DInterleavedLoadCombinePass.cpp870 Value *BasePtr; in computeFromLI() local
880 computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr, DL); in computeFromLI()
883 Result.PV = BasePtr; in computeFromLI()
957 Value *&BasePtr, in computePolynomialFromPointer()
963 BasePtr = nullptr; in computePolynomialFromPointer()
974 computePolynomialFromPointer(*CI.getOperand(0), Result, BasePtr, DL); in computePolynomialFromPointer()
977 BasePtr = &Ptr; in computePolynomialFromPointer()
991 BasePtr = GEP.getPointerOperand(); in computePolynomialFromPointer()
1009 BasePtr = nullptr; in computePolynomialFromPointer()
1026 BasePtr = GEP.getPointerOperand(); in computePolynomialFromPointer()
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H A DMachineOperand.cpp979 const Value *BasePtr = V.get<const Value *>(); in isDereferenceable() local
980 if (BasePtr == nullptr) in isDereferenceable()
984 BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL); in isDereferenceable()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp324 SDValue BasePtr = ST->getBasePtr(); in select() local
327 if (isa<FrameIndexSDNode>(BasePtr) || isa<ConstantSDNode>(BasePtr) || in select()
328 BasePtr.isUndef()) { in select()
332 const RegisterSDNode *RN = dyn_cast<RegisterSDNode>(BasePtr.getOperand(0)); in select()
338 int CST = (int)cast<ConstantSDNode>(BasePtr.getOperand(1))->getZExtValue(); in select()
343 SDValue Ops[] = {BasePtr.getOperand(0), Offset, ST->getValue(), Chain}; in select()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp115 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP); in eliminateFrameIndex() local
136 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
153 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64StackTagging.cpp87 Value *BasePtr; member in __anonce6747890111::InitializerBuilder
103 InitializerBuilder(uint64_t Size, const DataLayout *DL, Value *BasePtr, in InitializerBuilder() argument
106 : Size(Size), DL(DL), BasePtr(BasePtr), SetTagFn(SetTagFn), in InitializerBuilder()
239 Value *Ptr = BasePtr; in emitZeroes()
249 Value *Ptr = BasePtr; in emitUndef()
258 Value *Ptr = BasePtr; in emitPair()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp241 Register BasePtr = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
242 FI->setBasePointerVreg(BasePtr); in emitPrologue()
243 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), BasePtr) in emitPrologue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp423 SDValue BasePtr = LD->getBasePtr(); in LowerLOAD() local
429 if (DAG.isBaseWithConstantOffset(BasePtr) && in LowerLOAD()
430 isWordAligned(BasePtr->getOperand(0), DAG)) { in LowerLOAD()
431 SDValue NewBasePtr = BasePtr->getOperand(0); in LowerLOAD()
432 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue(); in LowerLOAD()
436 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) && in LowerLOAD()
439 BasePtr->getValueType(0)); in LowerLOAD()
446 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr, in LowerLOAD()
449 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in LowerLOAD()
470 Entry.Node = BasePtr; in LowerLOAD()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/CodeView/
H A DSymbolRecordMapping.cpp505 case EncodedFramePtrReg::BasePtr: return RegisterId::EBX; in decodeFramePtrReg()
513 case EncodedFramePtrReg::BasePtr: return RegisterId::R13; in decodeFramePtrReg()
539 return EncodedFramePtrReg::BasePtr; in encodeFramePtrReg()
551 return EncodedFramePtrReg::BasePtr; in encodeFramePtrReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/
H A DMemProfiler.cpp381 auto *BasePtr = CI->getOperand(0 + OpOffset); in isInterestingMemoryAccess() local
382 auto *Ty = cast<PointerType>(BasePtr->getType())->getElementType(); in isInterestingMemoryAccess()
390 Access.Addr = BasePtr; in isInterestingMemoryAccess()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DLowerMatrixIntrinsics.cpp132 Value *computeVectorAddr(Value *BasePtr, Value *VecIdx, Value *Stride, in computeVectorAddr() argument
139 unsigned AS = cast<PointerType>(BasePtr->getType())->getAddressSpace(); in computeVectorAddr()
147 VecStart = BasePtr; in computeVectorAddr()
149 VecStart = Builder.CreateGEP(EltType, BasePtr, VecStart, "vec.gep"); in computeVectorAddr()
751 Value *createElementPtr(Value *BasePtr, Type *EltType, IRBuilder<> &Builder) { in createElementPtr() argument
752 unsigned AS = cast<PointerType>(BasePtr->getType())->getAddressSpace(); in createElementPtr()
754 return Builder.CreatePointerCast(BasePtr, EltPtrType); in createElementPtr()
H A DSROA.cpp1400 static Value *buildGEP(IRBuilderTy &IRB, Value *BasePtr, in buildGEP() argument
1404 return BasePtr; in buildGEP()
1409 return BasePtr; in buildGEP()
1411 return IRB.CreateInBoundsGEP(BasePtr->getType()->getPointerElementType(), in buildGEP()
1412 BasePtr, Indices, NamePrefix + "sroa_idx"); in buildGEP()
1425 Value *BasePtr, Type *Ty, Type *TargetTy, in getNaturalGEPWithType() argument
1429 return buildGEP(IRB, BasePtr, Indices, NamePrefix); in getNaturalGEPWithType()
1432 unsigned OffsetSize = DL.getIndexTypeSizeInBits(BasePtr->getType()); in getNaturalGEPWithType()
1461 return buildGEP(IRB, BasePtr, Indices, NamePrefix); in getNaturalGEPWithType()
4002 Instruction *BasePtr = cast<Instruction>(LI->getPointerOperand()); in presplitLoadsAndStores() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1768 SDValue BasePtr = ST->getBasePtr(); in tryStore() local
1775 if (SelectDirectAddr(BasePtr, Addr)) { in tryStore()
1792 ? SelectADDRsi64(BasePtr.getNode(), BasePtr, Base, Offset) in tryStore()
1793 : SelectADDRsi(BasePtr.getNode(), BasePtr, Base, Offset)) { in tryStore()
1811 ? SelectADDRri64(BasePtr.getNode(), BasePtr, Base, Offset) in tryStore()
1812 : SelectADDRri(BasePtr.getNode(), BasePtr, Base, Offset)) { in tryStore()
1856 BasePtr, in tryStore()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp2255 SDValue BasePtr = cast<MemSDNode>(N)->getBasePtr(); in rebalanceAddressTrees() local
2256 if (BasePtr.getOpcode() != ISD::ADD) in rebalanceAddressTrees()
2260 if (RootWeights.count(BasePtr.getNode())) in rebalanceAddressTrees()
2269 Worklist.push_back(BasePtr.getOperand(0).getNode()); in rebalanceAddressTrees()
2270 Worklist.push_back(BasePtr.getOperand(1).getNode()); in rebalanceAddressTrees()
2294 RootWeights[BasePtr.getNode()] = -1; in rebalanceAddressTrees()
2295 SDValue NewBasePtr = balanceSubTree(BasePtr.getNode(), /*TopLevel=*/ true); in rebalanceAddressTrees()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp372 const DstOp &Dst, const SrcOp &BasePtr, in buildLoadFromOffset() argument
379 return buildLoad(Dst, BasePtr, *OffsetMMO); in buildLoadFromOffset()
381 LLT PtrTy = BasePtr.getLLTTy(*getMRI()); in buildLoadFromOffset()
384 auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset); in buildLoadFromOffset()

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