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Searched refs:BW (Results 1 – 25 of 95) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp161 unsigned BW = Ty->getPrimitiveSizeInBits(); in INITIALIZE_PASS_DEPENDENCY() local
162 if (BW != 32 && BW != 64) in INITIALIZE_PASS_DEPENDENCY()
174 APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL); in INITIALIZE_PASS_DEPENDENCY()
185 uint32_t U = BW - std::max(SL, SR); in INITIALIZE_PASS_DEPENDENCY()
200 APInt C = APInt::getHighBitsSet(BW, BW-U); in INITIALIZE_PASS_DEPENDENCY()
212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonBitTracker.cpp295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate() argument
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
300 while (I*BW < Ws) { in evaluate()
301 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
H A DHexagonConstPropagation.cpp1595 unsigned BW = A1.getBitWidth(); in evaluateZEXTi() local
1596 (void)BW; in evaluateZEXTi()
1597 assert(Width >= Bits && BW >= Bits); in evaluateZEXTi()
1626 unsigned BW = A1.getBitWidth(); in evaluateSEXTi() local
1627 assert(Width >= Bits && BW >= Bits); in evaluateSEXTi()
1636 if (BW <= 64 && Bits != 0) { in evaluateSEXTi()
1661 if (Bits < BW) in evaluateSEXTi()
1691 unsigned BW = A1.getBitWidth(); in evaluateCLBi() local
1699 Result = APInt(BW, static_cast<uint64_t>(Count), false); in evaluateCLBi()
1726 unsigned BW = A1.getBitWidth(); in evaluateCTBi() local
[all …]
H A DBitTracker.cpp350 uint16_t BW = getRegBitWidth(RR); in getCell() local
355 return RegisterCell::self(0, BW); in getCell()
362 return RegisterCell::self(0, BW); in getCell()
372 return RegisterCell::top(BW); in getCell()
424 uint16_t BW = A.getBitWidth(); in eIMM() local
425 assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow"); in eIMM()
426 RegisterCell Res(BW); in eIMM()
427 for (uint16_t i = 0; i < BW; ++i) in eIMM()
H A DHexagonExpandCondsets.cpp236 bool isIntReg(RegisterRef RR, unsigned &BW);
1095 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg() argument
1100 BW = 32; in isIntReg()
1104 BW = (RR.Sub != 0) ? 32 : 64; in isIntReg()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/ft32/
H A Dft32.md327 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,BW,r,r,r,r,A,r,r")
328 (match_operand:SI 1 "ft32_general_movsrc_operand" "r,r,BW,A,S,i,r,e,f"))]
370 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "BW,r,f")))]
387 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "BW,r,f")))]
403 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r,r")
404 (match_operand:QI 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,e,f"))]
451 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r,r")
452 (match_operand:HI 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,e,f"))]
479 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r")
480 (match_operand:SF 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,f"))]
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/ft32/
H A Dft32.md327 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,BW,r,r,r,r,A,r,r")
328 (match_operand:SI 1 "ft32_general_movsrc_operand" "r,r,BW,A,S,i,r,e,f"))]
370 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "BW,r,f")))]
387 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "BW,r,f")))]
403 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r,r")
404 (match_operand:QI 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,e,f"))]
451 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r,r")
452 (match_operand:HI 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,e,f"))]
479 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r")
480 (match_operand:SF 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,f"))]
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/cris/
H A Dcris.md185 (define_mode_iterator BW [HI QI])
380 (define_insn "*cmp_ext<BW:mode><NZVCSET:mode>"
385 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
408 (define_insn "*cmp<BW:mode><NZVCSET:mode>"
411 (match_operand:BW 0 "nonimmediate_operand" "<cmp_op0c>")
412 (match_operand:BW 1 "general_operand" "<cmp_op1c>")))]
719 [(set (match_operand:BW 2 "register_operand" "=r")
720 (match_operand:BW 1 "memory_operand" "m"))
721 (set (match_operand:BW 0 "register_operand" "=x")
727 [(set (match_operand:BW 2 "register_operand" "=&r")
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/cris/
H A Dcris.md213 (define_mode_iterator BW [HI QI])
268 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m")
279 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m")
355 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
368 [(match_operand:BW 0 "memory_operand" "Q>,m")])
397 (compare (match_operand:BW 0 "nonimmediate_operand" "r,r, Q>,r,m")
398 (match_operand:BW 1 "general_operand" "r,Q>,r, g,r")))]
603 [(set (match_operand:BW 0 "register_operand" "=r,r")
604 (mem:BW (plus:SI
641 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp455 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in generateCondForPow() local
457 if (BW == 8) in generateCondForPow()
459 else if (BW == 16) in generateCondForPow()
461 else if (BW == 32) in generateCondForPow()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/ADT/
H A DBitVector.h789 BitWord BW = Bits[i]; in applyMask() local
794 if (AddBits) BW |= BitWord(M) << b; in applyMask()
795 else BW &= ~(BitWord(M) << b); in applyMask()
797 Bits[i] = BW; in applyMask()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp983 unsigned BW = VT.getScalarSizeInBits(); in ExpandSEXTINREG() local
985 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT); in ExpandSEXTINREG()
1267 unsigned BW = VT.getScalarSizeInBits(); in ExpandUINT_TO_FLOAT() local
1268 assert((BW == 64 || BW == 32) && in ExpandUINT_TO_FLOAT()
1271 SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT); in ExpandUINT_TO_FLOAT()
1276 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF; in ExpandUINT_TO_FLOAT()
1281 DAG.getConstantFP(1ULL << (BW / 2), DL, Node->getValueType(0)); in ExpandUINT_TO_FLOAT()
/netbsd-src/external/gpl3/binutils/dist/cpu/
H A Dcris.cpu2035 (BW)
2037 ((BW tmpops) (SI newval))
2063 (BW)
2065 ((BW tmpops) (SI newval))
2433 (BW)
2436 Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit))
2464 (BW)
2467 Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit))
2513 (BW)
2516 (set tmp (ext SI (cris-get-mem BW Rs)))
[all …]
H A Dm32c.cpu7279 ; add.BW:Q #imm4,sp (m16 #7)
7284 ; add.BW:G #imm,sp (m16 #6)
7286 ; add.BW:G src,dst (m16 #4 m32 #6)
7300 ; add.BW:S #imm,dst2 (m32 #4)
7323 ; adc.BW:G src,dst
7385 ; dadc.BW src,dst
7403 ; dadd.BW src,dst
7456 ; and.BW:G src,dst (m16 #3 m32 #3)
7460 ; and.BW:S #imm,dst2 (m32 #2)
7743 ; cmp.BW:G src,dst (m16 #4 m32 #5)
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/cpu/
H A Dcris.cpu2034 (BW)
2036 ((BW tmpops) (SI newval))
2062 (BW)
2064 ((BW tmpops) (SI newval))
2432 (BW)
2435 Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit))
2463 (BW)
2466 Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit))
2512 (BW)
2515 (set tmp (ext SI (cris-get-mem BW Rs)))
[all …]
H A Dm32c.cpu7279 ; add.BW:Q #imm4,sp (m16 #7)
7284 ; add.BW:G #imm,sp (m16 #6)
7286 ; add.BW:G src,dst (m16 #4 m32 #6)
7300 ; add.BW:S #imm,dst2 (m32 #4)
7323 ; adc.BW:G src,dst
7385 ; dadc.BW src,dst
7403 ; dadd.BW src,dst
7456 ; and.BW:G src,dst (m16 #3 m32 #3)
7460 ; and.BW:S #imm,dst2 (m32 #2)
7743 ; cmp.BW:G src,dst (m16 #4 m32 #5)
[all …]
/netbsd-src/external/gpl3/gdb.old/dist/cpu/
H A Dcris.cpu2034 (BW)
2036 ((BW tmpops) (SI newval))
2062 (BW)
2064 ((BW tmpops) (SI newval))
2432 (BW)
2435 Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit))
2463 (BW)
2466 Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit))
2512 (BW)
2515 (set tmp (ext SI (cris-get-mem BW Rs)))
[all …]
H A Dm32c.cpu7279 ; add.BW:Q #imm4,sp (m16 #7)
7284 ; add.BW:G #imm,sp (m16 #6)
7286 ; add.BW:G src,dst (m16 #4 m32 #6)
7300 ; add.BW:S #imm,dst2 (m32 #4)
7323 ; adc.BW:G src,dst
7385 ; dadc.BW src,dst
7403 ; dadd.BW src,dst
7456 ; and.BW:G src,dst (m16 #3 m32 #3)
7460 ; and.BW:S #imm,dst2 (m32 #2)
7743 ; cmp.BW:G src,dst (m16 #4 m32 #5)
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DFloat2Int.cpp206 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in walkBackwards() local
207 auto Input = ConstantRange::getFull(BW); in walkBackwards()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/
H A DConstantRange.cpp668 auto BW = getBitWidth(); in castOp() local
669 APInt Min = APInt::getMinValue(BW).zextOrSelf(ResultBitWidth); in castOp()
670 APInt Max = APInt::getMaxValue(BW).zextOrSelf(ResultBitWidth); in castOp()
675 auto BW = getBitWidth(); in castOp() local
676 APInt SMin = APInt::getSignedMinValue(BW).sextOrSelf(ResultBitWidth); in castOp()
677 APInt SMax = APInt::getSignedMaxValue(BW).sextOrSelf(ResultBitWidth); in castOp()
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dmsp430-decode.opc94 #define BW(x) msp430->size = (x ? 8 : 16)
361 opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
364 opcode:9 BW:1 Ad:2 DSreg:4
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dmsp430-decode.opc94 #define BW(x) msp430->size = (x ? 8 : 16)
361 opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
364 opcode:9 BW:1 Ad:2 DSreg:4
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/AST/
H A DDeclObjC.h1932 QualType T, TypeSourceInfo *TInfo, AccessControl ac, Expr *BW, in ObjCIvarDecl() argument
1934 : FieldDecl(ObjCIvar, DC, StartLoc, IdLoc, Id, T, TInfo, BW, in ObjCIvarDecl()
1943 AccessControl ac, Expr *BW = nullptr,
1991 QualType T, Expr *BW) in ObjCAtDefsFieldDecl() argument
1994 BW, /*Mutable=*/false, /*HasInit=*/ICIS_NoInit) {} in ObjCAtDefsFieldDecl()
2002 QualType T, Expr *BW);
/netbsd-src/external/gpl3/gdb/dist/cpu/
H A Dm32c.cpu7279 ; add.BW:Q #imm4,sp (m16 #7)
7284 ; add.BW:G #imm,sp (m16 #6)
7286 ; add.BW:G src,dst (m16 #4 m32 #6)
7300 ; add.BW:S #imm,dst2 (m32 #4)
7323 ; adc.BW:G src,dst
7385 ; dadc.BW src,dst
7403 ; dadd.BW src,dst
7456 ; and.BW:G src,dst (m16 #3 m32 #3)
7460 ; and.BW:S #imm,dst2 (m32 #2)
7743 ; cmp.BW:G src,dst (m16 #4 m32 #5)
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td416 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
419 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
423 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
424 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;

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