Searched refs:BL2 (Results 1 – 2 of 2) sorted by relevance
47 #define BL2 2 macro52 #define BL2 1 macro58 #define OSIOP_SDID (0x00+BL2) /* rw: SCSI destination ID */63 #define OSIOP_SODL (0x04+BL2) /* rw: SCSI Output Data Latch */68 #define OSIOP_SBDL (0x08+BL2) /* ro: SCSI Bus Data Lines */73 #define OSIOP_SSTAT1 (0x0c+BL2) /* ro: SCSI status reg 1 */80 #define OSIOP_CTEST2 (0x14+BL2) /* ro: Chip test register 2 */85 #define OSIOP_CTEST6 (0x18+BL2) /* rw: Chip test register 6 */92 #define OSIOP_CTEST8 (0x20+BL2) /* rw: Chip test register 8 */98 #define OSIOP_DBC2 (0x24+BL2) /* rw: DMA Byte Counter reg 2 */[all …]
7735 insn from BL2 is after the insn from BL.