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Searched refs:ArgDescriptor (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.h23 struct ArgDescriptor { struct
40 constexpr ArgDescriptor(unsigned Val = 0, unsigned Mask = ~0u, argument
44 static constexpr ArgDescriptor createRegister(Register Reg, argument
46 return ArgDescriptor(Reg, Mask, false, true);
49 static constexpr ArgDescriptor createStack(unsigned Offset,
51 return ArgDescriptor(Offset, Mask, true, true);
54 static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, in createArg() argument
56 return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet); in createArg()
92 inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) { argument
124 ArgDescriptor PrivateSegmentBuffer;
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H A DAMDGPUArgumentUsageInfo.cpp26 void ArgDescriptor::print(raw_ostream &OS, in print()
88 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
152 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3); in fixedABILayout()
153 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5); in fixedABILayout()
154 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
158 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9); in fixedABILayout()
159 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
162 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
163 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
164 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
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H A DSIMachineFunctionInfo.cpp79 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
134 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
201 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
208 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
215 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
223 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
230 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
237 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
244 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
508 const ArgDescriptor &Arg) { in convertArgumentInfo()
H A DSIMachineFunctionInfo.h580 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
586 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
592 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
598 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
604 void setWorkItemIDX(ArgDescriptor Arg) {
608 void setWorkItemIDY(ArgDescriptor Arg) {
612 void setWorkItemIDZ(ArgDescriptor Arg) {
618 = ArgDescriptor::createRegister(getNextSystemSGPR());
624 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
699 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
H A DAMDGPUCallLowering.cpp782 const ArgDescriptor *OutgoingArg; in passSpecialInputs()
791 const ArgDescriptor *IncomingArg; in passSpecialInputs()
818 const ArgDescriptor *OutgoingArg; in passSpecialInputs()
840 const ArgDescriptor *IncomingArgX = std::get<0>(WorkitemIDX); in passSpecialInputs()
841 const ArgDescriptor *IncomingArgY = std::get<0>(WorkitemIDY); in passSpecialInputs()
842 const ArgDescriptor *IncomingArgZ = std::get<0>(WorkitemIDZ); in passSpecialInputs()
877 ArgDescriptor IncomingArg = ArgDescriptor::createArg( in passSpecialInputs()
H A DAMDGPUTargetMachine.cpp1308 ArgDescriptor &Arg, unsigned UserSGPRs, in parseMachineFunctionInfo()
1322 Arg = ArgDescriptor::createRegister(Reg); in parseMachineFunctionInfo()
1324 Arg = ArgDescriptor::createStack(A->StackOffset); in parseMachineFunctionInfo()
1327 Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue()); in parseMachineFunctionInfo()
H A DAMDGPUISelLowering.h25 struct ArgDescriptor;
312 const ArgDescriptor &Arg) const;
H A DAMDGPULegalizerInfo.h94 const ArgDescriptor *Arg,
H A DSIISelLowering.cpp1617 const ArgDescriptor *InputPtrReg; in lowerKernArgParameterPtr()
1766 const ArgDescriptor *Reg; in getPreloadedValue()
1837 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialEntryInputVGPRs()
1843 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1850 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1857 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1864 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1873 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u, in allocateVGPR32Input()
1874 ArgDescriptor Arg = ArgDescriptor()) { in allocateVGPR32Input()
1876 return ArgDescriptor::createArg(Arg, Mask); in allocateVGPR32Input()
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H A DAMDGPULegalizerInfo.cpp2721 const ArgDescriptor *Arg, in loadInputValue()
2755 const ArgDescriptor *Arg; in loadInputValue()
H A DAMDGPUISelLowering.cpp4169 const ArgDescriptor &Arg) const { in loadInputValue()