Searched refs:AddSubOpc (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
354 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
357 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| H A D | ARMBaseInstrInfo.h | 506 unsigned &AddSubOpc, bool &NegAcc,
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| H A D | ARMBaseInstrInfo.cpp | 85 uint16_t AddSubOpc; // Expanded add / sub opcode member
119 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
4890 unsigned &AddSubOpc, in isFpMLxInstruction() argument
4898 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 170 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
184 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
187 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
197 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
201 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
216 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12251 unsigned ShiftAmt, AddSubOpc; in performMulCombine() local
12265 AddSubOpc = ISD::ADD; in performMulCombine()
12268 AddSubOpc = ISD::SUB; in performMulCombine()
12278 AddSubOpc = ISD::SUB; in performMulCombine()
12282 AddSubOpc = ISD::ADD; in performMulCombine()
12295 SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1); in performMulCombine()
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