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Searched refs:getOpcode (Results 1 – 25 of 445) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp81 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRri()
82 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRri()
83 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRri()
86 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRri()
101 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
106 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
118 if (Addr.getOpcode() == ISD::FrameIndex) return false; in SelectADDRrr()
119 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRrr()
120 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRrr()
121 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRrr()
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H A DDelaySlotFiller.cpp121 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
122 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
128 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
129 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
180 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) in findDelayInstr()
183 if (slot->getOpcode() == SP::RETL) { in findDelayInstr()
187 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
188 || J->getOpcode() == SP::RESTOREri) { in findDelayInstr()
282 switch(MI->getOpcode()) { in insertCallDefsUses()
321 if (MO.isImplicit() && MI->getOpcode() == SP::RETL) in insertDefsUses()
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/minix3/external/bsd/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h35 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
39 return Info->get(Inst.getOpcode()).isConditionalBranch(); in isConditionalBranch()
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); in isUnconditionalBranch()
47 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
51 return Info->get(Inst.getOpcode()).isCall(); in isCall()
55 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
59 return Info->get(Inst.getOpcode()).isTerminator(); in isTerminator()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp129 if (II->getOpcode() == TargetOpcode::KILL) in INITIALIZE_PASS_DEPENDENCY()
179 if (MII->getOpcode() == Hexagon::J2_call) in commonChecksToProhibitNewValueJump()
193 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
194 MII->getOpcode() == TargetOpcode::PHI || in commonChecksToProhibitNewValueJump()
195 MII->getOpcode() == TargetOpcode::COPY) in commonChecksToProhibitNewValueJump()
202 if (MII->getOpcode() == Hexagon::TFR_condset_ii || in commonChecksToProhibitNewValueJump()
203 MII->getOpcode() == Hexagon::TFR_condset_ri || in commonChecksToProhibitNewValueJump()
204 MII->getOpcode() == Hexagon::TFR_condset_ir || in commonChecksToProhibitNewValueJump()
205 MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
206 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
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H A DHexagonRegisterInfo.cpp145 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && in eliminateFrameIndex()
153 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { in eliminateFrameIndex()
162 if ( (MI.getOpcode() == Hexagon::L2_loadri_io) || in eliminateFrameIndex()
163 (MI.getOpcode() == Hexagon::L2_loadrd_io) || in eliminateFrameIndex()
164 (MI.getOpcode() == Hexagon::L2_loadrh_io) || in eliminateFrameIndex()
165 (MI.getOpcode() == Hexagon::L2_loadruh_io) || in eliminateFrameIndex()
166 (MI.getOpcode() == Hexagon::L2_loadrb_io) || in eliminateFrameIndex()
167 (MI.getOpcode() == Hexagon::L2_loadrub_io) || in eliminateFrameIndex()
168 (MI.getOpcode() == Hexagon::LDriw_f) || in eliminateFrameIndex()
169 (MI.getOpcode() == Hexagon::LDrid_f)) { in eliminateFrameIndex()
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H A DHexagonSplitTFRCondSets.cpp94 switch(MI->getOpcode()) { in runOnMachineFunction()
101 if (MI->getOpcode() == Hexagon::TFR_condset_rr_f) { in runOnMachineFunction()
105 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { in runOnMachineFunction()
136 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) { in runOnMachineFunction()
141 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) { in runOnMachineFunction()
157 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) { in runOnMachineFunction()
162 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) { in runOnMachineFunction()
185 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) { in runOnMachineFunction()
194 } else if (MI->getOpcode() == Hexagon::TFR_condset_ii_f ) { in runOnMachineFunction()
H A DHexagonISelDAGToDAG.cpp392 if (Const32->getOpcode() == HexagonISD::CONST32 && in SelectBaseOffsetLoad()
774 if ((Const32->getOpcode() == HexagonISD::CONST32) && in SelectBaseOffsetStore()
777 if (Base.getOpcode() == ISD::TargetGlobalAddress) { in SelectBaseOffsetStore()
851 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul()
858 } else if (MulOp0.getOpcode() == ISD::LOAD) { in SelectMul()
877 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul()
884 } else if (MulOp1.getOpcode() == ISD::LOAD) { in SelectMul()
916 if (N0.getOpcode() == ISD::SETCC) { in SelectSelect()
918 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) { in SelectSelect()
1000 if (Shift.getOpcode() != ISD::SRL) { in SelectTruncate()
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/minix3/external/bsd/llvm/dist/llvm/unittests/Transforms/Utils/
H A DIntegerDivision.cpp42 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv); in TEST()
47 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); in TEST()
50 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::Sub); in TEST()
72 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv); in TEST()
77 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp); in TEST()
80 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::PHI); in TEST()
102 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); in TEST()
107 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); in TEST()
110 EXPECT_TRUE(Remainder && Remainder->getOpcode() == Instruction::Sub); in TEST()
132 EXPECT_TRUE(BB->front().getOpcode() == Instruction::URem); in TEST()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCBranchSelector.cpp143 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) in runOnMachineFunction()
145 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) && in runOnMachineFunction()
148 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || in runOnMachineFunction()
149 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && in runOnMachineFunction()
188 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
199 } else if (I->getOpcode() == PPC::BC) { in runOnMachineFunction()
202 } else if (I->getOpcode() == PPC::BCn) { in runOnMachineFunction()
205 } else if (I->getOpcode() == PPC::BDNZ) { in runOnMachineFunction()
207 } else if (I->getOpcode() == PPC::BDNZ8) { in runOnMachineFunction()
209 } else if (I->getOpcode() == PPC::BDZ) { in runOnMachineFunction()
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H A DPPCInstrInfo.cpp163 switch (MI.getOpcode()) { in isCoalescableExtInstr()
177 switch (MI->getOpcode()) { in isLoadFromStackSlot()
203 switch (MI->getOpcode()) { in isStoreToStackSlot()
233 if (MI->getOpcode() != PPC::RLWIMI && in commuteInstruction()
234 MI->getOpcode() != PPC::RLWIMIo) in commuteInstruction()
311 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode()); in findCommutedOpIndices()
369 if (LastInst->getOpcode() == PPC::B) { in AnalyzeBranch()
374 } else if (LastInst->getOpcode() == PPC::BCC) { in AnalyzeBranch()
382 } else if (LastInst->getOpcode() == PPC::BC) { in AnalyzeBranch()
390 } else if (LastInst->getOpcode() == PPC::BCn) { in AnalyzeBranch()
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/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h179 inline unsigned getOpcode() const;
407 unsigned getOpcode() const { return (unsigned short)NodeType; }
915 inline unsigned SDValue::getOpcode() const {
916 return Node->getOpcode();
1026 return isBinOpWithFlags(N->getOpcode());
1071 return N->getOpcode() == ISD::ADDRSPACECAST;
1158 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1165 return N->getOpcode() == ISD::LOAD ||
1166 N->getOpcode() == ISD::STORE ||
1167 N->getOpcode() == ISD::PREFETCH ||
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DR600EmitClauseMarkers.cpp42 switch (MI->getOpcode()) { in OccupiedDwords()
56 if (TII->isLDSRetInstr(MI->getOpcode())) in OccupiedDwords()
60 TII->isCubeOp(MI->getOpcode()) || in OccupiedDwords()
61 TII->isReductionOp(MI->getOpcode())) in OccupiedDwords()
75 if (TII->isALUInstr(MI->getOpcode())) in isALU()
77 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) in isALU()
79 switch (MI->getOpcode()) { in isALU()
93 switch (MI->getOpcode()) { in IsTrivialInst()
122 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4) in SubstituteKCacheBank()
127 assert((TII->isALUInstr(MI->getOpcode()) || in SubstituteKCacheBank()
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H A DR600Packetizer.cpp76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); in getPreviousVector()
93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector()
102 if (BI->getOpcode() == AMDGPU::DOT4_r600 || in getPreviousVector()
103 BI->getOpcode() == AMDGPU::DOT4_eg) { in getPreviousVector()
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); in substitutePV()
175 if (!TII->isALUInstr(MI->getOpcode())) in isSoloInstruction()
177 if (MI->getOpcode() == AMDGPU::GROUP_BARRIER) in isSoloInstruction()
181 if (TII->isLDSInstr(MI->getOpcode())) in isSoloInstruction()
193 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel), in isLegalToPacketizeTogether()
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H A DR600InstrInfo.cpp41 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; in isTrig()
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; in isVector()
164 if (isALUInstr(MI->getOpcode())) in canBeConsideredALU()
166 if (isVector(*MI) || isCubeOp(MI->getOpcode())) in canBeConsideredALU()
168 switch (MI->getOpcode()) { in canBeConsideredALU()
188 return isTransOnly(MI->getOpcode()); in isTransOnly()
196 return isVectorOnly(MI->getOpcode()); in isVectorOnly()
211 usesVertexCache(MI->getOpcode()); in usesVertexCache()
222 usesVertexCache(MI->getOpcode())) || in usesTextureCache()
223 usesTextureCache(MI->getOpcode()); in usesTextureCache()
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H A DSIInsertWaits.cpp142 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags; in getHwCounts()
149 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore())); in getHwCounts()
154 if (TII->isSMRD(MI.getOpcode())) { in getHwCounts()
187 if (MI.getOpcode() == AMDGPU::EXP) in isOpRelevant()
199 if (TII->isDS(MI.getOpcode())) { in isOpRelevant()
272 if ((LastOpcodeType == SMEM && TII->isSMRD(I->getOpcode())) || in pushInstruction()
280 if (TII->isSMRD(I->getOpcode())) in pushInstruction()
288 ExpInstrTypesSeen |= I->getOpcode() == AMDGPU::EXP ? 1 : 2; in pushInstruction()
316 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM) in insertWait()
389 if (MI.getOpcode() == AMDGPU::S_SENDMSG) in handleOperands()
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/minix3/external/bsd/llvm/dist/llvm/include/llvm/IR/
H A DOperator.h49 unsigned getOpcode() const { in getOpcode() function
51 return I->getOpcode(); in getOpcode()
52 return cast<ConstantExpr>(this)->getOpcode(); in getOpcode()
57 static unsigned getOpcode(const Value *V) { in getOpcode() function
59 return I->getOpcode(); in getOpcode()
61 return CE->getOpcode(); in getOpcode()
108 return I->getOpcode() == Instruction::Add || in classof()
109 I->getOpcode() == Instruction::Sub || in classof()
110 I->getOpcode() == Instruction::Mul || in classof()
111 I->getOpcode() == Instruction::Shl; in classof()
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H A DInstruction.h87 unsigned getOpcode() const { return getValueID() - InstructionVal; } in getOpcode() function
89 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); } in getOpcodeName()
90 bool isTerminator() const { return isTerminator(getOpcode()); } in isTerminator()
91 bool isBinaryOp() const { return isBinaryOp(getOpcode()); } in isBinaryOp()
92 bool isShift() { return isShift(getOpcode()); } in isShift()
93 bool isCast() const { return isCast(getOpcode()); } in isCast()
113 return getOpcode() == Shl || getOpcode() == LShr; in isLogicalShift()
118 return getOpcode() == AShr; in isArithmeticShift()
304 bool isCommutative() const { return isCommutative(getOpcode()); } in isCommutative()
313 bool isIdempotent() const { return isIdempotent(getOpcode()); } in isIdempotent()
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/minix3/external/bsd/llvm/dist/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp108 switch (I->getOpcode()) { in CanEvaluateShifted()
207 switch (I->getOpcode()) { in GetShiftedValue()
320 bool isLeftShift = I.getOpcode() == Instruction::Shl; in FoldShiftByConstant()
335 if (I.getOpcode() != Instruction::AShr && in FoldShiftByConstant()
353 if (BO->getOpcode() == Instruction::Mul && isLeftShift) in FoldShiftByConstant()
379 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName()); in FoldShiftByConstant()
393 if (I.getOpcode() == Instruction::Shl) in FoldShiftByConstant()
396 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift"); in FoldShiftByConstant()
415 switch (Op0BO->getOpcode()) { in FoldShiftByConstant()
429 Value *X = Builder->CreateBinOp(Op0BO->getOpcode(), YS, V1, in FoldShiftByConstant()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64BranchRelaxation.cpp293 switch (MI->getOpcode()) { in getDestBlock()
346 assert(MI->getOpcode() == AArch64::Bcc && "Unexpected opcode!"); in invertBccCondition()
376 BMI->getOpcode() == AArch64::B) { in fixupConditionalBranch()
386 getBranchDisplacementBits(MI->getOpcode()))) { in fixupConditionalBranch()
390 unsigned OpNum = (MI->getOpcode() == AArch64::TBZW || in fixupConditionalBranch()
391 MI->getOpcode() == AArch64::TBNZW || in fixupConditionalBranch()
392 MI->getOpcode() == AArch64::TBZX || in fixupConditionalBranch()
393 MI->getOpcode() == AArch64::TBNZX) in fixupConditionalBranch()
397 MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode()))); in fixupConditionalBranch()
398 if (MI->getOpcode() == AArch64::Bcc) in fixupConditionalBranch()
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/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp136 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
496 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
504 switch (Op.getOpcode()) { in isNegatibleForFree()
558 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
564 switch (Op.getOpcode()) { in GetNegatedExpression()
607 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
613 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
620 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
638 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
645 if (N.getOpcode() != ISD::SELECT_CC || in isSetCCEquivalent()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.cpp91 } else if (MI.getOpcode() == AArch64::ADRP) { in tryAddingSymbolicOperand()
104 } else if (MI.getOpcode() == AArch64::ADDXri || in tryAddingSymbolicOperand()
105 MI.getOpcode() == AArch64::LDRXui || in tryAddingSymbolicOperand()
106 MI.getOpcode() == AArch64::LDRXl || in tryAddingSymbolicOperand()
107 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
108 if (MI.getOpcode() == AArch64::ADDXri) in tryAddingSymbolicOperand()
110 else if (MI.getOpcode() == AArch64::LDRXui) in tryAddingSymbolicOperand()
112 if (MI.getOpcode() == AArch64::LDRXl) { in tryAddingSymbolicOperand()
116 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
125 MI.getOpcode() == AArch64::ADDXri ? 0x91000000: 0xF9400000; in tryAddingSymbolicOperand()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp92 switch (MI.getOpcode()) { in isReadSpecialReg()
136 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS) in CanTailMerge()
183 if (LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
186 } else if (LastInst->getOpcode() == NVPTX::CBranch) { in AnalyzeBranch()
204 if (SecondLastInst->getOpcode() == NVPTX::CBranch && in AnalyzeBranch()
205 LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
214 if (SecondLastInst->getOpcode() == NVPTX::GOTO && in AnalyzeBranch()
215 LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
232 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch) in RemoveBranch()
243 if (I->getOpcode() != NVPTX::CBranch) in RemoveBranch()
/minix3/external/bsd/llvm/dist/llvm/lib/Analysis/
H A DCostModel.cpp173 unsigned Opcode = BinOp->getOpcode(); in matchPairwiseReductionAtLevel()
220 else if (NextLevelBinOp->getOpcode() != Opcode) in matchPairwiseReductionAtLevel()
284 Opcode = RdxStart->getOpcode(); in matchPairwiseReduction()
320 unsigned RdxOpcode = RdxStart->getOpcode(); in matchVectorSplittingReduction()
347 if (BinOp->getOpcode() != RdxOpcode) in matchVectorSplittingReduction()
384 switch (I->getOpcode()) { in getInstructionCost()
393 return TTI->getCFInstrCost(I->getOpcode()); in getInstructionCost()
417 return TTI->getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, in getInstructionCost()
423 return TTI->getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy); in getInstructionCost()
428 return TTI->getCmpSelInstrCost(I->getOpcode(), ValTy); in getInstructionCost()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/MCTargetDesc/
H A DR600MCCodeEmitter.cpp92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in EncodeInstruction()
93 if (MI.getOpcode() == AMDGPU::RETURN || in EncodeInstruction()
94 MI.getOpcode() == AMDGPU::FETCH_CLAUSE || in EncodeInstruction()
95 MI.getOpcode() == AMDGPU::ALU_CLAUSE || in EncodeInstruction()
96 MI.getOpcode() == AMDGPU::BUNDLE || in EncodeInstruction()
97 MI.getOpcode() == AMDGPU::KILL) { in EncodeInstruction()
175 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp65 int Opcode = MI->getOpcode(); in isLoadFromStackSlot()
87 int Opcode = MI->getOpcode(); in isStoreToStackSlot()
216 if (IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
221 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
242 unsigned SecondLastOpc = SecondLastInst->getOpcode(); in AnalyzeBranch()
248 && IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
260 if (IsBRU(SecondLastInst->getOpcode()) && in AnalyzeBranch()
261 IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
270 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
323 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) in RemoveBranch()
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