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Searched refs:addRegisterClass (Results 1 – 17 of 17) sorted by relevance

/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DSIISelLowering.cpp40 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
41 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
43 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
44 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
46 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
47 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
49 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass); in SITargetLowering()
50 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
51 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); in SITargetLowering()
53 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); in SITargetLowering()
[all …]
H A DR600ISelLowering.cpp36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1052 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1053 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1056 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1057 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1060 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); in MipsSETargetLowering()
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering()
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering()
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
247 addRegisterClass(Ty, RC); in addMSAIntType()
296 addRegisterClass(Ty, RC); in addMSAFloatType()
H A DMips16ISelLowering.cpp128 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp133 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering()
134 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
135 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
136 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering()
137 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering()
138 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp90 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering()
92 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering()
93 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering()
94 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering()
95 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering()
96 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); in SystemZTargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp64 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
65 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp297 addRegisterClass(MVT::i8, &X86::GR8RegClass); in resetOperationActions()
298 addRegisterClass(MVT::i16, &X86::GR16RegClass); in resetOperationActions()
299 addRegisterClass(MVT::i32, &X86::GR32RegClass); in resetOperationActions()
301 addRegisterClass(MVT::i64, &X86::GR64RegClass); in resetOperationActions()
666 addRegisterClass(MVT::f32, &X86::FR32RegClass); in resetOperationActions()
667 addRegisterClass(MVT::f64, &X86::FR64RegClass); in resetOperationActions()
700 addRegisterClass(MVT::f32, &X86::FR32RegClass); in resetOperationActions()
701 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in resetOperationActions()
735 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in resetOperationActions()
736 addRegisterClass(MVT::f32, &X86::RFP32RegClass); in resetOperationActions()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1373 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1374 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1375 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1376 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1378 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
126 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
382 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
494 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
495 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
496 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
497 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
560 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass); in PPCTargetLowering()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
660 addRegisterClass(VT, &AArch64::FPR64RegClass); in addDRTypeForNEON()
665 addRegisterClass(VT, &AArch64::FPR128RegClass); in addQRTypeForNEON()
/minix3/external/bsd/llvm/dist/llvm/docs/
H A DWritingAnLLVMBackend.rst1311 ``addRegisterClass`` method to specify which types are supported and which
1320 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
1321 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1322 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
H A DCodeGenerator.rst896 register class to use for them) by calling the ``addRegisterClass`` method in
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetLowering.h1214 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { in addRegisterClass() function
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp150 addRegisterClass(VT, &ARM::DPRRegClass); in addDRTypeForNEON()
155 addRegisterClass(VT, &ARM::DPairRegClass); in addQRTypeForNEON()
398 addRegisterClass(MVT::i32, &ARM::tGPRRegClass); in ARMTargetLowering()
400 addRegisterClass(MVT::i32, &ARM::GPRRegClass); in ARMTargetLowering()
403 addRegisterClass(MVT::f32, &ARM::SPRRegClass); in ARMTargetLowering()
404 addRegisterClass(MVT::f64, &ARM::DPRRegClass); in ARMTargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp76 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()