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Searched refs:Cond (Results 1 – 25 of 211) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp73 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
80 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
83 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
89 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in AnalyzeBranch()
100 const SmallVectorImpl<MachineOperand> &Cond) const { in BuildCondBr()
101 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
105 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
106 if (Cond[i].isReg()) in BuildCondBr()
107 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
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H A DMipsInstrInfo.h56 SmallVectorImpl<MachineOperand> &Cond,
63 const SmallVectorImpl<MachineOperand> &Cond,
67 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
71 SmallVectorImpl<MachineOperand> &Cond,
136 SmallVectorImpl<MachineOperand> &Cond) const;
139 const SmallVectorImpl<MachineOperand>& Cond) const;
/minix3/external/bsd/llvm/dist/clang/test/SemaCXX/
H A Dvector.cpp40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, in conditional() argument
43 __typeof__(Cond? c16 : c16) *c16p1 = &c16; in conditional()
44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; in conditional()
45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; in conditional()
46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; in conditional()
49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; in conditional()
50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; in conditional()
51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; in conditional()
52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; in conditional()
55 (void)(Cond? c16 : ll16); in conditional()
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/minix3/external/bsd/llvm/dist/clang/test/SemaTemplate/
H A Dvalue-dependent-null-pointer-constant.cpp5 const char *f0(bool Cond) { in f0()
6 return Cond? "honk" : N; in f0()
9 const char *f1(bool Cond) { in f1()
10 return Cond? N : "honk"; in f1()
H A Dinstantiate-expr-2.cpp92 struct Cond { struct
97 typedef Cond<true, int, char>::True True;
98 typedef Cond<true, int, char>::False False;
112 struct Cond { struct
120 typedef Cond<true, int, double>::Type Type;
/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in ReverseBranchCondition()
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
157 Cond[0].setImm(CC); in ReverseBranchCondition()
175 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
210 Cond.clear(); in AnalyzeBranch()
234 if (Cond.empty()) { in AnalyzeBranch()
237 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
243 assert(Cond.size() == 1); in AnalyzeBranch()
251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
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H A DMSP430InstrInfo.h76 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
80 SmallVectorImpl<MachineOperand> &Cond,
86 const SmallVectorImpl<MachineOperand> &Cond,
H A DMSP430BranchSelector.cpp152 SmallVector<MachineOperand, 1> Cond; in runOnMachineFunction() local
153 Cond.push_back(I->getOperand(1)); in runOnMachineFunction()
156 TII->ReverseBranchCondition(Cond); in runOnMachineFunction()
158 .addImm(4).addOperand(Cond[0]); in runOnMachineFunction()
/minix3/external/bsd/llvm/dist/llvm/test/Transforms/InstCombine/
H A Dudiv_select_to_select_shift.ll2 ; udiv X, (Select Cond, C1, C2) --> Select Cond, (shr X, C1), (shr X, C2)
9 define i64 @test(i64 %X, i1 %Cond ) {
11 %divisor1 = select i1 %Cond, i64 16, i64 8
13 %divisor2 = select i1 %Cond, i64 8, i64 0
H A Dstore.ll28 br i1 %C, label %Cond, label %Cond2
30 Cond:
44 ; CHECK-NEXT: %storemerge = phi i32 [ 47, %Cond2 ], [ -987654321, %Cond ]
52 br i1 %C, label %Cond, label %Cont
54 Cond:
64 ; CHECK-NEXT: %storemerge = phi i32 [ -987654321, %Cond ], [ 47, %0 ]
71 br i1 %C, label %Cond, label %Cont
73 Cond:
H A Dshift-sra.ll23 define i64 @test3(i1 %X, i64 %Y, i1 %Cond) {
24 br i1 %Cond, label %T, label %F
41 define i64 @test4(i1 %X, i64 %Y, i1 %Cond) {
42 br i1 %Cond, label %T, label %F
/minix3/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp196 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
229 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
230 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
251 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
252 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
284 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
288 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
292 if (Cond.empty()) { in InsertBranch()
297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
298 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
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H A DXCoreInstrInfo.h55 SmallVectorImpl<MachineOperand> &Cond,
60 const SmallVectorImpl<MachineOperand> &Cond,
83 SmallVectorImpl<MachineOperand> &Cond) const override;
/minix3/external/bsd/llvm/dist/llvm/test/Transforms/ADCE/
H A D2003-11-16-MissingPostDominanceInfo.ll6 br i1 %C, label %Cond, label %Done
8 Cond: ; preds = %0
11 Loop: ; preds = %Loop, %Cond
15 Done: ; preds = %Cond, %0
/minix3/external/bsd/llvm/dist/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.cpp69 DefinedSVal Cond, in assume() argument
72 if (Optional<Loc> LV = Cond.getAs<Loc>()) { in assume()
81 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); in assume()
84 return assume(state, Cond.castAs<NonLoc>(), Assumption); in assume()
115 NonLoc Cond, in assumeAux() argument
120 if (!canReasonAbout(Cond)) { in assumeAux()
122 SymbolRef sym = Cond.getAsSymExpr(); in assumeAux()
126 switch (Cond.getSubKind()) { in assumeAux()
131 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); in assumeAux()
182 bool b = Cond.castAs<nonloc::ConcreteInt>().getValue() != 0; in assumeAux()
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H A DSimpleConstraintManager.h36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond,
39 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption);
88 NonLoc Cond,
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1208 ISD::CondCode Cond, bool foldBooleans, in SimplifySetCC() argument
1213 switch (Cond) { in SimplifySetCC()
1228 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); in SimplifySetCC()
1245 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1247 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1250 Cond = ISD::SETNE; in SimplifySetCC()
1254 Cond = ISD::SETEQ; in SimplifySetCC()
1258 Zero, Cond); in SimplifySetCC()
1275 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1279 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
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/minix3/external/bsd/llvm/dist/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DConstraintManager.h68 DefinedSVal Cond,
75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { in assumeDual() argument
76 ProgramStateRef StTrue = assume(State, Cond, true); in assumeDual()
86 assert(assume(State, Cond, false) && "System is over constrained."); in assumeDual()
91 ProgramStateRef StFalse = assume(State, Cond, false); in assumeDual()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp172 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { in AnalyzeBranch() argument
189 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
207 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
253 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { in InsertBranch() argument
256 assert((Cond.size() == 1 || Cond.size() == 0) && in InsertBranch()
261 if (Cond.empty()) // Unconditional branch in InsertBranch()
264 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in InsertBranch()
270 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in InsertBranch()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp347 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
379 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
380 Cond.push_back(LastInst->getOperand(1)); in AnalyzeBranch()
387 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in AnalyzeBranch()
388 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
395 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in AnalyzeBranch()
396 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
405 Cond.push_back(MachineOperand::CreateImm(1)); in AnalyzeBranch()
406 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
416 Cond.push_back(MachineOperand::CreateImm(0)); in AnalyzeBranch()
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H A DPPCInstrInfo.h140 SmallVectorImpl<MachineOperand> &Cond,
145 const SmallVectorImpl<MachineOperand> &Cond,
150 const SmallVectorImpl<MachineOperand> &Cond,
155 const SmallVectorImpl<MachineOperand> &Cond,
176 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp124 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
136 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { in InsertBranch()
142 if (Cond.empty()) { in InsertBranch()
148 SmallVector<MachineOperand, 4> Cond; in InsertBranch() local
150 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, in InsertBranch()
155 ReverseBranchCondition(Cond); in InsertBranch()
157 return InsertBranch(MBB, TBB, nullptr, Cond, DL); in InsertBranch()
163 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); in InsertBranch()
168 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); in InsertBranch()
178 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h139 SmallVectorImpl<MachineOperand> &Cond,
144 const SmallVectorImpl<MachineOperand> &Cond,
147 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
149 const SmallVectorImpl<MachineOperand> &Cond, unsigned,
153 const SmallVectorImpl<MachineOperand> &Cond,
192 const SmallVectorImpl<MachineOperand> &Cond) const;
/minix3/external/bsd/llvm/dist/clang/lib/Sema/
H A DScopeInfo.cpp163 if (const ConditionalOperator *Cond = dyn_cast<ConditionalOperator>(E)) { in markSafeWeakUse() local
164 markSafeWeakUse(Cond->getTrueExpr()); in markSafeWeakUse()
165 markSafeWeakUse(Cond->getFalseExpr()); in markSafeWeakUse()
169 if (const BinaryConditionalOperator *Cond = in markSafeWeakUse() local
171 markSafeWeakUse(Cond->getCommon()); in markSafeWeakUse()
172 markSafeWeakUse(Cond->getFalseExpr()); in markSafeWeakUse()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DMachineBasicBlock.cpp389 SmallVector<MachineOperand, 4> Cond; in updateTerminator() local
391 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); in updateTerminator()
394 if (Cond.empty()) { in updateTerminator()
419 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); in updateTerminator()
427 if (TII->ReverseBranchCondition(Cond)) in updateTerminator()
430 TII->InsertBranch(*this, FBB, nullptr, Cond, dl); in updateTerminator()
433 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); in updateTerminator()
457 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); in updateTerminator()
463 if (TII->ReverseBranchCondition(Cond)) { in updateTerminator()
465 Cond.clear(); in updateTerminator()
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