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Searched refs:memory_clock (Results 1 – 22 of 22) sorted by relevance

/dflybsd-src/sys/dev/drm/radeon/
H A Drv740_dpm.c95 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) in rv740_get_dll_speed() argument
106 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed()
188 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
206 memory_clock, false, &dividers); in rv740_populate_mclk_value()
248 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
267 memory_clock); in rv740_populate_mclk_value()
272 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
406 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) in rv740_get_mclk_frequency_ratio() argument
410 if ((memory_clock < 10000) || (memory_clock > 47500)) in rv740_get_mclk_frequency_ratio()
413 mc_para_index = (u8)((memory_clock - 10000) / 2500); in rv740_get_mclk_frequency_ratio()
H A Drv770_dpm.h183 u32 engine_clock, u32 memory_clock,
204 u32 engine_clock, u32 memory_clock,
211 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
212 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
H A Dcypress_dpm.c474 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value() argument
501 memory_clock, strobe_mode, &dividers); in cypress_populate_mclk_value()
555 u32 vco_freq = memory_clock * dividers.post_div; in cypress_populate_mclk_value()
574 memory_clock); in cypress_populate_mclk_value()
597 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
611 u32 memory_clock, bool strobe_mode) in cypress_get_mclk_frequency_ratio() argument
617 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
619 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
622 mc_para_index = (u8)((memory_clock - 10000) / 2500); in cypress_get_mclk_frequency_ratio()
624 if (memory_clock < 65000) in cypress_get_mclk_frequency_ratio()
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H A Dcypress_dpm.h125 u32 engine_clock, u32 memory_clock);
157 u32 memory_clock, bool strobe_mode);
H A Drv730_dpm.c120 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
136 memory_clock, false, &dividers); in rv730_populate_mclk_value()
168 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
188 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
H A Dci_dpm.c2531 const u32 memory_clock, in ci_register_patching_mc_arb() argument
2543 if ((memory_clock > 100000) && (memory_clock <= 125000)) { in ci_register_patching_mc_arb()
2547 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { in ci_register_patching_mc_arb()
2823 u32 memory_clock, in ci_calculate_mclk_params() argument
2841 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in ci_calculate_mclk_params()
2868 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); in ci_calculate_mclk_params()
2870 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); in ci_calculate_mclk_params()
2895 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
2910 u32 memory_clock, in ci_populate_single_memory_level() argument
2920 memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
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H A Drv770_dpm.c322 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, in rv770_calculate_fractional_mpll_feedback_divider() argument
333 fyclk = (memory_clock * 8) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
335 fyclk = (memory_clock * 4) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
391 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
415 memory_clock, false, &dividers); in rv770_populate_mclk_value()
422 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, reference_clock, in rv770_populate_mclk_value()
449 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, in rv770_populate_mclk_value()
477 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
H A Dsi_dpm.c3823 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument
3827 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
3829 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
3832 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio()
3836 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) in si_get_mclk_frequency_ratio() argument
3841 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
3843 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
3846 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
3848 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
3850 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
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H A Dradeon_asic.h754 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
755 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
H A Dni_dpm.c2160 u32 memory_clock, in ni_populate_mclk_value() argument
2182 memory_clock, strobe_mode, &dividers); in ni_populate_mclk_value()
2236 u32 vco_freq = memory_clock * dividers.post_div; in ni_populate_mclk_value()
2255 memory_clock); in ni_populate_mclk_value()
2279 mclk->mclk_value = cpu_to_be32(memory_clock); in ni_populate_mclk_value()
/dflybsd-src/sys/dev/drm/amd/powerplay/smumgr/
H A Diceland_smumgr.c1046 uint32_t memory_clock, in iceland_calculate_mclk_params() argument
1068 memory_clock, &mpll_param, strobe_mode); in iceland_calculate_mclk_params()
1119 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1121 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1155 mclk->MclkFrequency = memory_clock; in iceland_calculate_mclk_params()
1169 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, in iceland_get_mclk_frequency_ratio() argument
1175 if (memory_clock < 12500) { in iceland_get_mclk_frequency_ratio()
1177 } else if (memory_clock > 47500) { in iceland_get_mclk_frequency_ratio()
1180 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in iceland_get_mclk_frequency_ratio()
1183 if (memory_clock < 65000) { in iceland_get_mclk_frequency_ratio()
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H A Dci_smumgr.c1023 uint32_t memory_clock, in ci_calculate_mclk_params() argument
1044 memory_clock, &mpll_param, strobe_mode); in ci_calculate_mclk_params()
1076 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1078 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1103 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
1117 static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, in ci_get_mclk_frequency_ratio() argument
1123 if (memory_clock < 12500) in ci_get_mclk_frequency_ratio()
1125 else if (memory_clock > 47500) in ci_get_mclk_frequency_ratio()
1128 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in ci_get_mclk_frequency_ratio()
1130 if (memory_clock < 65000) in ci_get_mclk_frequency_ratio()
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H A Dtonga_smumgr.c779 uint32_t memory_clock, in tonga_calculate_mclk_params() argument
801 memory_clock, &mpll_param, strobe_mode); in tonga_calculate_mclk_params()
861 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
863 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
896 mclk->MclkFrequency = memory_clock; in tonga_calculate_mclk_params()
910 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, in tonga_get_mclk_frequency_ratio() argument
916 if (memory_clock < 12500) in tonga_get_mclk_frequency_ratio()
918 else if (memory_clock > 47500) in tonga_get_mclk_frequency_ratio()
921 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in tonga_get_mclk_frequency_ratio()
923 if (memory_clock < 65000) in tonga_get_mclk_frequency_ratio()
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/dflybsd-src/sys/dev/drm/amd/powerplay/hwmgr/
H A Dppatomctrl.h294 …t_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_in…
297 …et_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
316 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
H A Dsmu7_hwmgr.c2918 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules()
2919 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()
2965 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
2969 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules()
2980 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
2989 if (mclk < smu7_ps->performance_levels[1].memory_clock) in smu7_apply_state_adjust_rules()
2990 mclk = smu7_ps->performance_levels[1].memory_clock; in smu7_apply_state_adjust_rules()
2992 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
2993 smu7_ps->performance_levels[1].memory_clock = mclk; in smu7_apply_state_adjust_rules()
2995 if (smu7_ps->performance_levels[1].memory_clock < in smu7_apply_state_adjust_rules()
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H A Dhardwaremanager.c374 pclock_info->min_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
384 pclock_info->max_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
H A Dppatomctrl.c176 uint32_t memory_clock) in atomctrl_set_engine_dram_timings_rv770() argument
189 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); in atomctrl_set_engine_dram_timings_rv770()
1280 const uint32_t memory_clock, in atomctrl_get_memory_clock_spread_spectrum() argument
1284 ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo); in atomctrl_get_memory_clock_spread_spectrum()
1319 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, in atomctrl_set_ac_timing_ai() argument
1327 memory_clock & SET_CLOCK_FREQ_MASK; in atomctrl_set_ac_timing_ai()
H A Dsmu7_hwmgr.h55 uint32_t memory_clock; member
H A Dsmu10_hwmgr.c910 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; in smu10_get_performance_level()
913 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ in smu10_get_performance_level()
H A Dsmu8_hwmgr.c1575 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; in smu8_get_performance_level()
1577 level->memory_clock = data->sys_info.nbp_memory_clock[0]; in smu8_get_performance_level()
/dflybsd-src/sys/dev/drm/amd/powerplay/inc/
H A Dhardwaremanager.h271 uint32_t memory_clock; member
/dflybsd-src/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c4289 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument
4293 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
4295 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
4298 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio()
4302 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) in si_get_mclk_frequency_ratio() argument
4307 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
4309 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
4312 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
4314 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
4316 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
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