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Searched refs:engineClock (Results 1 – 11 of 11) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega12_processpptables.c254 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; in init_powerplay_table_information()
256 …hwmgr->platform_descriptor.overdriveLimit.engineClock = powerplay_table->ODSettingsMax[ATOM_VEGA12… in init_powerplay_table_information()
266 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 in init_powerplay_table_information()
H A Dsmu8_hwmgr.c417 data->boot_power_level.engineClock = in smu8_construct_boot_state()
1310 return smu8_ps->levels[0].engineClock; in smu8_dpm_get_sclk()
1312 return smu8_ps->levels[smu8_ps->level-1].engineClock; in smu8_dpm_get_sclk()
1346 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; in smu8_dpm_get_pp_table_entry_callback()
1563 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()
1567 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { in smu8_get_performance_level()
1568 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()
1591 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); in smu8_get_current_shallow_sleep_clocks()
1592 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1]… in smu8_get_current_shallow_sleep_clocks()
H A Dvega10_hwmgr.c889 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega10_hwmgr_backend_init()
1324 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in vega10_setup_default_dpm_tables()
1325 hwmgr->platform_descriptor.overdriveLimit.engineClock = in vega10_setup_default_dpm_tables()
1527 hwmgr->platform_descriptor.overdriveLimit.engineClock; in vega10_populate_single_gfx_level()
3148 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3179 minimum_clocks.engineClock = stable_pstate_sclk; in vega10_apply_state_adjust_rules()
3200 if (sclk < minimum_clocks.engineClock) in vega10_apply_state_adjust_rules()
3201 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in vega10_apply_state_adjust_rules()
3202 max_limits->sclk : minimum_clocks.engineClock; in vega10_apply_state_adjust_rules()
4314 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_print_clock_levels()
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H A Dsmu8_hwmgr.h100 uint32_t engineClock; member
H A Dsmu7_hwmgr.c796 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in smu7_setup_dpm_tables_v1()
797 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()
2592 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu7_hwmgr_backend_init()
2925 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
2948 minimum_clocks.engineClock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()
2971 if (sclk < minimum_clocks.engineClock) in smu7_apply_state_adjust_rules()
2972 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in smu7_apply_state_adjust_rules()
2973 max_limits->sclk : minimum_clocks.engineClock; in smu7_apply_state_adjust_rules()
4512 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in smu7_print_clock_levels()
4813 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { in smu7_check_clk_voltage_valid()
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H A Dprocesspptables.c1019 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_overdrive_limits_V1_4()
1057 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); in init_overdrive_limits_V2_1()
1077 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; in init_overdrive_limits()
H A Dvega10_processpptables.c278 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
281 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
H A Dsmu10_hwmgr.c505 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu10_hwmgr_backend_init()
H A Dprocess_pptables_v1_0.c864 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
H A Dvega12_hwmgr.c411 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega12_hwmgr_backend_init()
/dflybsd-src/sys/dev/drm/amd/powerplay/inc/
H A Dhardwaremanager.h325 uint32_t engineClock; member