1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "regs.h"
30 #include "hard-reg-set.h"
31 #include "real.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
35 #include "flags.h"
36 #include "recog.h"
37 #include "obstack.h"
38 #include "tree.h"
39 #include "expr.h"
40 #include "optabs.h"
41 #include "except.h"
42 #include "function.h"
43 #include "output.h"
44 #include "basic-block.h"
45 #include "integrate.h"
46 #include "toplev.h"
47 #include "ggc.h"
48 #include "hashtab.h"
49 #include "tm_p.h"
50 #include "target.h"
51 #include "target-def.h"
52 #include "langhooks.h"
53 #include "reload.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
57 #include "intl.h"
58 #include "params.h"
59 #include "tm-constrs.h"
60 #if TARGET_XCOFF
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
62 #endif
63 #if TARGET_MACHO
64 #include "gstab.h" /* for N_SLINE */
65 #endif
66
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
69 #endif
70
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
73
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
107 not in save_size */
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
112 } rs6000_stack_t;
113
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
117 {
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
125 int ra_need_lr;
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
129 } machine_function;
130
131 /* Target cpu type */
132
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
135 {
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
140 };
141
142 /* Always emit branch hint bits. */
143 static GTY(()) bool rs6000_always_hint;
144
145 /* Schedule instructions for group formation. */
146 static GTY(()) bool rs6000_sched_groups;
147
148 /* Support for -msched-costly-dep option. */
149 const char *rs6000_sched_costly_dep_str;
150 enum rs6000_dependence_cost rs6000_sched_costly_dep;
151
152 /* Support for -minsert-sched-nops option. */
153 const char *rs6000_sched_insert_nops_str;
154 enum rs6000_nop_insertion rs6000_sched_insert_nops;
155
156 /* Support targetm.vectorize.builtin_mask_for_load. */
157 static GTY(()) tree altivec_builtin_mask_for_load;
158
159 /* Size of long double. */
160 int rs6000_long_double_type_size;
161
162 /* IEEE quad extended precision long double. */
163 int rs6000_ieeequad;
164
165 /* Whether -mabi=altivec has appeared. */
166 int rs6000_altivec_abi;
167
168 /* Nonzero if we want SPE ABI extensions. */
169 int rs6000_spe_abi;
170
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs = 0;
173
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi;
176
177 /* Set to nonzero once AIX common-mode calls have been defined. */
178 static GTY(()) int common_mode_defined;
179
180 /* Save information from a "cmpxx" operation until the branch or scc is
181 emitted. */
182 rtx rs6000_compare_op0, rs6000_compare_op1;
183 int rs6000_compare_fp_p;
184
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 int rs6000_pic_labelno;
188
189 #ifdef USING_ELFOS_H
190 /* Which abi to adhere to */
191 const char *rs6000_abi_name;
192
193 /* Semantics of the small data area */
194 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
195
196 /* Which small data model to use */
197 const char *rs6000_sdata_name = (char *)0;
198
199 /* Counter for labels which are to be placed in .fixup. */
200 int fixuplabelno = 0;
201 #endif
202
203 /* Bit size of immediate TLS offsets and string from which it is decoded. */
204 int rs6000_tls_size = 32;
205 const char *rs6000_tls_size_string;
206
207 /* ABI enumeration available for subtarget to use. */
208 enum rs6000_abi rs6000_current_abi;
209
210 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
211 int dot_symbols;
212
213 /* Debug flags */
214 const char *rs6000_debug_name;
215 int rs6000_debug_stack; /* debug stack applications */
216 int rs6000_debug_arg; /* debug argument handling */
217
218 /* Value is TRUE if register/mode pair is acceptable. */
219 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
220
221 /* Built in types. */
222
223 tree rs6000_builtin_types[RS6000_BTI_MAX];
224 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
225
226 const char *rs6000_traceback_name;
227 static enum {
228 traceback_default = 0,
229 traceback_none,
230 traceback_part,
231 traceback_full
232 } rs6000_traceback;
233
234 /* Flag to say the TOC is initialized */
235 int toc_initialized;
236 char toc_label_name[10];
237
238 static GTY(()) section *read_only_data_section;
239 static GTY(()) section *private_data_section;
240 static GTY(()) section *read_only_private_data_section;
241 static GTY(()) section *sdata2_section;
242 static GTY(()) section *toc_section;
243
244 /* Control alignment for fields within structures. */
245 /* String from -malign-XXXXX. */
246 int rs6000_alignment_flags;
247
248 /* True for any options that were explicitly set. */
249 struct {
250 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
251 bool alignment; /* True if -malign- was used. */
252 bool abi; /* True if -mabi=spe/nospe was used. */
253 bool spe; /* True if -mspe= was used. */
254 bool float_gprs; /* True if -mfloat-gprs= was used. */
255 bool isel; /* True if -misel was used. */
256 bool long_double; /* True if -mlong-double- was used. */
257 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
258 } rs6000_explicit_options;
259
260 struct builtin_description
261 {
262 /* mask is not const because we're going to alter it below. This
263 nonsense will go away when we rewrite the -march infrastructure
264 to give us more target flag bits. */
265 unsigned int mask;
266 const enum insn_code icode;
267 const char *const name;
268 const enum rs6000_builtins code;
269 };
270
271 /* Target cpu costs. */
272
273 struct processor_costs {
274 const int mulsi; /* cost of SImode multiplication. */
275 const int mulsi_const; /* cost of SImode multiplication by constant. */
276 const int mulsi_const9; /* cost of SImode mult by short constant. */
277 const int muldi; /* cost of DImode multiplication. */
278 const int divsi; /* cost of SImode division. */
279 const int divdi; /* cost of DImode division. */
280 const int fp; /* cost of simple SFmode and DFmode insns. */
281 const int dmul; /* cost of DFmode multiplication (and fmadd). */
282 const int sdiv; /* cost of SFmode division (fdivs). */
283 const int ddiv; /* cost of DFmode division (fdiv). */
284 };
285
286 const struct processor_costs *rs6000_cost;
287
288 /* Processor costs (relative to an add) */
289
290 /* Instruction size costs on 32bit processors. */
291 static const
292 struct processor_costs size32_cost = {
293 COSTS_N_INSNS (1), /* mulsi */
294 COSTS_N_INSNS (1), /* mulsi_const */
295 COSTS_N_INSNS (1), /* mulsi_const9 */
296 COSTS_N_INSNS (1), /* muldi */
297 COSTS_N_INSNS (1), /* divsi */
298 COSTS_N_INSNS (1), /* divdi */
299 COSTS_N_INSNS (1), /* fp */
300 COSTS_N_INSNS (1), /* dmul */
301 COSTS_N_INSNS (1), /* sdiv */
302 COSTS_N_INSNS (1), /* ddiv */
303 };
304
305 /* Instruction size costs on 64bit processors. */
306 static const
307 struct processor_costs size64_cost = {
308 COSTS_N_INSNS (1), /* mulsi */
309 COSTS_N_INSNS (1), /* mulsi_const */
310 COSTS_N_INSNS (1), /* mulsi_const9 */
311 COSTS_N_INSNS (1), /* muldi */
312 COSTS_N_INSNS (1), /* divsi */
313 COSTS_N_INSNS (1), /* divdi */
314 COSTS_N_INSNS (1), /* fp */
315 COSTS_N_INSNS (1), /* dmul */
316 COSTS_N_INSNS (1), /* sdiv */
317 COSTS_N_INSNS (1), /* ddiv */
318 };
319
320 /* Instruction costs on RIOS1 processors. */
321 static const
322 struct processor_costs rios1_cost = {
323 COSTS_N_INSNS (5), /* mulsi */
324 COSTS_N_INSNS (4), /* mulsi_const */
325 COSTS_N_INSNS (3), /* mulsi_const9 */
326 COSTS_N_INSNS (5), /* muldi */
327 COSTS_N_INSNS (19), /* divsi */
328 COSTS_N_INSNS (19), /* divdi */
329 COSTS_N_INSNS (2), /* fp */
330 COSTS_N_INSNS (2), /* dmul */
331 COSTS_N_INSNS (19), /* sdiv */
332 COSTS_N_INSNS (19), /* ddiv */
333 };
334
335 /* Instruction costs on RIOS2 processors. */
336 static const
337 struct processor_costs rios2_cost = {
338 COSTS_N_INSNS (2), /* mulsi */
339 COSTS_N_INSNS (2), /* mulsi_const */
340 COSTS_N_INSNS (2), /* mulsi_const9 */
341 COSTS_N_INSNS (2), /* muldi */
342 COSTS_N_INSNS (13), /* divsi */
343 COSTS_N_INSNS (13), /* divdi */
344 COSTS_N_INSNS (2), /* fp */
345 COSTS_N_INSNS (2), /* dmul */
346 COSTS_N_INSNS (17), /* sdiv */
347 COSTS_N_INSNS (17), /* ddiv */
348 };
349
350 /* Instruction costs on RS64A processors. */
351 static const
352 struct processor_costs rs64a_cost = {
353 COSTS_N_INSNS (20), /* mulsi */
354 COSTS_N_INSNS (12), /* mulsi_const */
355 COSTS_N_INSNS (8), /* mulsi_const9 */
356 COSTS_N_INSNS (34), /* muldi */
357 COSTS_N_INSNS (65), /* divsi */
358 COSTS_N_INSNS (67), /* divdi */
359 COSTS_N_INSNS (4), /* fp */
360 COSTS_N_INSNS (4), /* dmul */
361 COSTS_N_INSNS (31), /* sdiv */
362 COSTS_N_INSNS (31), /* ddiv */
363 };
364
365 /* Instruction costs on MPCCORE processors. */
366 static const
367 struct processor_costs mpccore_cost = {
368 COSTS_N_INSNS (2), /* mulsi */
369 COSTS_N_INSNS (2), /* mulsi_const */
370 COSTS_N_INSNS (2), /* mulsi_const9 */
371 COSTS_N_INSNS (2), /* muldi */
372 COSTS_N_INSNS (6), /* divsi */
373 COSTS_N_INSNS (6), /* divdi */
374 COSTS_N_INSNS (4), /* fp */
375 COSTS_N_INSNS (5), /* dmul */
376 COSTS_N_INSNS (10), /* sdiv */
377 COSTS_N_INSNS (17), /* ddiv */
378 };
379
380 /* Instruction costs on PPC403 processors. */
381 static const
382 struct processor_costs ppc403_cost = {
383 COSTS_N_INSNS (4), /* mulsi */
384 COSTS_N_INSNS (4), /* mulsi_const */
385 COSTS_N_INSNS (4), /* mulsi_const9 */
386 COSTS_N_INSNS (4), /* muldi */
387 COSTS_N_INSNS (33), /* divsi */
388 COSTS_N_INSNS (33), /* divdi */
389 COSTS_N_INSNS (11), /* fp */
390 COSTS_N_INSNS (11), /* dmul */
391 COSTS_N_INSNS (11), /* sdiv */
392 COSTS_N_INSNS (11), /* ddiv */
393 };
394
395 /* Instruction costs on PPC405 processors. */
396 static const
397 struct processor_costs ppc405_cost = {
398 COSTS_N_INSNS (5), /* mulsi */
399 COSTS_N_INSNS (4), /* mulsi_const */
400 COSTS_N_INSNS (3), /* mulsi_const9 */
401 COSTS_N_INSNS (5), /* muldi */
402 COSTS_N_INSNS (35), /* divsi */
403 COSTS_N_INSNS (35), /* divdi */
404 COSTS_N_INSNS (11), /* fp */
405 COSTS_N_INSNS (11), /* dmul */
406 COSTS_N_INSNS (11), /* sdiv */
407 COSTS_N_INSNS (11), /* ddiv */
408 };
409
410 /* Instruction costs on PPC440 processors. */
411 static const
412 struct processor_costs ppc440_cost = {
413 COSTS_N_INSNS (3), /* mulsi */
414 COSTS_N_INSNS (2), /* mulsi_const */
415 COSTS_N_INSNS (2), /* mulsi_const9 */
416 COSTS_N_INSNS (3), /* muldi */
417 COSTS_N_INSNS (34), /* divsi */
418 COSTS_N_INSNS (34), /* divdi */
419 COSTS_N_INSNS (5), /* fp */
420 COSTS_N_INSNS (5), /* dmul */
421 COSTS_N_INSNS (19), /* sdiv */
422 COSTS_N_INSNS (33), /* ddiv */
423 };
424
425 /* Instruction costs on PPC601 processors. */
426 static const
427 struct processor_costs ppc601_cost = {
428 COSTS_N_INSNS (5), /* mulsi */
429 COSTS_N_INSNS (5), /* mulsi_const */
430 COSTS_N_INSNS (5), /* mulsi_const9 */
431 COSTS_N_INSNS (5), /* muldi */
432 COSTS_N_INSNS (36), /* divsi */
433 COSTS_N_INSNS (36), /* divdi */
434 COSTS_N_INSNS (4), /* fp */
435 COSTS_N_INSNS (5), /* dmul */
436 COSTS_N_INSNS (17), /* sdiv */
437 COSTS_N_INSNS (31), /* ddiv */
438 };
439
440 /* Instruction costs on PPC603 processors. */
441 static const
442 struct processor_costs ppc603_cost = {
443 COSTS_N_INSNS (5), /* mulsi */
444 COSTS_N_INSNS (3), /* mulsi_const */
445 COSTS_N_INSNS (2), /* mulsi_const9 */
446 COSTS_N_INSNS (5), /* muldi */
447 COSTS_N_INSNS (37), /* divsi */
448 COSTS_N_INSNS (37), /* divdi */
449 COSTS_N_INSNS (3), /* fp */
450 COSTS_N_INSNS (4), /* dmul */
451 COSTS_N_INSNS (18), /* sdiv */
452 COSTS_N_INSNS (33), /* ddiv */
453 };
454
455 /* Instruction costs on PPC604 processors. */
456 static const
457 struct processor_costs ppc604_cost = {
458 COSTS_N_INSNS (4), /* mulsi */
459 COSTS_N_INSNS (4), /* mulsi_const */
460 COSTS_N_INSNS (4), /* mulsi_const9 */
461 COSTS_N_INSNS (4), /* muldi */
462 COSTS_N_INSNS (20), /* divsi */
463 COSTS_N_INSNS (20), /* divdi */
464 COSTS_N_INSNS (3), /* fp */
465 COSTS_N_INSNS (3), /* dmul */
466 COSTS_N_INSNS (18), /* sdiv */
467 COSTS_N_INSNS (32), /* ddiv */
468 };
469
470 /* Instruction costs on PPC604e processors. */
471 static const
472 struct processor_costs ppc604e_cost = {
473 COSTS_N_INSNS (2), /* mulsi */
474 COSTS_N_INSNS (2), /* mulsi_const */
475 COSTS_N_INSNS (2), /* mulsi_const9 */
476 COSTS_N_INSNS (2), /* muldi */
477 COSTS_N_INSNS (20), /* divsi */
478 COSTS_N_INSNS (20), /* divdi */
479 COSTS_N_INSNS (3), /* fp */
480 COSTS_N_INSNS (3), /* dmul */
481 COSTS_N_INSNS (18), /* sdiv */
482 COSTS_N_INSNS (32), /* ddiv */
483 };
484
485 /* Instruction costs on PPC620 processors. */
486 static const
487 struct processor_costs ppc620_cost = {
488 COSTS_N_INSNS (5), /* mulsi */
489 COSTS_N_INSNS (4), /* mulsi_const */
490 COSTS_N_INSNS (3), /* mulsi_const9 */
491 COSTS_N_INSNS (7), /* muldi */
492 COSTS_N_INSNS (21), /* divsi */
493 COSTS_N_INSNS (37), /* divdi */
494 COSTS_N_INSNS (3), /* fp */
495 COSTS_N_INSNS (3), /* dmul */
496 COSTS_N_INSNS (18), /* sdiv */
497 COSTS_N_INSNS (32), /* ddiv */
498 };
499
500 /* Instruction costs on PPC630 processors. */
501 static const
502 struct processor_costs ppc630_cost = {
503 COSTS_N_INSNS (5), /* mulsi */
504 COSTS_N_INSNS (4), /* mulsi_const */
505 COSTS_N_INSNS (3), /* mulsi_const9 */
506 COSTS_N_INSNS (7), /* muldi */
507 COSTS_N_INSNS (21), /* divsi */
508 COSTS_N_INSNS (37), /* divdi */
509 COSTS_N_INSNS (3), /* fp */
510 COSTS_N_INSNS (3), /* dmul */
511 COSTS_N_INSNS (17), /* sdiv */
512 COSTS_N_INSNS (21), /* ddiv */
513 };
514
515 /* Instruction costs on PPC750 and PPC7400 processors. */
516 static const
517 struct processor_costs ppc750_cost = {
518 COSTS_N_INSNS (5), /* mulsi */
519 COSTS_N_INSNS (3), /* mulsi_const */
520 COSTS_N_INSNS (2), /* mulsi_const9 */
521 COSTS_N_INSNS (5), /* muldi */
522 COSTS_N_INSNS (17), /* divsi */
523 COSTS_N_INSNS (17), /* divdi */
524 COSTS_N_INSNS (3), /* fp */
525 COSTS_N_INSNS (3), /* dmul */
526 COSTS_N_INSNS (17), /* sdiv */
527 COSTS_N_INSNS (31), /* ddiv */
528 };
529
530 /* Instruction costs on PPC7450 processors. */
531 static const
532 struct processor_costs ppc7450_cost = {
533 COSTS_N_INSNS (4), /* mulsi */
534 COSTS_N_INSNS (3), /* mulsi_const */
535 COSTS_N_INSNS (3), /* mulsi_const9 */
536 COSTS_N_INSNS (4), /* muldi */
537 COSTS_N_INSNS (23), /* divsi */
538 COSTS_N_INSNS (23), /* divdi */
539 COSTS_N_INSNS (5), /* fp */
540 COSTS_N_INSNS (5), /* dmul */
541 COSTS_N_INSNS (21), /* sdiv */
542 COSTS_N_INSNS (35), /* ddiv */
543 };
544
545 /* Instruction costs on PPC8540 processors. */
546 static const
547 struct processor_costs ppc8540_cost = {
548 COSTS_N_INSNS (4), /* mulsi */
549 COSTS_N_INSNS (4), /* mulsi_const */
550 COSTS_N_INSNS (4), /* mulsi_const9 */
551 COSTS_N_INSNS (4), /* muldi */
552 COSTS_N_INSNS (19), /* divsi */
553 COSTS_N_INSNS (19), /* divdi */
554 COSTS_N_INSNS (4), /* fp */
555 COSTS_N_INSNS (4), /* dmul */
556 COSTS_N_INSNS (29), /* sdiv */
557 COSTS_N_INSNS (29), /* ddiv */
558 };
559
560 /* Instruction costs on POWER4 and POWER5 processors. */
561 static const
562 struct processor_costs power4_cost = {
563 COSTS_N_INSNS (3), /* mulsi */
564 COSTS_N_INSNS (2), /* mulsi_const */
565 COSTS_N_INSNS (2), /* mulsi_const9 */
566 COSTS_N_INSNS (4), /* muldi */
567 COSTS_N_INSNS (18), /* divsi */
568 COSTS_N_INSNS (34), /* divdi */
569 COSTS_N_INSNS (3), /* fp */
570 COSTS_N_INSNS (3), /* dmul */
571 COSTS_N_INSNS (17), /* sdiv */
572 COSTS_N_INSNS (17), /* ddiv */
573 };
574
575
576 static bool rs6000_function_ok_for_sibcall (tree, tree);
577 static const char *rs6000_invalid_within_doloop (rtx);
578 static rtx rs6000_generate_compare (enum rtx_code);
579 static void rs6000_maybe_dead (rtx);
580 static void rs6000_emit_stack_tie (void);
581 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
582 static rtx spe_synthesize_frame_save (rtx);
583 static bool spe_func_has_64bit_regs_p (void);
584 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
585 int, HOST_WIDE_INT);
586 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
587 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
588 static unsigned rs6000_hash_constant (rtx);
589 static unsigned toc_hash_function (const void *);
590 static int toc_hash_eq (const void *, const void *);
591 static int constant_pool_expr_1 (rtx, int *, int *);
592 static bool constant_pool_expr_p (rtx);
593 static bool legitimate_small_data_p (enum machine_mode, rtx);
594 static bool legitimate_indexed_address_p (rtx, int);
595 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
596 static struct machine_function * rs6000_init_machine_status (void);
597 static bool rs6000_assemble_integer (rtx, unsigned int, int);
598 static bool no_global_regs_above (int);
599 #ifdef HAVE_GAS_HIDDEN
600 static void rs6000_assemble_visibility (tree, int);
601 #endif
602 static int rs6000_ra_ever_killed (void);
603 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
604 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
605 static bool rs6000_ms_bitfield_layout_p (tree);
606 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
607 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
608 static const char *rs6000_mangle_fundamental_type (tree);
609 extern const struct attribute_spec rs6000_attribute_table[];
610 static void rs6000_set_default_type_attributes (tree);
611 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
612 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
613 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
614 tree);
615 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
616 static bool rs6000_return_in_memory (tree, tree);
617 static void rs6000_file_start (void);
618 #if TARGET_ELF
619 static int rs6000_elf_reloc_rw_mask (void);
620 static void rs6000_elf_asm_out_constructor (rtx, int);
621 static void rs6000_elf_asm_out_destructor (rtx, int);
622 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
623 static void rs6000_elf_asm_init_sections (void);
624 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
625 unsigned HOST_WIDE_INT);
626 static void rs6000_elf_encode_section_info (tree, rtx, int)
627 ATTRIBUTE_UNUSED;
628 #endif
629 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
630 #if TARGET_XCOFF
631 static void rs6000_xcoff_asm_output_anchor (rtx);
632 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
633 static void rs6000_xcoff_asm_init_sections (void);
634 static int rs6000_xcoff_reloc_rw_mask (void);
635 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
636 static section *rs6000_xcoff_select_section (tree, int,
637 unsigned HOST_WIDE_INT);
638 static void rs6000_xcoff_unique_section (tree, int);
639 static section *rs6000_xcoff_select_rtx_section
640 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
641 static const char * rs6000_xcoff_strip_name_encoding (const char *);
642 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
643 static void rs6000_xcoff_file_start (void);
644 static void rs6000_xcoff_file_end (void);
645 #endif
646 static int rs6000_variable_issue (FILE *, int, rtx, int);
647 static bool rs6000_rtx_costs (rtx, int, int, int *);
648 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
649 static bool is_microcoded_insn (rtx);
650 static int is_dispatch_slot_restricted (rtx);
651 static bool is_cracked_insn (rtx);
652 static bool is_branch_slot_insn (rtx);
653 static int rs6000_adjust_priority (rtx, int);
654 static int rs6000_issue_rate (void);
655 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
656 static rtx get_next_active_insn (rtx, rtx);
657 static bool insn_terminates_group_p (rtx , enum group_termination);
658 static bool is_costly_group (rtx *, rtx);
659 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
660 static int redefine_groups (FILE *, int, rtx, rtx);
661 static int pad_groups (FILE *, int, rtx, rtx);
662 static void rs6000_sched_finish (FILE *, int);
663 static int rs6000_use_sched_lookahead (void);
664 static tree rs6000_builtin_mask_for_load (void);
665
666 static void def_builtin (int, const char *, tree, int);
667 static void rs6000_init_builtins (void);
668 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
669 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
670 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
671 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
672 static void altivec_init_builtins (void);
673 static void rs6000_common_init_builtins (void);
674 static void rs6000_init_libfuncs (void);
675
676 static void enable_mask_for_builtins (struct builtin_description *, int,
677 enum rs6000_builtins,
678 enum rs6000_builtins);
679 static tree build_opaque_vector_type (tree, int);
680 static void spe_init_builtins (void);
681 static rtx spe_expand_builtin (tree, rtx, bool *);
682 static rtx spe_expand_stv_builtin (enum insn_code, tree);
683 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
684 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
685 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
686 static rs6000_stack_t *rs6000_stack_info (void);
687 static void debug_stack_info (rs6000_stack_t *);
688
689 static rtx altivec_expand_builtin (tree, rtx, bool *);
690 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
691 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
692 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
693 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
694 static rtx altivec_expand_predicate_builtin (enum insn_code,
695 const char *, tree, rtx);
696 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
697 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
698 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
699 static rtx altivec_expand_vec_set_builtin (tree);
700 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
701 static int get_element_number (tree, tree);
702 static bool rs6000_handle_option (size_t, const char *, int);
703 static void rs6000_parse_tls_size_option (void);
704 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
705 static int first_altivec_reg_to_save (void);
706 static unsigned int compute_vrsave_mask (void);
707 static void compute_save_world_info (rs6000_stack_t *info_ptr);
708 static void is_altivec_return_reg (rtx, void *);
709 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
710 int easy_vector_constant (rtx, enum machine_mode);
711 static bool rs6000_is_opaque_type (tree);
712 static rtx rs6000_dwarf_register_span (rtx);
713 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
714 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
715 static rtx rs6000_tls_get_addr (void);
716 static rtx rs6000_got_sym (void);
717 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
718 static const char *rs6000_get_some_local_dynamic_name (void);
719 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
720 static rtx rs6000_complex_function_value (enum machine_mode);
721 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
722 enum machine_mode, tree);
723 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
724 HOST_WIDE_INT);
725 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
726 tree, HOST_WIDE_INT);
727 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
728 HOST_WIDE_INT,
729 rtx[], int *);
730 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
731 tree, HOST_WIDE_INT,
732 rtx[], int *);
733 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
734 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
735 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
736 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
737 enum machine_mode, tree,
738 int *, int);
739 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
740 tree, bool);
741 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
742 tree, bool);
743 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
744 #if TARGET_MACHO
745 static void macho_branch_islands (void);
746 static int no_previous_def (tree function_name);
747 static tree get_prev_label (tree function_name);
748 static void rs6000_darwin_file_start (void);
749 #endif
750
751 static tree rs6000_build_builtin_va_list (void);
752 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
753 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
754 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
755 static bool rs6000_vector_mode_supported_p (enum machine_mode);
756 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
757 enum machine_mode);
758 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
759 enum machine_mode);
760 static int get_vsel_insn (enum machine_mode);
761 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
762 static tree rs6000_stack_protect_fail (void);
763
764 const int INSN_NOT_AVAILABLE = -1;
765 static enum machine_mode rs6000_eh_return_filter_mode (void);
766
767 /* Hash table stuff for keeping track of TOC entries. */
768
769 struct toc_hash_struct GTY(())
770 {
771 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
772 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
773 rtx key;
774 enum machine_mode key_mode;
775 int labelno;
776 };
777
778 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
779
780 /* Default register names. */
781 char rs6000_reg_names[][8] =
782 {
783 "0", "1", "2", "3", "4", "5", "6", "7",
784 "8", "9", "10", "11", "12", "13", "14", "15",
785 "16", "17", "18", "19", "20", "21", "22", "23",
786 "24", "25", "26", "27", "28", "29", "30", "31",
787 "0", "1", "2", "3", "4", "5", "6", "7",
788 "8", "9", "10", "11", "12", "13", "14", "15",
789 "16", "17", "18", "19", "20", "21", "22", "23",
790 "24", "25", "26", "27", "28", "29", "30", "31",
791 "mq", "lr", "ctr","ap",
792 "0", "1", "2", "3", "4", "5", "6", "7",
793 "xer",
794 /* AltiVec registers. */
795 "0", "1", "2", "3", "4", "5", "6", "7",
796 "8", "9", "10", "11", "12", "13", "14", "15",
797 "16", "17", "18", "19", "20", "21", "22", "23",
798 "24", "25", "26", "27", "28", "29", "30", "31",
799 "vrsave", "vscr",
800 /* SPE registers. */
801 "spe_acc", "spefscr",
802 /* Soft frame pointer. */
803 "sfp"
804 };
805
806 #ifdef TARGET_REGNAMES
807 static const char alt_reg_names[][8] =
808 {
809 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
810 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
811 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
812 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
813 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
814 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
815 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
816 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
817 "mq", "lr", "ctr", "ap",
818 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
819 "xer",
820 /* AltiVec registers. */
821 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
822 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
823 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
824 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
825 "vrsave", "vscr",
826 /* SPE registers. */
827 "spe_acc", "spefscr",
828 /* Soft frame pointer. */
829 "sfp"
830 };
831 #endif
832
833 #ifndef MASK_STRICT_ALIGN
834 #define MASK_STRICT_ALIGN 0
835 #endif
836 #ifndef TARGET_PROFILE_KERNEL
837 #define TARGET_PROFILE_KERNEL 0
838 #endif
839
840 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
841 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
842
843 /* Initialize the GCC target structure. */
844 #undef TARGET_ATTRIBUTE_TABLE
845 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
846 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
847 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
848
849 #undef TARGET_ASM_ALIGNED_DI_OP
850 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
851
852 /* Default unaligned ops are only provided for ELF. Find the ops needed
853 for non-ELF systems. */
854 #ifndef OBJECT_FORMAT_ELF
855 #if TARGET_XCOFF
856 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
857 64-bit targets. */
858 #undef TARGET_ASM_UNALIGNED_HI_OP
859 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
860 #undef TARGET_ASM_UNALIGNED_SI_OP
861 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
862 #undef TARGET_ASM_UNALIGNED_DI_OP
863 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
864 #else
865 /* For Darwin. */
866 #undef TARGET_ASM_UNALIGNED_HI_OP
867 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
868 #undef TARGET_ASM_UNALIGNED_SI_OP
869 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
870 #undef TARGET_ASM_UNALIGNED_DI_OP
871 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
872 #undef TARGET_ASM_ALIGNED_DI_OP
873 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
874 #endif
875 #endif
876
877 /* This hook deals with fixups for relocatable code and DI-mode objects
878 in 64-bit code. */
879 #undef TARGET_ASM_INTEGER
880 #define TARGET_ASM_INTEGER rs6000_assemble_integer
881
882 #ifdef HAVE_GAS_HIDDEN
883 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
884 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
885 #endif
886
887 #undef TARGET_HAVE_TLS
888 #define TARGET_HAVE_TLS HAVE_AS_TLS
889
890 #undef TARGET_CANNOT_FORCE_CONST_MEM
891 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
892
893 #undef TARGET_ASM_FUNCTION_PROLOGUE
894 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
895 #undef TARGET_ASM_FUNCTION_EPILOGUE
896 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
897
898 #undef TARGET_SCHED_VARIABLE_ISSUE
899 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
900
901 #undef TARGET_SCHED_ISSUE_RATE
902 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
903 #undef TARGET_SCHED_ADJUST_COST
904 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
905 #undef TARGET_SCHED_ADJUST_PRIORITY
906 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
907 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
908 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
909 #undef TARGET_SCHED_FINISH
910 #define TARGET_SCHED_FINISH rs6000_sched_finish
911
912 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
913 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
914
915 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
916 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
917
918 #undef TARGET_INIT_BUILTINS
919 #define TARGET_INIT_BUILTINS rs6000_init_builtins
920
921 #undef TARGET_EXPAND_BUILTIN
922 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
923
924 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
925 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
926
927 #undef TARGET_INIT_LIBFUNCS
928 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
929
930 #if TARGET_MACHO
931 #undef TARGET_BINDS_LOCAL_P
932 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
933 #endif
934
935 #undef TARGET_MS_BITFIELD_LAYOUT_P
936 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
937
938 #undef TARGET_ASM_OUTPUT_MI_THUNK
939 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
940
941 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
942 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
943
944 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
945 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
946
947 #undef TARGET_INVALID_WITHIN_DOLOOP
948 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
949
950 #undef TARGET_RTX_COSTS
951 #define TARGET_RTX_COSTS rs6000_rtx_costs
952 #undef TARGET_ADDRESS_COST
953 #define TARGET_ADDRESS_COST hook_int_rtx_0
954
955 #undef TARGET_VECTOR_OPAQUE_P
956 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
957
958 #undef TARGET_DWARF_REGISTER_SPAN
959 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
960
961 /* On rs6000, function arguments are promoted, as are function return
962 values. */
963 #undef TARGET_PROMOTE_FUNCTION_ARGS
964 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
965 #undef TARGET_PROMOTE_FUNCTION_RETURN
966 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
967
968 #undef TARGET_RETURN_IN_MEMORY
969 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
970
971 #undef TARGET_SETUP_INCOMING_VARARGS
972 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
973
974 /* Always strict argument naming on rs6000. */
975 #undef TARGET_STRICT_ARGUMENT_NAMING
976 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
977 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
978 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
979 #undef TARGET_SPLIT_COMPLEX_ARG
980 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
981 #undef TARGET_MUST_PASS_IN_STACK
982 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
983 #undef TARGET_PASS_BY_REFERENCE
984 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
985 #undef TARGET_ARG_PARTIAL_BYTES
986 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
987
988 #undef TARGET_BUILD_BUILTIN_VA_LIST
989 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
990
991 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
992 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
993
994 #undef TARGET_EH_RETURN_FILTER_MODE
995 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
996
997 #undef TARGET_SCALAR_MODE_SUPPORTED_P
998 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
999
1000 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1001 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1002
1003 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1004 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1005
1006 #undef TARGET_HANDLE_OPTION
1007 #define TARGET_HANDLE_OPTION rs6000_handle_option
1008
1009 #undef TARGET_DEFAULT_TARGET_FLAGS
1010 #define TARGET_DEFAULT_TARGET_FLAGS \
1011 (TARGET_DEFAULT)
1012
1013 #undef TARGET_STACK_PROTECT_FAIL
1014 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1015
1016 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1017 The PowerPC architecture requires only weak consistency among
1018 processors--that is, memory accesses between processors need not be
1019 sequentially consistent and memory accesses among processors can occur
1020 in any order. The ability to order memory accesses weakly provides
1021 opportunities for more efficient use of the system bus. Unless a
1022 dependency exists, the 604e allows read operations to precede store
1023 operations. */
1024 #undef TARGET_RELAXED_ORDERING
1025 #define TARGET_RELAXED_ORDERING true
1026
1027 #ifdef HAVE_AS_TLS
1028 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1029 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1030 #endif
1031
1032 /* Use a 32-bit anchor range. This leads to sequences like:
1033
1034 addis tmp,anchor,high
1035 add dest,tmp,low
1036
1037 where tmp itself acts as an anchor, and can be shared between
1038 accesses to the same 64k page. */
1039 #undef TARGET_MIN_ANCHOR_OFFSET
1040 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1041 #undef TARGET_MAX_ANCHOR_OFFSET
1042 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1043 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1044 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1045
1046 struct gcc_target targetm = TARGET_INITIALIZER;
1047
1048
1049 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1050 MODE. */
1051 static int
rs6000_hard_regno_mode_ok(int regno,enum machine_mode mode)1052 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1053 {
1054 /* The GPRs can hold any mode, but values bigger than one register
1055 cannot go past R31. */
1056 if (INT_REGNO_P (regno))
1057 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1058
1059 /* The float registers can only hold floating modes and DImode.
1060 This also excludes decimal float modes. */
1061 if (FP_REGNO_P (regno))
1062 return
1063 (SCALAR_FLOAT_MODE_P (mode)
1064 && !DECIMAL_FLOAT_MODE_P (mode)
1065 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1066 || (GET_MODE_CLASS (mode) == MODE_INT
1067 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1068
1069 /* The CR register can only hold CC modes. */
1070 if (CR_REGNO_P (regno))
1071 return GET_MODE_CLASS (mode) == MODE_CC;
1072
1073 if (XER_REGNO_P (regno))
1074 return mode == PSImode;
1075
1076 /* AltiVec only in AldyVec registers. */
1077 if (ALTIVEC_REGNO_P (regno))
1078 return ALTIVEC_VECTOR_MODE (mode);
1079
1080 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1081 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1082 return 1;
1083
1084 /* We cannot put TImode anywhere except general register and it must be
1085 able to fit within the register set. */
1086
1087 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1088 }
1089
1090 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1091 static void
rs6000_init_hard_regno_mode_ok(void)1092 rs6000_init_hard_regno_mode_ok (void)
1093 {
1094 int r, m;
1095
1096 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1097 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1098 if (rs6000_hard_regno_mode_ok (r, m))
1099 rs6000_hard_regno_mode_ok_p[m][r] = true;
1100 }
1101
1102 /* If not otherwise specified by a target, make 'long double' equivalent to
1103 'double'. */
1104
1105 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1106 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1107 #endif
1108
1109 /* Override command line options. Mostly we process the processor
1110 type and sometimes adjust other TARGET_ options. */
1111
1112 void
rs6000_override_options(const char * default_cpu)1113 rs6000_override_options (const char *default_cpu)
1114 {
1115 size_t i, j;
1116 struct rs6000_cpu_select *ptr;
1117 int set_masks;
1118
1119 /* Simplifications for entries below. */
1120
1121 enum {
1122 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1123 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1124 };
1125
1126 /* This table occasionally claims that a processor does not support
1127 a particular feature even though it does, but the feature is slower
1128 than the alternative. Thus, it shouldn't be relied on as a
1129 complete description of the processor's support.
1130
1131 Please keep this list in order, and don't forget to update the
1132 documentation in invoke.texi when adding a new processor or
1133 flag. */
1134 static struct ptt
1135 {
1136 const char *const name; /* Canonical processor name. */
1137 const enum processor_type processor; /* Processor type enum value. */
1138 const int target_enable; /* Target flags to enable. */
1139 } const processor_target_table[]
1140 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1141 {"403", PROCESSOR_PPC403,
1142 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1143 {"405", PROCESSOR_PPC405,
1144 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1145 {"405fp", PROCESSOR_PPC405,
1146 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1147 {"440", PROCESSOR_PPC440,
1148 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1149 {"440fp", PROCESSOR_PPC440,
1150 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1151 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1152 {"601", PROCESSOR_PPC601,
1153 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1154 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1155 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1156 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1157 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1158 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1159 {"620", PROCESSOR_PPC620,
1160 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1161 {"630", PROCESSOR_PPC630,
1162 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1163 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1164 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1165 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1166 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1167 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1168 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1169 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1170 {"8540", PROCESSOR_PPC8540,
1171 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
1172 /* 8548 has a dummy entry for now. */
1173 {"8548", PROCESSOR_PPC8540,
1174 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
1175 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1176 {"970", PROCESSOR_POWER4,
1177 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1178 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1179 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1180 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1181 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1182 {"G5", PROCESSOR_POWER4,
1183 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1184 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1185 {"power2", PROCESSOR_POWER,
1186 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1187 {"power3", PROCESSOR_PPC630,
1188 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1189 {"power4", PROCESSOR_POWER4,
1190 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1191 {"power5", PROCESSOR_POWER5,
1192 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1193 | MASK_MFCRF | MASK_POPCNTB},
1194 {"power5+", PROCESSOR_POWER5,
1195 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1196 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1197 {"power6", PROCESSOR_POWER5,
1198 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1199 | MASK_FPRND},
1200 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1201 {"powerpc64", PROCESSOR_POWERPC64,
1202 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1203 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1204 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1205 {"rios2", PROCESSOR_RIOS2,
1206 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1207 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1208 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1209 {"rs64", PROCESSOR_RS64A,
1210 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1211 };
1212
1213 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1214
1215 /* Some OSs don't support saving the high part of 64-bit registers on
1216 context switch. Other OSs don't support saving Altivec registers.
1217 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1218 settings; if the user wants either, the user must explicitly specify
1219 them and we won't interfere with the user's specification. */
1220
1221 enum {
1222 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1223 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1224 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1225 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1226 | MASK_DLMZB)
1227 };
1228
1229 rs6000_init_hard_regno_mode_ok ();
1230
1231 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1232 #ifdef OS_MISSING_POWERPC64
1233 if (OS_MISSING_POWERPC64)
1234 set_masks &= ~MASK_POWERPC64;
1235 #endif
1236 #ifdef OS_MISSING_ALTIVEC
1237 if (OS_MISSING_ALTIVEC)
1238 set_masks &= ~MASK_ALTIVEC;
1239 #endif
1240
1241 /* Don't override by the processor default if given explicitly. */
1242 set_masks &= ~target_flags_explicit;
1243
1244 /* Identify the processor type. */
1245 rs6000_select[0].string = default_cpu;
1246 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1247
1248 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1249 {
1250 ptr = &rs6000_select[i];
1251 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1252 {
1253 for (j = 0; j < ptt_size; j++)
1254 if (! strcmp (ptr->string, processor_target_table[j].name))
1255 {
1256 if (ptr->set_tune_p)
1257 rs6000_cpu = processor_target_table[j].processor;
1258
1259 if (ptr->set_arch_p)
1260 {
1261 target_flags &= ~set_masks;
1262 target_flags |= (processor_target_table[j].target_enable
1263 & set_masks);
1264 }
1265 break;
1266 }
1267
1268 if (j == ptt_size)
1269 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1270 }
1271 }
1272
1273 if (TARGET_E500)
1274 rs6000_isel = 1;
1275
1276 /* If we are optimizing big endian systems for space, use the load/store
1277 multiple and string instructions. */
1278 if (BYTES_BIG_ENDIAN && optimize_size)
1279 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1280
1281 /* Don't allow -mmultiple or -mstring on little endian systems
1282 unless the cpu is a 750, because the hardware doesn't support the
1283 instructions used in little endian mode, and causes an alignment
1284 trap. The 750 does not cause an alignment trap (except when the
1285 target is unaligned). */
1286
1287 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1288 {
1289 if (TARGET_MULTIPLE)
1290 {
1291 target_flags &= ~MASK_MULTIPLE;
1292 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1293 warning (0, "-mmultiple is not supported on little endian systems");
1294 }
1295
1296 if (TARGET_STRING)
1297 {
1298 target_flags &= ~MASK_STRING;
1299 if ((target_flags_explicit & MASK_STRING) != 0)
1300 warning (0, "-mstring is not supported on little endian systems");
1301 }
1302 }
1303
1304 /* Set debug flags */
1305 if (rs6000_debug_name)
1306 {
1307 if (! strcmp (rs6000_debug_name, "all"))
1308 rs6000_debug_stack = rs6000_debug_arg = 1;
1309 else if (! strcmp (rs6000_debug_name, "stack"))
1310 rs6000_debug_stack = 1;
1311 else if (! strcmp (rs6000_debug_name, "arg"))
1312 rs6000_debug_arg = 1;
1313 else
1314 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1315 }
1316
1317 if (rs6000_traceback_name)
1318 {
1319 if (! strncmp (rs6000_traceback_name, "full", 4))
1320 rs6000_traceback = traceback_full;
1321 else if (! strncmp (rs6000_traceback_name, "part", 4))
1322 rs6000_traceback = traceback_part;
1323 else if (! strncmp (rs6000_traceback_name, "no", 2))
1324 rs6000_traceback = traceback_none;
1325 else
1326 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1327 rs6000_traceback_name);
1328 }
1329
1330 if (!rs6000_explicit_options.long_double)
1331 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1332
1333 #ifndef POWERPC_LINUX
1334 if (!rs6000_explicit_options.ieee)
1335 rs6000_ieeequad = 1;
1336 #endif
1337
1338 /* Set Altivec ABI as default for powerpc64 linux. */
1339 if (TARGET_ELF && TARGET_64BIT)
1340 {
1341 rs6000_altivec_abi = 1;
1342 TARGET_ALTIVEC_VRSAVE = 1;
1343 }
1344
1345 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1346 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1347 {
1348 rs6000_darwin64_abi = 1;
1349 #if TARGET_MACHO
1350 darwin_one_byte_bool = 1;
1351 #endif
1352 /* Default to natural alignment, for better performance. */
1353 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1354 }
1355
1356 /* Place FP constants in the constant pool instead of TOC
1357 if section anchors enabled. */
1358 if (flag_section_anchors)
1359 TARGET_NO_FP_IN_TOC = 1;
1360
1361 /* Handle -mtls-size option. */
1362 rs6000_parse_tls_size_option ();
1363
1364 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1365 SUBTARGET_OVERRIDE_OPTIONS;
1366 #endif
1367 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1368 SUBSUBTARGET_OVERRIDE_OPTIONS;
1369 #endif
1370 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1371 SUB3TARGET_OVERRIDE_OPTIONS;
1372 #endif
1373
1374 if (TARGET_E500)
1375 {
1376 if (TARGET_ALTIVEC)
1377 error ("AltiVec and E500 instructions cannot coexist");
1378
1379 /* The e500 does not have string instructions, and we set
1380 MASK_STRING above when optimizing for size. */
1381 if ((target_flags & MASK_STRING) != 0)
1382 target_flags = target_flags & ~MASK_STRING;
1383 }
1384 else if (rs6000_select[1].string != NULL)
1385 {
1386 /* For the powerpc-eabispe configuration, we set all these by
1387 default, so let's unset them if we manually set another
1388 CPU that is not the E500. */
1389 if (!rs6000_explicit_options.abi)
1390 rs6000_spe_abi = 0;
1391 if (!rs6000_explicit_options.spe)
1392 rs6000_spe = 0;
1393 if (!rs6000_explicit_options.float_gprs)
1394 rs6000_float_gprs = 0;
1395 if (!rs6000_explicit_options.isel)
1396 rs6000_isel = 0;
1397 if (!rs6000_explicit_options.long_double)
1398 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1399 }
1400
1401 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1402 && rs6000_cpu != PROCESSOR_POWER5);
1403 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1404 || rs6000_cpu == PROCESSOR_POWER5);
1405
1406 rs6000_sched_restricted_insns_priority
1407 = (rs6000_sched_groups ? 1 : 0);
1408
1409 /* Handle -msched-costly-dep option. */
1410 rs6000_sched_costly_dep
1411 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1412
1413 if (rs6000_sched_costly_dep_str)
1414 {
1415 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1416 rs6000_sched_costly_dep = no_dep_costly;
1417 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1418 rs6000_sched_costly_dep = all_deps_costly;
1419 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1420 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1421 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1422 rs6000_sched_costly_dep = store_to_load_dep_costly;
1423 else
1424 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1425 }
1426
1427 /* Handle -minsert-sched-nops option. */
1428 rs6000_sched_insert_nops
1429 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1430
1431 if (rs6000_sched_insert_nops_str)
1432 {
1433 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1434 rs6000_sched_insert_nops = sched_finish_none;
1435 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1436 rs6000_sched_insert_nops = sched_finish_pad_groups;
1437 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1438 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1439 else
1440 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1441 }
1442
1443 #ifdef TARGET_REGNAMES
1444 /* If the user desires alternate register names, copy in the
1445 alternate names now. */
1446 if (TARGET_REGNAMES)
1447 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1448 #endif
1449
1450 /* Set aix_struct_return last, after the ABI is determined.
1451 If -maix-struct-return or -msvr4-struct-return was explicitly
1452 used, don't override with the ABI default. */
1453 if (!rs6000_explicit_options.aix_struct_ret)
1454 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1455
1456 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1457 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1458
1459 if (TARGET_TOC)
1460 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1461
1462 /* We can only guarantee the availability of DI pseudo-ops when
1463 assembling for 64-bit targets. */
1464 if (!TARGET_64BIT)
1465 {
1466 targetm.asm_out.aligned_op.di = NULL;
1467 targetm.asm_out.unaligned_op.di = NULL;
1468 }
1469
1470 /* Set branch target alignment, if not optimizing for size. */
1471 if (!optimize_size)
1472 {
1473 if (rs6000_sched_groups)
1474 {
1475 if (align_functions <= 0)
1476 align_functions = 16;
1477 if (align_jumps <= 0)
1478 align_jumps = 16;
1479 if (align_loops <= 0)
1480 align_loops = 16;
1481 }
1482 if (align_jumps_max_skip <= 0)
1483 align_jumps_max_skip = 15;
1484 if (align_loops_max_skip <= 0)
1485 align_loops_max_skip = 15;
1486 }
1487
1488 /* Arrange to save and restore machine status around nested functions. */
1489 init_machine_status = rs6000_init_machine_status;
1490
1491 /* We should always be splitting complex arguments, but we can't break
1492 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1493 if (DEFAULT_ABI != ABI_AIX)
1494 targetm.calls.split_complex_arg = NULL;
1495
1496 /* Initialize rs6000_cost with the appropriate target costs. */
1497 if (optimize_size)
1498 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1499 else
1500 switch (rs6000_cpu)
1501 {
1502 case PROCESSOR_RIOS1:
1503 rs6000_cost = &rios1_cost;
1504 break;
1505
1506 case PROCESSOR_RIOS2:
1507 rs6000_cost = &rios2_cost;
1508 break;
1509
1510 case PROCESSOR_RS64A:
1511 rs6000_cost = &rs64a_cost;
1512 break;
1513
1514 case PROCESSOR_MPCCORE:
1515 rs6000_cost = &mpccore_cost;
1516 break;
1517
1518 case PROCESSOR_PPC403:
1519 rs6000_cost = &ppc403_cost;
1520 break;
1521
1522 case PROCESSOR_PPC405:
1523 rs6000_cost = &ppc405_cost;
1524 break;
1525
1526 case PROCESSOR_PPC440:
1527 rs6000_cost = &ppc440_cost;
1528 break;
1529
1530 case PROCESSOR_PPC601:
1531 rs6000_cost = &ppc601_cost;
1532 break;
1533
1534 case PROCESSOR_PPC603:
1535 rs6000_cost = &ppc603_cost;
1536 break;
1537
1538 case PROCESSOR_PPC604:
1539 rs6000_cost = &ppc604_cost;
1540 break;
1541
1542 case PROCESSOR_PPC604e:
1543 rs6000_cost = &ppc604e_cost;
1544 break;
1545
1546 case PROCESSOR_PPC620:
1547 rs6000_cost = &ppc620_cost;
1548 break;
1549
1550 case PROCESSOR_PPC630:
1551 rs6000_cost = &ppc630_cost;
1552 break;
1553
1554 case PROCESSOR_PPC750:
1555 case PROCESSOR_PPC7400:
1556 rs6000_cost = &ppc750_cost;
1557 break;
1558
1559 case PROCESSOR_PPC7450:
1560 rs6000_cost = &ppc7450_cost;
1561 break;
1562
1563 case PROCESSOR_PPC8540:
1564 rs6000_cost = &ppc8540_cost;
1565 break;
1566
1567 case PROCESSOR_POWER4:
1568 case PROCESSOR_POWER5:
1569 rs6000_cost = &power4_cost;
1570 break;
1571
1572 default:
1573 gcc_unreachable ();
1574 }
1575 }
1576
1577 /* Implement targetm.vectorize.builtin_mask_for_load. */
1578 static tree
rs6000_builtin_mask_for_load(void)1579 rs6000_builtin_mask_for_load (void)
1580 {
1581 if (TARGET_ALTIVEC)
1582 return altivec_builtin_mask_for_load;
1583 else
1584 return 0;
1585 }
1586
1587 /* Handle generic options of the form -mfoo=yes/no.
1588 NAME is the option name.
1589 VALUE is the option value.
1590 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1591 whether the option value is 'yes' or 'no' respectively. */
1592 static void
rs6000_parse_yes_no_option(const char * name,const char * value,int * flag)1593 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1594 {
1595 if (value == 0)
1596 return;
1597 else if (!strcmp (value, "yes"))
1598 *flag = 1;
1599 else if (!strcmp (value, "no"))
1600 *flag = 0;
1601 else
1602 error ("unknown -m%s= option specified: '%s'", name, value);
1603 }
1604
1605 /* Validate and record the size specified with the -mtls-size option. */
1606
1607 static void
rs6000_parse_tls_size_option(void)1608 rs6000_parse_tls_size_option (void)
1609 {
1610 if (rs6000_tls_size_string == 0)
1611 return;
1612 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1613 rs6000_tls_size = 16;
1614 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1615 rs6000_tls_size = 32;
1616 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1617 rs6000_tls_size = 64;
1618 else
1619 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1620 }
1621
1622 void
optimization_options(int level ATTRIBUTE_UNUSED,int size ATTRIBUTE_UNUSED)1623 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1624 {
1625 if (DEFAULT_ABI == ABI_DARWIN)
1626 /* The Darwin libraries never set errno, so we might as well
1627 avoid calling them when that's the only reason we would. */
1628 flag_errno_math = 0;
1629
1630 /* Double growth factor to counter reduced min jump length. */
1631 set_param_value ("max-grow-copy-bb-insns", 16);
1632
1633 /* Enable section anchors by default.
1634 Skip section anchors for Objective C and Objective C++
1635 until front-ends fixed. */
1636 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1637 flag_section_anchors = 1;
1638 }
1639
1640 /* Implement TARGET_HANDLE_OPTION. */
1641
1642 static bool
rs6000_handle_option(size_t code,const char * arg,int value)1643 rs6000_handle_option (size_t code, const char *arg, int value)
1644 {
1645 switch (code)
1646 {
1647 case OPT_mno_power:
1648 target_flags &= ~(MASK_POWER | MASK_POWER2
1649 | MASK_MULTIPLE | MASK_STRING);
1650 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1651 | MASK_MULTIPLE | MASK_STRING);
1652 break;
1653 case OPT_mno_powerpc:
1654 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1655 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1656 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1657 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1658 break;
1659 case OPT_mfull_toc:
1660 target_flags &= ~MASK_MINIMAL_TOC;
1661 TARGET_NO_FP_IN_TOC = 0;
1662 TARGET_NO_SUM_IN_TOC = 0;
1663 target_flags_explicit |= MASK_MINIMAL_TOC;
1664 #ifdef TARGET_USES_SYSV4_OPT
1665 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1666 just the same as -mminimal-toc. */
1667 target_flags |= MASK_MINIMAL_TOC;
1668 target_flags_explicit |= MASK_MINIMAL_TOC;
1669 #endif
1670 break;
1671
1672 #ifdef TARGET_USES_SYSV4_OPT
1673 case OPT_mtoc:
1674 /* Make -mtoc behave like -mminimal-toc. */
1675 target_flags |= MASK_MINIMAL_TOC;
1676 target_flags_explicit |= MASK_MINIMAL_TOC;
1677 break;
1678 #endif
1679
1680 #ifdef TARGET_USES_AIX64_OPT
1681 case OPT_maix64:
1682 #else
1683 case OPT_m64:
1684 #endif
1685 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1686 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1687 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1688 break;
1689
1690 #ifdef TARGET_USES_AIX64_OPT
1691 case OPT_maix32:
1692 #else
1693 case OPT_m32:
1694 #endif
1695 target_flags &= ~MASK_POWERPC64;
1696 target_flags_explicit |= MASK_POWERPC64;
1697 break;
1698
1699 case OPT_minsert_sched_nops_:
1700 rs6000_sched_insert_nops_str = arg;
1701 break;
1702
1703 case OPT_mminimal_toc:
1704 if (value == 1)
1705 {
1706 TARGET_NO_FP_IN_TOC = 0;
1707 TARGET_NO_SUM_IN_TOC = 0;
1708 }
1709 break;
1710
1711 case OPT_mpower:
1712 if (value == 1)
1713 {
1714 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1715 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1716 }
1717 break;
1718
1719 case OPT_mpower2:
1720 if (value == 1)
1721 {
1722 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1723 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1724 }
1725 break;
1726
1727 case OPT_mpowerpc_gpopt:
1728 case OPT_mpowerpc_gfxopt:
1729 if (value == 1)
1730 {
1731 target_flags |= MASK_POWERPC;
1732 target_flags_explicit |= MASK_POWERPC;
1733 }
1734 break;
1735
1736 case OPT_maix_struct_return:
1737 case OPT_msvr4_struct_return:
1738 rs6000_explicit_options.aix_struct_ret = true;
1739 break;
1740
1741 case OPT_mvrsave_:
1742 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1743 break;
1744
1745 case OPT_misel_:
1746 rs6000_explicit_options.isel = true;
1747 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1748 break;
1749
1750 case OPT_mspe_:
1751 rs6000_explicit_options.spe = true;
1752 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1753 /* No SPE means 64-bit long doubles, even if an E500. */
1754 if (!rs6000_spe)
1755 rs6000_long_double_type_size = 64;
1756 break;
1757
1758 case OPT_mdebug_:
1759 rs6000_debug_name = arg;
1760 break;
1761
1762 #ifdef TARGET_USES_SYSV4_OPT
1763 case OPT_mcall_:
1764 rs6000_abi_name = arg;
1765 break;
1766
1767 case OPT_msdata_:
1768 rs6000_sdata_name = arg;
1769 break;
1770
1771 case OPT_mtls_size_:
1772 rs6000_tls_size_string = arg;
1773 break;
1774
1775 case OPT_mrelocatable:
1776 if (value == 1)
1777 {
1778 target_flags |= MASK_MINIMAL_TOC;
1779 target_flags_explicit |= MASK_MINIMAL_TOC;
1780 TARGET_NO_FP_IN_TOC = 1;
1781 }
1782 break;
1783
1784 case OPT_mrelocatable_lib:
1785 if (value == 1)
1786 {
1787 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1788 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1789 TARGET_NO_FP_IN_TOC = 1;
1790 }
1791 else
1792 {
1793 target_flags &= ~MASK_RELOCATABLE;
1794 target_flags_explicit |= MASK_RELOCATABLE;
1795 }
1796 break;
1797 #endif
1798
1799 case OPT_mabi_:
1800 if (!strcmp (arg, "altivec"))
1801 {
1802 rs6000_explicit_options.abi = true;
1803 rs6000_altivec_abi = 1;
1804 rs6000_spe_abi = 0;
1805 }
1806 else if (! strcmp (arg, "no-altivec"))
1807 {
1808 /* ??? Don't set rs6000_explicit_options.abi here, to allow
1809 the default for rs6000_spe_abi to be chosen later. */
1810 rs6000_altivec_abi = 0;
1811 }
1812 else if (! strcmp (arg, "spe"))
1813 {
1814 rs6000_explicit_options.abi = true;
1815 rs6000_spe_abi = 1;
1816 rs6000_altivec_abi = 0;
1817 if (!TARGET_SPE_ABI)
1818 error ("not configured for ABI: '%s'", arg);
1819 }
1820 else if (! strcmp (arg, "no-spe"))
1821 {
1822 rs6000_explicit_options.abi = true;
1823 rs6000_spe_abi = 0;
1824 }
1825
1826 /* These are here for testing during development only, do not
1827 document in the manual please. */
1828 else if (! strcmp (arg, "d64"))
1829 {
1830 rs6000_darwin64_abi = 1;
1831 warning (0, "Using darwin64 ABI");
1832 }
1833 else if (! strcmp (arg, "d32"))
1834 {
1835 rs6000_darwin64_abi = 0;
1836 warning (0, "Using old darwin ABI");
1837 }
1838
1839 else if (! strcmp (arg, "ibmlongdouble"))
1840 {
1841 rs6000_explicit_options.ieee = true;
1842 rs6000_ieeequad = 0;
1843 warning (0, "Using IBM extended precision long double");
1844 }
1845 else if (! strcmp (arg, "ieeelongdouble"))
1846 {
1847 rs6000_explicit_options.ieee = true;
1848 rs6000_ieeequad = 1;
1849 warning (0, "Using IEEE extended precision long double");
1850 }
1851
1852 else
1853 {
1854 error ("unknown ABI specified: '%s'", arg);
1855 return false;
1856 }
1857 break;
1858
1859 case OPT_mcpu_:
1860 rs6000_select[1].string = arg;
1861 break;
1862
1863 case OPT_mtune_:
1864 rs6000_select[2].string = arg;
1865 break;
1866
1867 case OPT_mtraceback_:
1868 rs6000_traceback_name = arg;
1869 break;
1870
1871 case OPT_mfloat_gprs_:
1872 rs6000_explicit_options.float_gprs = true;
1873 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1874 rs6000_float_gprs = 1;
1875 else if (! strcmp (arg, "double"))
1876 rs6000_float_gprs = 2;
1877 else if (! strcmp (arg, "no"))
1878 rs6000_float_gprs = 0;
1879 else
1880 {
1881 error ("invalid option for -mfloat-gprs: '%s'", arg);
1882 return false;
1883 }
1884 break;
1885
1886 case OPT_mlong_double_:
1887 rs6000_explicit_options.long_double = true;
1888 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1889 if (value != 64 && value != 128)
1890 {
1891 error ("Unknown switch -mlong-double-%s", arg);
1892 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1893 return false;
1894 }
1895 else
1896 rs6000_long_double_type_size = value;
1897 break;
1898
1899 case OPT_msched_costly_dep_:
1900 rs6000_sched_costly_dep_str = arg;
1901 break;
1902
1903 case OPT_malign_:
1904 rs6000_explicit_options.alignment = true;
1905 if (! strcmp (arg, "power"))
1906 {
1907 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1908 some C library functions, so warn about it. The flag may be
1909 useful for performance studies from time to time though, so
1910 don't disable it entirely. */
1911 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1912 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1913 " it is incompatible with the installed C and C++ libraries");
1914 rs6000_alignment_flags = MASK_ALIGN_POWER;
1915 }
1916 else if (! strcmp (arg, "natural"))
1917 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1918 else
1919 {
1920 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1921 return false;
1922 }
1923 break;
1924 }
1925 return true;
1926 }
1927
1928 /* Do anything needed at the start of the asm file. */
1929
1930 static void
rs6000_file_start(void)1931 rs6000_file_start (void)
1932 {
1933 size_t i;
1934 char buffer[80];
1935 const char *start = buffer;
1936 struct rs6000_cpu_select *ptr;
1937 const char *default_cpu = TARGET_CPU_DEFAULT;
1938 FILE *file = asm_out_file;
1939
1940 default_file_start ();
1941
1942 #ifdef TARGET_BI_ARCH
1943 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1944 default_cpu = 0;
1945 #endif
1946
1947 if (flag_verbose_asm)
1948 {
1949 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1950 rs6000_select[0].string = default_cpu;
1951
1952 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1953 {
1954 ptr = &rs6000_select[i];
1955 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1956 {
1957 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1958 start = "";
1959 }
1960 }
1961
1962 if (PPC405_ERRATUM77)
1963 {
1964 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1965 start = "";
1966 }
1967
1968 #ifdef USING_ELFOS_H
1969 switch (rs6000_sdata)
1970 {
1971 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1972 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1973 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1974 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1975 }
1976
1977 if (rs6000_sdata && g_switch_value)
1978 {
1979 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1980 g_switch_value);
1981 start = "";
1982 }
1983 #endif
1984
1985 if (*start == '\0')
1986 putc ('\n', file);
1987 }
1988
1989 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1990 {
1991 switch_to_section (toc_section);
1992 switch_to_section (text_section);
1993 }
1994 }
1995
1996
1997 /* Return nonzero if this function is known to have a null epilogue. */
1998
1999 int
direct_return(void)2000 direct_return (void)
2001 {
2002 if (reload_completed)
2003 {
2004 rs6000_stack_t *info = rs6000_stack_info ();
2005
2006 if (info->first_gp_reg_save == 32
2007 && info->first_fp_reg_save == 64
2008 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2009 && ! info->lr_save_p
2010 && ! info->cr_save_p
2011 && info->vrsave_mask == 0
2012 && ! info->push_p)
2013 return 1;
2014 }
2015
2016 return 0;
2017 }
2018
2019 /* Return the number of instructions it takes to form a constant in an
2020 integer register. */
2021
2022 int
num_insns_constant_wide(HOST_WIDE_INT value)2023 num_insns_constant_wide (HOST_WIDE_INT value)
2024 {
2025 /* signed constant loadable with {cal|addi} */
2026 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2027 return 1;
2028
2029 /* constant loadable with {cau|addis} */
2030 else if ((value & 0xffff) == 0
2031 && (value >> 31 == -1 || value >> 31 == 0))
2032 return 1;
2033
2034 #if HOST_BITS_PER_WIDE_INT == 64
2035 else if (TARGET_POWERPC64)
2036 {
2037 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2038 HOST_WIDE_INT high = value >> 31;
2039
2040 if (high == 0 || high == -1)
2041 return 2;
2042
2043 high >>= 1;
2044
2045 if (low == 0)
2046 return num_insns_constant_wide (high) + 1;
2047 else
2048 return (num_insns_constant_wide (high)
2049 + num_insns_constant_wide (low) + 1);
2050 }
2051 #endif
2052
2053 else
2054 return 2;
2055 }
2056
2057 int
num_insns_constant(rtx op,enum machine_mode mode)2058 num_insns_constant (rtx op, enum machine_mode mode)
2059 {
2060 HOST_WIDE_INT low, high;
2061
2062 switch (GET_CODE (op))
2063 {
2064 case CONST_INT:
2065 #if HOST_BITS_PER_WIDE_INT == 64
2066 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2067 && mask64_operand (op, mode))
2068 return 2;
2069 else
2070 #endif
2071 return num_insns_constant_wide (INTVAL (op));
2072
2073 case CONST_DOUBLE:
2074 if (mode == SFmode)
2075 {
2076 long l;
2077 REAL_VALUE_TYPE rv;
2078
2079 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2080 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2081 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2082 }
2083
2084 if (mode == VOIDmode || mode == DImode)
2085 {
2086 high = CONST_DOUBLE_HIGH (op);
2087 low = CONST_DOUBLE_LOW (op);
2088 }
2089 else
2090 {
2091 long l[2];
2092 REAL_VALUE_TYPE rv;
2093
2094 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2095 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2096 high = l[WORDS_BIG_ENDIAN == 0];
2097 low = l[WORDS_BIG_ENDIAN != 0];
2098 }
2099
2100 if (TARGET_32BIT)
2101 return (num_insns_constant_wide (low)
2102 + num_insns_constant_wide (high));
2103 else
2104 {
2105 if ((high == 0 && low >= 0)
2106 || (high == -1 && low < 0))
2107 return num_insns_constant_wide (low);
2108
2109 else if (mask64_operand (op, mode))
2110 return 2;
2111
2112 else if (low == 0)
2113 return num_insns_constant_wide (high) + 1;
2114
2115 else
2116 return (num_insns_constant_wide (high)
2117 + num_insns_constant_wide (low) + 1);
2118 }
2119
2120 default:
2121 gcc_unreachable ();
2122 }
2123 }
2124
2125 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2126 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2127 corresponding element of the vector, but for V4SFmode and V2SFmode,
2128 the corresponding "float" is interpreted as an SImode integer. */
2129
2130 static HOST_WIDE_INT
const_vector_elt_as_int(rtx op,unsigned int elt)2131 const_vector_elt_as_int (rtx op, unsigned int elt)
2132 {
2133 rtx tmp = CONST_VECTOR_ELT (op, elt);
2134 if (GET_MODE (op) == V4SFmode
2135 || GET_MODE (op) == V2SFmode)
2136 tmp = gen_lowpart (SImode, tmp);
2137 return INTVAL (tmp);
2138 }
2139
2140 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2141 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2142 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2143 all items are set to the same value and contain COPIES replicas of the
2144 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2145 operand and the others are set to the value of the operand's msb. */
2146
2147 static bool
vspltis_constant(rtx op,unsigned step,unsigned copies)2148 vspltis_constant (rtx op, unsigned step, unsigned copies)
2149 {
2150 enum machine_mode mode = GET_MODE (op);
2151 enum machine_mode inner = GET_MODE_INNER (mode);
2152
2153 unsigned i;
2154 unsigned nunits = GET_MODE_NUNITS (mode);
2155 unsigned bitsize = GET_MODE_BITSIZE (inner);
2156 unsigned mask = GET_MODE_MASK (inner);
2157
2158 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2159 HOST_WIDE_INT splat_val = val;
2160 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2161
2162 /* Construct the value to be splatted, if possible. If not, return 0. */
2163 for (i = 2; i <= copies; i *= 2)
2164 {
2165 HOST_WIDE_INT small_val;
2166 bitsize /= 2;
2167 small_val = splat_val >> bitsize;
2168 mask >>= bitsize;
2169 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2170 return false;
2171 splat_val = small_val;
2172 }
2173
2174 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2175 if (EASY_VECTOR_15 (splat_val))
2176 ;
2177
2178 /* Also check if we can splat, and then add the result to itself. Do so if
2179 the value is positive, of if the splat instruction is using OP's mode;
2180 for splat_val < 0, the splat and the add should use the same mode. */
2181 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2182 && (splat_val >= 0 || (step == 1 && copies == 1)))
2183 ;
2184
2185 else
2186 return false;
2187
2188 /* Check if VAL is present in every STEP-th element, and the
2189 other elements are filled with its most significant bit. */
2190 for (i = 0; i < nunits - 1; ++i)
2191 {
2192 HOST_WIDE_INT desired_val;
2193 if (((i + 1) & (step - 1)) == 0)
2194 desired_val = val;
2195 else
2196 desired_val = msb_val;
2197
2198 if (desired_val != const_vector_elt_as_int (op, i))
2199 return false;
2200 }
2201
2202 return true;
2203 }
2204
2205
2206 /* Return true if OP is of the given MODE and can be synthesized
2207 with a vspltisb, vspltish or vspltisw. */
2208
2209 bool
easy_altivec_constant(rtx op,enum machine_mode mode)2210 easy_altivec_constant (rtx op, enum machine_mode mode)
2211 {
2212 unsigned step, copies;
2213
2214 if (mode == VOIDmode)
2215 mode = GET_MODE (op);
2216 else if (mode != GET_MODE (op))
2217 return false;
2218
2219 /* Start with a vspltisw. */
2220 step = GET_MODE_NUNITS (mode) / 4;
2221 copies = 1;
2222
2223 if (vspltis_constant (op, step, copies))
2224 return true;
2225
2226 /* Then try with a vspltish. */
2227 if (step == 1)
2228 copies <<= 1;
2229 else
2230 step >>= 1;
2231
2232 if (vspltis_constant (op, step, copies))
2233 return true;
2234
2235 /* And finally a vspltisb. */
2236 if (step == 1)
2237 copies <<= 1;
2238 else
2239 step >>= 1;
2240
2241 if (vspltis_constant (op, step, copies))
2242 return true;
2243
2244 return false;
2245 }
2246
2247 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2248 result is OP. Abort if it is not possible. */
2249
2250 rtx
gen_easy_altivec_constant(rtx op)2251 gen_easy_altivec_constant (rtx op)
2252 {
2253 enum machine_mode mode = GET_MODE (op);
2254 int nunits = GET_MODE_NUNITS (mode);
2255 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2256 unsigned step = nunits / 4;
2257 unsigned copies = 1;
2258
2259 /* Start with a vspltisw. */
2260 if (vspltis_constant (op, step, copies))
2261 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2262
2263 /* Then try with a vspltish. */
2264 if (step == 1)
2265 copies <<= 1;
2266 else
2267 step >>= 1;
2268
2269 if (vspltis_constant (op, step, copies))
2270 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2271
2272 /* And finally a vspltisb. */
2273 if (step == 1)
2274 copies <<= 1;
2275 else
2276 step >>= 1;
2277
2278 if (vspltis_constant (op, step, copies))
2279 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2280
2281 gcc_unreachable ();
2282 }
2283
2284 const char *
output_vec_const_move(rtx * operands)2285 output_vec_const_move (rtx *operands)
2286 {
2287 int cst, cst2;
2288 enum machine_mode mode;
2289 rtx dest, vec;
2290
2291 dest = operands[0];
2292 vec = operands[1];
2293 mode = GET_MODE (dest);
2294
2295 if (TARGET_ALTIVEC)
2296 {
2297 rtx splat_vec;
2298 if (zero_constant (vec, mode))
2299 return "vxor %0,%0,%0";
2300
2301 splat_vec = gen_easy_altivec_constant (vec);
2302 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2303 operands[1] = XEXP (splat_vec, 0);
2304 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2305 return "#";
2306
2307 switch (GET_MODE (splat_vec))
2308 {
2309 case V4SImode:
2310 return "vspltisw %0,%1";
2311
2312 case V8HImode:
2313 return "vspltish %0,%1";
2314
2315 case V16QImode:
2316 return "vspltisb %0,%1";
2317
2318 default:
2319 gcc_unreachable ();
2320 }
2321 }
2322
2323 gcc_assert (TARGET_SPE);
2324
2325 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2326 pattern of V1DI, V4HI, and V2SF.
2327
2328 FIXME: We should probably return # and add post reload
2329 splitters for these, but this way is so easy ;-). */
2330 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2331 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2332 operands[1] = CONST_VECTOR_ELT (vec, 0);
2333 operands[2] = CONST_VECTOR_ELT (vec, 1);
2334 if (cst == cst2)
2335 return "li %0,%1\n\tevmergelo %0,%0,%0";
2336 else
2337 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2338 }
2339
2340 /* Initialize vector TARGET to VALS. */
2341
2342 void
rs6000_expand_vector_init(rtx target,rtx vals)2343 rs6000_expand_vector_init (rtx target, rtx vals)
2344 {
2345 enum machine_mode mode = GET_MODE (target);
2346 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2347 int n_elts = GET_MODE_NUNITS (mode);
2348 int n_var = 0, one_var = -1;
2349 bool all_same = true, all_const_zero = true;
2350 rtx x, mem;
2351 int i;
2352
2353 for (i = 0; i < n_elts; ++i)
2354 {
2355 x = XVECEXP (vals, 0, i);
2356 if (!CONSTANT_P (x))
2357 ++n_var, one_var = i;
2358 else if (x != CONST0_RTX (inner_mode))
2359 all_const_zero = false;
2360
2361 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2362 all_same = false;
2363 }
2364
2365 if (n_var == 0)
2366 {
2367 if (mode != V4SFmode && all_const_zero)
2368 {
2369 /* Zero register. */
2370 emit_insn (gen_rtx_SET (VOIDmode, target,
2371 gen_rtx_XOR (mode, target, target)));
2372 return;
2373 }
2374 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2375 {
2376 /* Splat immediate. */
2377 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2378 return;
2379 }
2380 else if (all_same)
2381 ; /* Splat vector element. */
2382 else
2383 {
2384 /* Load from constant pool. */
2385 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2386 return;
2387 }
2388 }
2389
2390 /* Store value to stack temp. Load vector element. Splat. */
2391 if (all_same)
2392 {
2393 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2394 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2395 XVECEXP (vals, 0, 0));
2396 x = gen_rtx_UNSPEC (VOIDmode,
2397 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2398 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2399 gen_rtvec (2,
2400 gen_rtx_SET (VOIDmode,
2401 target, mem),
2402 x)));
2403 x = gen_rtx_VEC_SELECT (inner_mode, target,
2404 gen_rtx_PARALLEL (VOIDmode,
2405 gen_rtvec (1, const0_rtx)));
2406 emit_insn (gen_rtx_SET (VOIDmode, target,
2407 gen_rtx_VEC_DUPLICATE (mode, x)));
2408 return;
2409 }
2410
2411 /* One field is non-constant. Load constant then overwrite
2412 varying field. */
2413 if (n_var == 1)
2414 {
2415 rtx copy = copy_rtx (vals);
2416
2417 /* Load constant part of vector, substitute neighboring value for
2418 varying element. */
2419 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2420 rs6000_expand_vector_init (target, copy);
2421
2422 /* Insert variable. */
2423 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2424 return;
2425 }
2426
2427 /* Construct the vector in memory one field at a time
2428 and load the whole vector. */
2429 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2430 for (i = 0; i < n_elts; i++)
2431 emit_move_insn (adjust_address_nv (mem, inner_mode,
2432 i * GET_MODE_SIZE (inner_mode)),
2433 XVECEXP (vals, 0, i));
2434 emit_move_insn (target, mem);
2435 }
2436
2437 /* Set field ELT of TARGET to VAL. */
2438
2439 void
rs6000_expand_vector_set(rtx target,rtx val,int elt)2440 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2441 {
2442 enum machine_mode mode = GET_MODE (target);
2443 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2444 rtx reg = gen_reg_rtx (mode);
2445 rtx mask, mem, x;
2446 int width = GET_MODE_SIZE (inner_mode);
2447 int i;
2448
2449 /* Load single variable value. */
2450 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2451 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2452 x = gen_rtx_UNSPEC (VOIDmode,
2453 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2454 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2455 gen_rtvec (2,
2456 gen_rtx_SET (VOIDmode,
2457 reg, mem),
2458 x)));
2459
2460 /* Linear sequence. */
2461 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2462 for (i = 0; i < 16; ++i)
2463 XVECEXP (mask, 0, i) = GEN_INT (i);
2464
2465 /* Set permute mask to insert element into target. */
2466 for (i = 0; i < width; ++i)
2467 XVECEXP (mask, 0, elt*width + i)
2468 = GEN_INT (i + 0x10);
2469 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2470 x = gen_rtx_UNSPEC (mode,
2471 gen_rtvec (3, target, reg,
2472 force_reg (V16QImode, x)),
2473 UNSPEC_VPERM);
2474 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2475 }
2476
2477 /* Extract field ELT from VEC into TARGET. */
2478
2479 void
rs6000_expand_vector_extract(rtx target,rtx vec,int elt)2480 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2481 {
2482 enum machine_mode mode = GET_MODE (vec);
2483 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2484 rtx mem, x;
2485
2486 /* Allocate mode-sized buffer. */
2487 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2488
2489 /* Add offset to field within buffer matching vector element. */
2490 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2491
2492 /* Store single field into mode-sized buffer. */
2493 x = gen_rtx_UNSPEC (VOIDmode,
2494 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2495 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2496 gen_rtvec (2,
2497 gen_rtx_SET (VOIDmode,
2498 mem, vec),
2499 x)));
2500 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2501 }
2502
2503 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2504 implement ANDing by the mask IN. */
2505 void
build_mask64_2_operands(rtx in,rtx * out)2506 build_mask64_2_operands (rtx in, rtx *out)
2507 {
2508 #if HOST_BITS_PER_WIDE_INT >= 64
2509 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2510 int shift;
2511
2512 gcc_assert (GET_CODE (in) == CONST_INT);
2513
2514 c = INTVAL (in);
2515 if (c & 1)
2516 {
2517 /* Assume c initially something like 0x00fff000000fffff. The idea
2518 is to rotate the word so that the middle ^^^^^^ group of zeros
2519 is at the MS end and can be cleared with an rldicl mask. We then
2520 rotate back and clear off the MS ^^ group of zeros with a
2521 second rldicl. */
2522 c = ~c; /* c == 0xff000ffffff00000 */
2523 lsb = c & -c; /* lsb == 0x0000000000100000 */
2524 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2525 c = ~c; /* c == 0x00fff000000fffff */
2526 c &= -lsb; /* c == 0x00fff00000000000 */
2527 lsb = c & -c; /* lsb == 0x0000100000000000 */
2528 c = ~c; /* c == 0xff000fffffffffff */
2529 c &= -lsb; /* c == 0xff00000000000000 */
2530 shift = 0;
2531 while ((lsb >>= 1) != 0)
2532 shift++; /* shift == 44 on exit from loop */
2533 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2534 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2535 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2536 }
2537 else
2538 {
2539 /* Assume c initially something like 0xff000f0000000000. The idea
2540 is to rotate the word so that the ^^^ middle group of zeros
2541 is at the LS end and can be cleared with an rldicr mask. We then
2542 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2543 a second rldicr. */
2544 lsb = c & -c; /* lsb == 0x0000010000000000 */
2545 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2546 c = ~c; /* c == 0x00fff0ffffffffff */
2547 c &= -lsb; /* c == 0x00fff00000000000 */
2548 lsb = c & -c; /* lsb == 0x0000100000000000 */
2549 c = ~c; /* c == 0xff000fffffffffff */
2550 c &= -lsb; /* c == 0xff00000000000000 */
2551 shift = 0;
2552 while ((lsb >>= 1) != 0)
2553 shift++; /* shift == 44 on exit from loop */
2554 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2555 m1 >>= shift; /* m1 == 0x0000000000000fff */
2556 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2557 }
2558
2559 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2560 masks will be all 1's. We are guaranteed more than one transition. */
2561 out[0] = GEN_INT (64 - shift);
2562 out[1] = GEN_INT (m1);
2563 out[2] = GEN_INT (shift);
2564 out[3] = GEN_INT (m2);
2565 #else
2566 (void)in;
2567 (void)out;
2568 gcc_unreachable ();
2569 #endif
2570 }
2571
2572 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2573
2574 bool
invalid_e500_subreg(rtx op,enum machine_mode mode)2575 invalid_e500_subreg (rtx op, enum machine_mode mode)
2576 {
2577 if (TARGET_E500_DOUBLE)
2578 {
2579 /* Reject (subreg:SI (reg:DF)). */
2580 if (GET_CODE (op) == SUBREG
2581 && mode == SImode
2582 && REG_P (SUBREG_REG (op))
2583 && GET_MODE (SUBREG_REG (op)) == DFmode)
2584 return true;
2585
2586 /* Reject (subreg:DF (reg:DI)). */
2587 if (GET_CODE (op) == SUBREG
2588 && mode == DFmode
2589 && REG_P (SUBREG_REG (op))
2590 && GET_MODE (SUBREG_REG (op)) == DImode)
2591 return true;
2592 }
2593
2594 if (TARGET_SPE
2595 && GET_CODE (op) == SUBREG
2596 && mode == SImode
2597 && REG_P (SUBREG_REG (op))
2598 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2599 return true;
2600
2601 return false;
2602 }
2603
2604 /* Darwin, AIX increases natural record alignment to doubleword if the first
2605 field is an FP double while the FP fields remain word aligned. */
2606
2607 unsigned int
rs6000_special_round_type_align(tree type,unsigned int computed,unsigned int specified)2608 rs6000_special_round_type_align (tree type, unsigned int computed,
2609 unsigned int specified)
2610 {
2611 unsigned int align = MAX (computed, specified);
2612 tree field = TYPE_FIELDS (type);
2613
2614 /* Skip all non field decls */
2615 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2616 field = TREE_CHAIN (field);
2617
2618 if (field != NULL && field != type)
2619 {
2620 type = TREE_TYPE (field);
2621 while (TREE_CODE (type) == ARRAY_TYPE)
2622 type = TREE_TYPE (type);
2623
2624 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2625 align = MAX (align, 64);
2626 }
2627
2628 return align;
2629 }
2630
2631 /* Return 1 for an operand in small memory on V.4/eabi. */
2632
2633 int
small_data_operand(rtx op ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED)2634 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2635 enum machine_mode mode ATTRIBUTE_UNUSED)
2636 {
2637 #if TARGET_ELF
2638 rtx sym_ref;
2639
2640 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2641 return 0;
2642
2643 if (DEFAULT_ABI != ABI_V4)
2644 return 0;
2645
2646 if (GET_CODE (op) == SYMBOL_REF)
2647 sym_ref = op;
2648
2649 else if (GET_CODE (op) != CONST
2650 || GET_CODE (XEXP (op, 0)) != PLUS
2651 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2652 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2653 return 0;
2654
2655 else
2656 {
2657 rtx sum = XEXP (op, 0);
2658 HOST_WIDE_INT summand;
2659
2660 /* We have to be careful here, because it is the referenced address
2661 that must be 32k from _SDA_BASE_, not just the symbol. */
2662 summand = INTVAL (XEXP (sum, 1));
2663 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2664 return 0;
2665
2666 sym_ref = XEXP (sum, 0);
2667 }
2668
2669 return SYMBOL_REF_SMALL_P (sym_ref);
2670 #else
2671 return 0;
2672 #endif
2673 }
2674
2675 /* Return true if either operand is a general purpose register. */
2676
2677 bool
gpr_or_gpr_p(rtx op0,rtx op1)2678 gpr_or_gpr_p (rtx op0, rtx op1)
2679 {
2680 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2681 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2682 }
2683
2684
2685 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2686
2687 static int
constant_pool_expr_1(rtx op,int * have_sym,int * have_toc)2688 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2689 {
2690 switch (GET_CODE (op))
2691 {
2692 case SYMBOL_REF:
2693 if (RS6000_SYMBOL_REF_TLS_P (op))
2694 return 0;
2695 else if (CONSTANT_POOL_ADDRESS_P (op))
2696 {
2697 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2698 {
2699 *have_sym = 1;
2700 return 1;
2701 }
2702 else
2703 return 0;
2704 }
2705 else if (! strcmp (XSTR (op, 0), toc_label_name))
2706 {
2707 *have_toc = 1;
2708 return 1;
2709 }
2710 else
2711 return 0;
2712 case PLUS:
2713 case MINUS:
2714 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2715 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2716 case CONST:
2717 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2718 case CONST_INT:
2719 return 1;
2720 default:
2721 return 0;
2722 }
2723 }
2724
2725 static bool
constant_pool_expr_p(rtx op)2726 constant_pool_expr_p (rtx op)
2727 {
2728 int have_sym = 0;
2729 int have_toc = 0;
2730 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2731 }
2732
2733 bool
toc_relative_expr_p(rtx op)2734 toc_relative_expr_p (rtx op)
2735 {
2736 int have_sym = 0;
2737 int have_toc = 0;
2738 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2739 }
2740
2741 bool
legitimate_constant_pool_address_p(rtx x)2742 legitimate_constant_pool_address_p (rtx x)
2743 {
2744 return (TARGET_TOC
2745 && GET_CODE (x) == PLUS
2746 && GET_CODE (XEXP (x, 0)) == REG
2747 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2748 && constant_pool_expr_p (XEXP (x, 1)));
2749 }
2750
2751 static bool
legitimate_small_data_p(enum machine_mode mode,rtx x)2752 legitimate_small_data_p (enum machine_mode mode, rtx x)
2753 {
2754 return (DEFAULT_ABI == ABI_V4
2755 && !flag_pic && !TARGET_TOC
2756 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2757 && small_data_operand (x, mode));
2758 }
2759
2760 /* SPE offset addressing is limited to 5-bits worth of double words. */
2761 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2762
2763 bool
rs6000_legitimate_offset_address_p(enum machine_mode mode,rtx x,int strict)2764 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2765 {
2766 unsigned HOST_WIDE_INT offset, extra;
2767
2768 if (GET_CODE (x) != PLUS)
2769 return false;
2770 if (GET_CODE (XEXP (x, 0)) != REG)
2771 return false;
2772 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2773 return false;
2774 if (legitimate_constant_pool_address_p (x))
2775 return true;
2776 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2777 return false;
2778
2779 offset = INTVAL (XEXP (x, 1));
2780 extra = 0;
2781 switch (mode)
2782 {
2783 case V16QImode:
2784 case V8HImode:
2785 case V4SFmode:
2786 case V4SImode:
2787 /* AltiVec vector modes. Only reg+reg addressing is valid and
2788 constant offset zero should not occur due to canonicalization.
2789 Allow any offset when not strict before reload. */
2790 return !strict;
2791
2792 case V4HImode:
2793 case V2SImode:
2794 case V1DImode:
2795 case V2SFmode:
2796 /* SPE vector modes. */
2797 return SPE_CONST_OFFSET_OK (offset);
2798
2799 case DFmode:
2800 if (TARGET_E500_DOUBLE)
2801 return SPE_CONST_OFFSET_OK (offset);
2802
2803 case DImode:
2804 /* On e500v2, we may have:
2805
2806 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2807
2808 Which gets addressed with evldd instructions. */
2809 if (TARGET_E500_DOUBLE)
2810 return SPE_CONST_OFFSET_OK (offset);
2811
2812 if (mode == DFmode || !TARGET_POWERPC64)
2813 extra = 4;
2814 else if (offset & 3)
2815 return false;
2816 break;
2817
2818 case TFmode:
2819 case TImode:
2820 if (mode == TFmode || !TARGET_POWERPC64)
2821 extra = 12;
2822 else if (offset & 3)
2823 return false;
2824 else
2825 extra = 8;
2826 break;
2827
2828 default:
2829 break;
2830 }
2831
2832 offset += 0x8000;
2833 return (offset < 0x10000) && (offset + extra < 0x10000);
2834 }
2835
2836 static bool
legitimate_indexed_address_p(rtx x,int strict)2837 legitimate_indexed_address_p (rtx x, int strict)
2838 {
2839 rtx op0, op1;
2840
2841 if (GET_CODE (x) != PLUS)
2842 return false;
2843
2844 op0 = XEXP (x, 0);
2845 op1 = XEXP (x, 1);
2846
2847 /* Recognize the rtl generated by reload which we know will later be
2848 replaced with proper base and index regs. */
2849 if (!strict
2850 && reload_in_progress
2851 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2852 && REG_P (op1))
2853 return true;
2854
2855 return (REG_P (op0) && REG_P (op1)
2856 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2857 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2858 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2859 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2860 }
2861
2862 inline bool
legitimate_indirect_address_p(rtx x,int strict)2863 legitimate_indirect_address_p (rtx x, int strict)
2864 {
2865 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2866 }
2867
2868 bool
macho_lo_sum_memory_operand(rtx x,enum machine_mode mode)2869 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2870 {
2871 if (!TARGET_MACHO || !flag_pic
2872 || mode != SImode || GET_CODE (x) != MEM)
2873 return false;
2874 x = XEXP (x, 0);
2875
2876 if (GET_CODE (x) != LO_SUM)
2877 return false;
2878 if (GET_CODE (XEXP (x, 0)) != REG)
2879 return false;
2880 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2881 return false;
2882 x = XEXP (x, 1);
2883
2884 return CONSTANT_P (x);
2885 }
2886
2887 static bool
legitimate_lo_sum_address_p(enum machine_mode mode,rtx x,int strict)2888 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2889 {
2890 if (GET_CODE (x) != LO_SUM)
2891 return false;
2892 if (GET_CODE (XEXP (x, 0)) != REG)
2893 return false;
2894 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2895 return false;
2896 /* Restrict addressing for DI because of our SUBREG hackery. */
2897 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2898 return false;
2899 x = XEXP (x, 1);
2900
2901 if (TARGET_ELF || TARGET_MACHO)
2902 {
2903 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2904 return false;
2905 if (TARGET_TOC)
2906 return false;
2907 if (GET_MODE_NUNITS (mode) != 1)
2908 return false;
2909 if (GET_MODE_BITSIZE (mode) > 64
2910 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2911 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2912 return false;
2913
2914 return CONSTANT_P (x);
2915 }
2916
2917 return false;
2918 }
2919
2920
2921 /* Try machine-dependent ways of modifying an illegitimate address
2922 to be legitimate. If we find one, return the new, valid address.
2923 This is used from only one place: `memory_address' in explow.c.
2924
2925 OLDX is the address as it was before break_out_memory_refs was
2926 called. In some cases it is useful to look at this to decide what
2927 needs to be done.
2928
2929 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2930
2931 It is always safe for this function to do nothing. It exists to
2932 recognize opportunities to optimize the output.
2933
2934 On RS/6000, first check for the sum of a register with a constant
2935 integer that is out of range. If so, generate code to add the
2936 constant with the low-order 16 bits masked to the register and force
2937 this result into another register (this can be done with `cau').
2938 Then generate an address of REG+(CONST&0xffff), allowing for the
2939 possibility of bit 16 being a one.
2940
2941 Then check for the sum of a register and something not constant, try to
2942 load the other things into a register and return the sum. */
2943
2944 rtx
rs6000_legitimize_address(rtx x,rtx oldx ATTRIBUTE_UNUSED,enum machine_mode mode)2945 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2946 enum machine_mode mode)
2947 {
2948 if (GET_CODE (x) == SYMBOL_REF)
2949 {
2950 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2951 if (model != 0)
2952 return rs6000_legitimize_tls_address (x, model);
2953 }
2954
2955 if (GET_CODE (x) == PLUS
2956 && GET_CODE (XEXP (x, 0)) == REG
2957 && GET_CODE (XEXP (x, 1)) == CONST_INT
2958 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2959 {
2960 HOST_WIDE_INT high_int, low_int;
2961 rtx sum;
2962 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2963 high_int = INTVAL (XEXP (x, 1)) - low_int;
2964 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2965 GEN_INT (high_int)), 0);
2966 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2967 }
2968 else if (GET_CODE (x) == PLUS
2969 && GET_CODE (XEXP (x, 0)) == REG
2970 && GET_CODE (XEXP (x, 1)) != CONST_INT
2971 && GET_MODE_NUNITS (mode) == 1
2972 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2973 || TARGET_POWERPC64
2974 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2975 && mode != TFmode))
2976 && (TARGET_POWERPC64 || mode != DImode)
2977 && mode != TImode)
2978 {
2979 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2980 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2981 }
2982 else if (ALTIVEC_VECTOR_MODE (mode))
2983 {
2984 rtx reg;
2985
2986 /* Make sure both operands are registers. */
2987 if (GET_CODE (x) == PLUS)
2988 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2989 force_reg (Pmode, XEXP (x, 1)));
2990
2991 reg = force_reg (Pmode, x);
2992 return reg;
2993 }
2994 else if (SPE_VECTOR_MODE (mode)
2995 || (TARGET_E500_DOUBLE && (mode == DFmode
2996 || mode == DImode)))
2997 {
2998 if (mode == DImode)
2999 return NULL_RTX;
3000 /* We accept [reg + reg] and [reg + OFFSET]. */
3001
3002 if (GET_CODE (x) == PLUS)
3003 {
3004 rtx op1 = XEXP (x, 0);
3005 rtx op2 = XEXP (x, 1);
3006
3007 op1 = force_reg (Pmode, op1);
3008
3009 if (GET_CODE (op2) != REG
3010 && (GET_CODE (op2) != CONST_INT
3011 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3012 op2 = force_reg (Pmode, op2);
3013
3014 return gen_rtx_PLUS (Pmode, op1, op2);
3015 }
3016
3017 return force_reg (Pmode, x);
3018 }
3019 else if (TARGET_ELF
3020 && TARGET_32BIT
3021 && TARGET_NO_TOC
3022 && ! flag_pic
3023 && GET_CODE (x) != CONST_INT
3024 && GET_CODE (x) != CONST_DOUBLE
3025 && CONSTANT_P (x)
3026 && GET_MODE_NUNITS (mode) == 1
3027 && (GET_MODE_BITSIZE (mode) <= 32
3028 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3029 {
3030 rtx reg = gen_reg_rtx (Pmode);
3031 emit_insn (gen_elf_high (reg, x));
3032 return gen_rtx_LO_SUM (Pmode, reg, x);
3033 }
3034 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3035 && ! flag_pic
3036 #if TARGET_MACHO
3037 && ! MACHO_DYNAMIC_NO_PIC_P
3038 #endif
3039 && GET_CODE (x) != CONST_INT
3040 && GET_CODE (x) != CONST_DOUBLE
3041 && CONSTANT_P (x)
3042 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3043 && mode != DImode
3044 && mode != TImode)
3045 {
3046 rtx reg = gen_reg_rtx (Pmode);
3047 emit_insn (gen_macho_high (reg, x));
3048 return gen_rtx_LO_SUM (Pmode, reg, x);
3049 }
3050 else if (TARGET_TOC
3051 && constant_pool_expr_p (x)
3052 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3053 {
3054 return create_TOC_reference (x);
3055 }
3056 else
3057 return NULL_RTX;
3058 }
3059
3060 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3061 We need to emit DTP-relative relocations. */
3062
3063 static void
rs6000_output_dwarf_dtprel(FILE * file,int size,rtx x)3064 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3065 {
3066 switch (size)
3067 {
3068 case 4:
3069 fputs ("\t.long\t", file);
3070 break;
3071 case 8:
3072 fputs (DOUBLE_INT_ASM_OP, file);
3073 break;
3074 default:
3075 gcc_unreachable ();
3076 }
3077 output_addr_const (file, x);
3078 fputs ("@dtprel+0x8000", file);
3079 }
3080
3081 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3082
3083 static GTY(()) rtx rs6000_tls_symbol;
3084 static rtx
rs6000_tls_get_addr(void)3085 rs6000_tls_get_addr (void)
3086 {
3087 if (!rs6000_tls_symbol)
3088 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3089
3090 return rs6000_tls_symbol;
3091 }
3092
3093 /* Construct the SYMBOL_REF for TLS GOT references. */
3094
3095 static GTY(()) rtx rs6000_got_symbol;
3096 static rtx
rs6000_got_sym(void)3097 rs6000_got_sym (void)
3098 {
3099 if (!rs6000_got_symbol)
3100 {
3101 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3102 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3103 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3104 }
3105
3106 return rs6000_got_symbol;
3107 }
3108
3109 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3110 this (thread-local) address. */
3111
3112 static rtx
rs6000_legitimize_tls_address(rtx addr,enum tls_model model)3113 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3114 {
3115 rtx dest, insn;
3116
3117 dest = gen_reg_rtx (Pmode);
3118 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3119 {
3120 rtx tlsreg;
3121
3122 if (TARGET_64BIT)
3123 {
3124 tlsreg = gen_rtx_REG (Pmode, 13);
3125 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3126 }
3127 else
3128 {
3129 tlsreg = gen_rtx_REG (Pmode, 2);
3130 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3131 }
3132 emit_insn (insn);
3133 }
3134 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3135 {
3136 rtx tlsreg, tmp;
3137
3138 tmp = gen_reg_rtx (Pmode);
3139 if (TARGET_64BIT)
3140 {
3141 tlsreg = gen_rtx_REG (Pmode, 13);
3142 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3143 }
3144 else
3145 {
3146 tlsreg = gen_rtx_REG (Pmode, 2);
3147 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3148 }
3149 emit_insn (insn);
3150 if (TARGET_64BIT)
3151 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3152 else
3153 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3154 emit_insn (insn);
3155 }
3156 else
3157 {
3158 rtx r3, got, tga, tmp1, tmp2, eqv;
3159
3160 /* We currently use relocations like @got@tlsgd for tls, which
3161 means the linker will handle allocation of tls entries, placing
3162 them in the .got section. So use a pointer to the .got section,
3163 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3164 or to secondary GOT sections used by 32-bit -fPIC. */
3165 if (TARGET_64BIT)
3166 got = gen_rtx_REG (Pmode, 2);
3167 else
3168 {
3169 if (flag_pic == 1)
3170 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3171 else
3172 {
3173 rtx gsym = rs6000_got_sym ();
3174 got = gen_reg_rtx (Pmode);
3175 if (flag_pic == 0)
3176 rs6000_emit_move (got, gsym, Pmode);
3177 else
3178 {
3179 rtx tempLR, tmp3, mem;
3180 rtx first, last;
3181
3182 tempLR = gen_reg_rtx (Pmode);
3183 tmp1 = gen_reg_rtx (Pmode);
3184 tmp2 = gen_reg_rtx (Pmode);
3185 tmp3 = gen_reg_rtx (Pmode);
3186 mem = gen_const_mem (Pmode, tmp1);
3187
3188 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3189 emit_move_insn (tmp1, tempLR);
3190 emit_move_insn (tmp2, mem);
3191 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3192 last = emit_move_insn (got, tmp3);
3193 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3194 REG_NOTES (last));
3195 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3196 REG_NOTES (first));
3197 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3198 REG_NOTES (last));
3199 }
3200 }
3201 }
3202
3203 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3204 {
3205 r3 = gen_rtx_REG (Pmode, 3);
3206 if (TARGET_64BIT)
3207 insn = gen_tls_gd_64 (r3, got, addr);
3208 else
3209 insn = gen_tls_gd_32 (r3, got, addr);
3210 start_sequence ();
3211 emit_insn (insn);
3212 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3213 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3214 insn = emit_call_insn (insn);
3215 CONST_OR_PURE_CALL_P (insn) = 1;
3216 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3217 insn = get_insns ();
3218 end_sequence ();
3219 emit_libcall_block (insn, dest, r3, addr);
3220 }
3221 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3222 {
3223 r3 = gen_rtx_REG (Pmode, 3);
3224 if (TARGET_64BIT)
3225 insn = gen_tls_ld_64 (r3, got);
3226 else
3227 insn = gen_tls_ld_32 (r3, got);
3228 start_sequence ();
3229 emit_insn (insn);
3230 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3231 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3232 insn = emit_call_insn (insn);
3233 CONST_OR_PURE_CALL_P (insn) = 1;
3234 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3235 insn = get_insns ();
3236 end_sequence ();
3237 tmp1 = gen_reg_rtx (Pmode);
3238 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3239 UNSPEC_TLSLD);
3240 emit_libcall_block (insn, tmp1, r3, eqv);
3241 if (rs6000_tls_size == 16)
3242 {
3243 if (TARGET_64BIT)
3244 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3245 else
3246 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3247 }
3248 else if (rs6000_tls_size == 32)
3249 {
3250 tmp2 = gen_reg_rtx (Pmode);
3251 if (TARGET_64BIT)
3252 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3253 else
3254 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3255 emit_insn (insn);
3256 if (TARGET_64BIT)
3257 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3258 else
3259 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3260 }
3261 else
3262 {
3263 tmp2 = gen_reg_rtx (Pmode);
3264 if (TARGET_64BIT)
3265 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3266 else
3267 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3268 emit_insn (insn);
3269 insn = gen_rtx_SET (Pmode, dest,
3270 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3271 }
3272 emit_insn (insn);
3273 }
3274 else
3275 {
3276 /* IE, or 64 bit offset LE. */
3277 tmp2 = gen_reg_rtx (Pmode);
3278 if (TARGET_64BIT)
3279 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3280 else
3281 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3282 emit_insn (insn);
3283 if (TARGET_64BIT)
3284 insn = gen_tls_tls_64 (dest, tmp2, addr);
3285 else
3286 insn = gen_tls_tls_32 (dest, tmp2, addr);
3287 emit_insn (insn);
3288 }
3289 }
3290
3291 return dest;
3292 }
3293
3294 /* Return 1 if X contains a thread-local symbol. */
3295
3296 bool
rs6000_tls_referenced_p(rtx x)3297 rs6000_tls_referenced_p (rtx x)
3298 {
3299 if (! TARGET_HAVE_TLS)
3300 return false;
3301
3302 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3303 }
3304
3305 /* Return 1 if *X is a thread-local symbol. This is the same as
3306 rs6000_tls_symbol_ref except for the type of the unused argument. */
3307
3308 static int
rs6000_tls_symbol_ref_1(rtx * x,void * data ATTRIBUTE_UNUSED)3309 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3310 {
3311 return RS6000_SYMBOL_REF_TLS_P (*x);
3312 }
3313
3314 /* The convention appears to be to define this wherever it is used.
3315 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3316 is now used here. */
3317 #ifndef REG_MODE_OK_FOR_BASE_P
3318 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3319 #endif
3320
3321 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3322 replace the input X, or the original X if no replacement is called for.
3323 The output parameter *WIN is 1 if the calling macro should goto WIN,
3324 0 if it should not.
3325
3326 For RS/6000, we wish to handle large displacements off a base
3327 register by splitting the addend across an addiu/addis and the mem insn.
3328 This cuts number of extra insns needed from 3 to 1.
3329
3330 On Darwin, we use this to generate code for floating point constants.
3331 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3332 The Darwin code is inside #if TARGET_MACHO because only then is
3333 machopic_function_base_name() defined. */
3334 rtx
rs6000_legitimize_reload_address(rtx x,enum machine_mode mode,int opnum,int type,int ind_levels ATTRIBUTE_UNUSED,int * win)3335 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3336 int opnum, int type,
3337 int ind_levels ATTRIBUTE_UNUSED, int *win)
3338 {
3339 /* We must recognize output that we have already generated ourselves. */
3340 if (GET_CODE (x) == PLUS
3341 && GET_CODE (XEXP (x, 0)) == PLUS
3342 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3343 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3344 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3345 {
3346 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3347 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3348 opnum, (enum reload_type)type);
3349 *win = 1;
3350 return x;
3351 }
3352
3353 #if TARGET_MACHO
3354 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3355 && GET_CODE (x) == LO_SUM
3356 && GET_CODE (XEXP (x, 0)) == PLUS
3357 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3358 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3359 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3360 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3361 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3362 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3363 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3364 {
3365 /* Result of previous invocation of this function on Darwin
3366 floating point constant. */
3367 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3368 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3369 opnum, (enum reload_type)type);
3370 *win = 1;
3371 return x;
3372 }
3373 #endif
3374
3375 /* Force ld/std non-word aligned offset into base register by wrapping
3376 in offset 0. */
3377 if (GET_CODE (x) == PLUS
3378 && GET_CODE (XEXP (x, 0)) == REG
3379 && REGNO (XEXP (x, 0)) < 32
3380 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3381 && GET_CODE (XEXP (x, 1)) == CONST_INT
3382 && (INTVAL (XEXP (x, 1)) & 3) != 0
3383 && !ALTIVEC_VECTOR_MODE (mode)
3384 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3385 && TARGET_POWERPC64)
3386 {
3387 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3388 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3389 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3390 opnum, (enum reload_type) type);
3391 *win = 1;
3392 return x;
3393 }
3394
3395 if (GET_CODE (x) == PLUS
3396 && GET_CODE (XEXP (x, 0)) == REG
3397 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3398 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3399 && GET_CODE (XEXP (x, 1)) == CONST_INT
3400 && !SPE_VECTOR_MODE (mode)
3401 && !(TARGET_E500_DOUBLE && (mode == DFmode
3402 || mode == DImode))
3403 && !ALTIVEC_VECTOR_MODE (mode))
3404 {
3405 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3406 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3407 HOST_WIDE_INT high
3408 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3409
3410 /* Check for 32-bit overflow. */
3411 if (high + low != val)
3412 {
3413 *win = 0;
3414 return x;
3415 }
3416
3417 /* Reload the high part into a base reg; leave the low part
3418 in the mem directly. */
3419
3420 x = gen_rtx_PLUS (GET_MODE (x),
3421 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3422 GEN_INT (high)),
3423 GEN_INT (low));
3424
3425 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3426 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3427 opnum, (enum reload_type)type);
3428 *win = 1;
3429 return x;
3430 }
3431
3432 if (GET_CODE (x) == SYMBOL_REF
3433 && !ALTIVEC_VECTOR_MODE (mode)
3434 && !SPE_VECTOR_MODE (mode)
3435 #if TARGET_MACHO
3436 && DEFAULT_ABI == ABI_DARWIN
3437 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3438 #else
3439 && DEFAULT_ABI == ABI_V4
3440 && !flag_pic
3441 #endif
3442 /* Don't do this for TFmode, since the result isn't offsettable.
3443 The same goes for DImode without 64-bit gprs and DFmode
3444 without fprs. */
3445 && mode != TFmode
3446 && (mode != DImode || TARGET_POWERPC64)
3447 && (mode != DFmode || TARGET_POWERPC64
3448 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3449 {
3450 #if TARGET_MACHO
3451 if (flag_pic)
3452 {
3453 rtx offset = gen_rtx_CONST (Pmode,
3454 gen_rtx_MINUS (Pmode, x,
3455 machopic_function_base_sym ()));
3456 x = gen_rtx_LO_SUM (GET_MODE (x),
3457 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3458 gen_rtx_HIGH (Pmode, offset)), offset);
3459 }
3460 else
3461 #endif
3462 x = gen_rtx_LO_SUM (GET_MODE (x),
3463 gen_rtx_HIGH (Pmode, x), x);
3464
3465 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3466 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3467 opnum, (enum reload_type)type);
3468 *win = 1;
3469 return x;
3470 }
3471
3472 /* Reload an offset address wrapped by an AND that represents the
3473 masking of the lower bits. Strip the outer AND and let reload
3474 convert the offset address into an indirect address. */
3475 if (TARGET_ALTIVEC
3476 && ALTIVEC_VECTOR_MODE (mode)
3477 && GET_CODE (x) == AND
3478 && GET_CODE (XEXP (x, 0)) == PLUS
3479 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3480 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3481 && GET_CODE (XEXP (x, 1)) == CONST_INT
3482 && INTVAL (XEXP (x, 1)) == -16)
3483 {
3484 x = XEXP (x, 0);
3485 *win = 1;
3486 return x;
3487 }
3488
3489 if (TARGET_TOC
3490 && constant_pool_expr_p (x)
3491 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3492 {
3493 x = create_TOC_reference (x);
3494 *win = 1;
3495 return x;
3496 }
3497 *win = 0;
3498 return x;
3499 }
3500
3501 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3502 that is a valid memory address for an instruction.
3503 The MODE argument is the machine mode for the MEM expression
3504 that wants to use this address.
3505
3506 On the RS/6000, there are four valid address: a SYMBOL_REF that
3507 refers to a constant pool entry of an address (or the sum of it
3508 plus a constant), a short (16-bit signed) constant plus a register,
3509 the sum of two registers, or a register indirect, possibly with an
3510 auto-increment. For DFmode and DImode with a constant plus register,
3511 we must ensure that both words are addressable or PowerPC64 with offset
3512 word aligned.
3513
3514 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3515 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3516 adjacent memory cells are accessed by adding word-sized offsets
3517 during assembly output. */
3518 int
rs6000_legitimate_address(enum machine_mode mode,rtx x,int reg_ok_strict)3519 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3520 {
3521 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3522 if (TARGET_ALTIVEC
3523 && ALTIVEC_VECTOR_MODE (mode)
3524 && GET_CODE (x) == AND
3525 && GET_CODE (XEXP (x, 1)) == CONST_INT
3526 && INTVAL (XEXP (x, 1)) == -16)
3527 x = XEXP (x, 0);
3528
3529 if (RS6000_SYMBOL_REF_TLS_P (x))
3530 return 0;
3531 if (legitimate_indirect_address_p (x, reg_ok_strict))
3532 return 1;
3533 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3534 && !ALTIVEC_VECTOR_MODE (mode)
3535 && !SPE_VECTOR_MODE (mode)
3536 && mode != TFmode
3537 /* Restrict addressing for DI because of our SUBREG hackery. */
3538 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3539 && TARGET_UPDATE
3540 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3541 return 1;
3542 if (legitimate_small_data_p (mode, x))
3543 return 1;
3544 if (legitimate_constant_pool_address_p (x))
3545 return 1;
3546 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3547 if (! reg_ok_strict
3548 && GET_CODE (x) == PLUS
3549 && GET_CODE (XEXP (x, 0)) == REG
3550 && (XEXP (x, 0) == virtual_stack_vars_rtx
3551 || XEXP (x, 0) == arg_pointer_rtx)
3552 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3553 return 1;
3554 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3555 return 1;
3556 if (mode != TImode
3557 && mode != TFmode
3558 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3559 || TARGET_POWERPC64
3560 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3561 && (TARGET_POWERPC64 || mode != DImode)
3562 && legitimate_indexed_address_p (x, reg_ok_strict))
3563 return 1;
3564 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3565 return 1;
3566 return 0;
3567 }
3568
3569 /* Go to LABEL if ADDR (a legitimate address expression)
3570 has an effect that depends on the machine mode it is used for.
3571
3572 On the RS/6000 this is true of all integral offsets (since AltiVec
3573 modes don't allow them) or is a pre-increment or decrement.
3574
3575 ??? Except that due to conceptual problems in offsettable_address_p
3576 we can't really report the problems of integral offsets. So leave
3577 this assuming that the adjustable offset must be valid for the
3578 sub-words of a TFmode operand, which is what we had before. */
3579
3580 bool
rs6000_mode_dependent_address(rtx addr)3581 rs6000_mode_dependent_address (rtx addr)
3582 {
3583 switch (GET_CODE (addr))
3584 {
3585 case PLUS:
3586 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3587 {
3588 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3589 return val + 12 + 0x8000 >= 0x10000;
3590 }
3591 break;
3592
3593 case LO_SUM:
3594 return true;
3595
3596 case PRE_INC:
3597 case PRE_DEC:
3598 return TARGET_UPDATE;
3599
3600 default:
3601 break;
3602 }
3603
3604 return false;
3605 }
3606
3607 /* More elaborate version of recog's offsettable_memref_p predicate
3608 that works around the ??? note of rs6000_mode_dependent_address.
3609 In particular it accepts
3610
3611 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3612
3613 in 32-bit mode, that the recog predicate rejects. */
3614
3615 bool
rs6000_offsettable_memref_p(rtx op)3616 rs6000_offsettable_memref_p (rtx op)
3617 {
3618 if (!MEM_P (op))
3619 return false;
3620
3621 /* First mimic offsettable_memref_p. */
3622 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3623 return true;
3624
3625 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3626 the latter predicate knows nothing about the mode of the memory
3627 reference and, therefore, assumes that it is the largest supported
3628 mode (TFmode). As a consequence, legitimate offsettable memory
3629 references are rejected. rs6000_legitimate_offset_address_p contains
3630 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3631 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3632 }
3633
3634 /* Return number of consecutive hard regs needed starting at reg REGNO
3635 to hold something of mode MODE.
3636 This is ordinarily the length in words of a value of mode MODE
3637 but can be less for certain modes in special long registers.
3638
3639 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3640 scalar instructions. The upper 32 bits are only available to the
3641 SIMD instructions.
3642
3643 POWER and PowerPC GPRs hold 32 bits worth;
3644 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3645
3646 int
rs6000_hard_regno_nregs(int regno,enum machine_mode mode)3647 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3648 {
3649 if (FP_REGNO_P (regno))
3650 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3651
3652 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3653 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3654
3655 if (ALTIVEC_REGNO_P (regno))
3656 return
3657 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3658
3659 /* The value returned for SCmode in the E500 double case is 2 for
3660 ABI compatibility; storing an SCmode value in a single register
3661 would require function_arg and rs6000_spe_function_arg to handle
3662 SCmode so as to pass the value correctly in a pair of
3663 registers. */
3664 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
3665 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3666
3667 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3668 }
3669
3670 /* Change register usage conditional on target flags. */
3671 void
rs6000_conditional_register_usage(void)3672 rs6000_conditional_register_usage (void)
3673 {
3674 int i;
3675
3676 /* Set MQ register fixed (already call_used) if not POWER
3677 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3678 be allocated. */
3679 if (! TARGET_POWER)
3680 fixed_regs[64] = 1;
3681
3682 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3683 if (TARGET_64BIT)
3684 fixed_regs[13] = call_used_regs[13]
3685 = call_really_used_regs[13] = 1;
3686
3687 /* Conditionally disable FPRs. */
3688 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3689 for (i = 32; i < 64; i++)
3690 fixed_regs[i] = call_used_regs[i]
3691 = call_really_used_regs[i] = 1;
3692
3693 /* The TOC register is not killed across calls in a way that is
3694 visible to the compiler. */
3695 if (DEFAULT_ABI == ABI_AIX)
3696 call_really_used_regs[2] = 0;
3697
3698 if (DEFAULT_ABI == ABI_V4
3699 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3700 && flag_pic == 2)
3701 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3702
3703 if (DEFAULT_ABI == ABI_V4
3704 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3705 && flag_pic == 1)
3706 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3707 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3708 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3709
3710 if (DEFAULT_ABI == ABI_DARWIN
3711 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3712 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3713 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3714 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3715
3716 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3717 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3718 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3719
3720 if (TARGET_ALTIVEC)
3721 global_regs[VSCR_REGNO] = 1;
3722
3723 if (TARGET_SPE)
3724 {
3725 global_regs[SPEFSCR_REGNO] = 1;
3726 fixed_regs[FIXED_SCRATCH]
3727 = call_used_regs[FIXED_SCRATCH]
3728 = call_really_used_regs[FIXED_SCRATCH] = 1;
3729 }
3730
3731 if (! TARGET_ALTIVEC)
3732 {
3733 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3734 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3735 call_really_used_regs[VRSAVE_REGNO] = 1;
3736 }
3737
3738 if (TARGET_ALTIVEC_ABI)
3739 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3740 call_used_regs[i] = call_really_used_regs[i] = 1;
3741 }
3742
3743 /* Try to output insns to set TARGET equal to the constant C if it can
3744 be done in less than N insns. Do all computations in MODE.
3745 Returns the place where the output has been placed if it can be
3746 done and the insns have been emitted. If it would take more than N
3747 insns, zero is returned and no insns and emitted. */
3748
3749 rtx
rs6000_emit_set_const(rtx dest,enum machine_mode mode,rtx source,int n ATTRIBUTE_UNUSED)3750 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3751 rtx source, int n ATTRIBUTE_UNUSED)
3752 {
3753 rtx result, insn, set;
3754 HOST_WIDE_INT c0, c1;
3755
3756 switch (mode)
3757 {
3758 case QImode:
3759 case HImode:
3760 if (dest == NULL)
3761 dest = gen_reg_rtx (mode);
3762 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3763 return dest;
3764
3765 case SImode:
3766 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3767
3768 emit_insn (gen_rtx_SET (VOIDmode, result,
3769 GEN_INT (INTVAL (source)
3770 & (~ (HOST_WIDE_INT) 0xffff))));
3771 emit_insn (gen_rtx_SET (VOIDmode, dest,
3772 gen_rtx_IOR (SImode, result,
3773 GEN_INT (INTVAL (source) & 0xffff))));
3774 result = dest;
3775 break;
3776
3777 case DImode:
3778 switch (GET_CODE (source))
3779 {
3780 case CONST_INT:
3781 c0 = INTVAL (source);
3782 c1 = -(c0 < 0);
3783 break;
3784
3785 case CONST_DOUBLE:
3786 #if HOST_BITS_PER_WIDE_INT >= 64
3787 c0 = CONST_DOUBLE_LOW (source);
3788 c1 = -(c0 < 0);
3789 #else
3790 c0 = CONST_DOUBLE_LOW (source);
3791 c1 = CONST_DOUBLE_HIGH (source);
3792 #endif
3793 break;
3794
3795 default:
3796 gcc_unreachable ();
3797 }
3798
3799 result = rs6000_emit_set_long_const (dest, c0, c1);
3800 break;
3801
3802 default:
3803 gcc_unreachable ();
3804 }
3805
3806 insn = get_last_insn ();
3807 set = single_set (insn);
3808 if (! CONSTANT_P (SET_SRC (set)))
3809 set_unique_reg_note (insn, REG_EQUAL, source);
3810
3811 return result;
3812 }
3813
3814 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3815 fall back to a straight forward decomposition. We do this to avoid
3816 exponential run times encountered when looking for longer sequences
3817 with rs6000_emit_set_const. */
3818 static rtx
rs6000_emit_set_long_const(rtx dest,HOST_WIDE_INT c1,HOST_WIDE_INT c2)3819 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3820 {
3821 if (!TARGET_POWERPC64)
3822 {
3823 rtx operand1, operand2;
3824
3825 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3826 DImode);
3827 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3828 DImode);
3829 emit_move_insn (operand1, GEN_INT (c1));
3830 emit_move_insn (operand2, GEN_INT (c2));
3831 }
3832 else
3833 {
3834 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3835
3836 ud1 = c1 & 0xffff;
3837 ud2 = (c1 & 0xffff0000) >> 16;
3838 #if HOST_BITS_PER_WIDE_INT >= 64
3839 c2 = c1 >> 32;
3840 #endif
3841 ud3 = c2 & 0xffff;
3842 ud4 = (c2 & 0xffff0000) >> 16;
3843
3844 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3845 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3846 {
3847 if (ud1 & 0x8000)
3848 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3849 else
3850 emit_move_insn (dest, GEN_INT (ud1));
3851 }
3852
3853 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3854 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3855 {
3856 if (ud2 & 0x8000)
3857 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3858 - 0x80000000));
3859 else
3860 emit_move_insn (dest, GEN_INT (ud2 << 16));
3861 if (ud1 != 0)
3862 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3863 }
3864 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3865 || (ud4 == 0 && ! (ud3 & 0x8000)))
3866 {
3867 if (ud3 & 0x8000)
3868 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3869 - 0x80000000));
3870 else
3871 emit_move_insn (dest, GEN_INT (ud3 << 16));
3872
3873 if (ud2 != 0)
3874 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3875 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3876 if (ud1 != 0)
3877 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3878 }
3879 else
3880 {
3881 if (ud4 & 0x8000)
3882 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3883 - 0x80000000));
3884 else
3885 emit_move_insn (dest, GEN_INT (ud4 << 16));
3886
3887 if (ud3 != 0)
3888 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3889
3890 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3891 if (ud2 != 0)
3892 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3893 GEN_INT (ud2 << 16)));
3894 if (ud1 != 0)
3895 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3896 }
3897 }
3898 return dest;
3899 }
3900
3901 /* Helper for the following. Get rid of [r+r] memory refs
3902 in cases where it won't work (TImode, TFmode). */
3903
3904 static void
rs6000_eliminate_indexed_memrefs(rtx operands[2])3905 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3906 {
3907 if (GET_CODE (operands[0]) == MEM
3908 && GET_CODE (XEXP (operands[0], 0)) != REG
3909 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3910 && ! reload_in_progress)
3911 operands[0]
3912 = replace_equiv_address (operands[0],
3913 copy_addr_to_reg (XEXP (operands[0], 0)));
3914
3915 if (GET_CODE (operands[1]) == MEM
3916 && GET_CODE (XEXP (operands[1], 0)) != REG
3917 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3918 && ! reload_in_progress)
3919 operands[1]
3920 = replace_equiv_address (operands[1],
3921 copy_addr_to_reg (XEXP (operands[1], 0)));
3922 }
3923
3924 /* Emit a move from SOURCE to DEST in mode MODE. */
3925 void
rs6000_emit_move(rtx dest,rtx source,enum machine_mode mode)3926 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3927 {
3928 rtx operands[2];
3929 operands[0] = dest;
3930 operands[1] = source;
3931
3932 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3933 if (GET_CODE (operands[1]) == CONST_DOUBLE
3934 && ! FLOAT_MODE_P (mode)
3935 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3936 {
3937 /* FIXME. This should never happen. */
3938 /* Since it seems that it does, do the safe thing and convert
3939 to a CONST_INT. */
3940 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3941 }
3942 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3943 || FLOAT_MODE_P (mode)
3944 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3945 || CONST_DOUBLE_LOW (operands[1]) < 0)
3946 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3947 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3948
3949 /* Check if GCC is setting up a block move that will end up using FP
3950 registers as temporaries. We must make sure this is acceptable. */
3951 if (GET_CODE (operands[0]) == MEM
3952 && GET_CODE (operands[1]) == MEM
3953 && mode == DImode
3954 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3955 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3956 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3957 ? 32 : MEM_ALIGN (operands[0])))
3958 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3959 ? 32
3960 : MEM_ALIGN (operands[1]))))
3961 && ! MEM_VOLATILE_P (operands [0])
3962 && ! MEM_VOLATILE_P (operands [1]))
3963 {
3964 emit_move_insn (adjust_address (operands[0], SImode, 0),
3965 adjust_address (operands[1], SImode, 0));
3966 emit_move_insn (adjust_address (operands[0], SImode, 4),
3967 adjust_address (operands[1], SImode, 4));
3968 return;
3969 }
3970
3971 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3972 && !gpc_reg_operand (operands[1], mode))
3973 operands[1] = force_reg (mode, operands[1]);
3974
3975 if (mode == SFmode && ! TARGET_POWERPC
3976 && TARGET_HARD_FLOAT && TARGET_FPRS
3977 && GET_CODE (operands[0]) == MEM)
3978 {
3979 int regnum;
3980
3981 if (reload_in_progress || reload_completed)
3982 regnum = true_regnum (operands[1]);
3983 else if (GET_CODE (operands[1]) == REG)
3984 regnum = REGNO (operands[1]);
3985 else
3986 regnum = -1;
3987
3988 /* If operands[1] is a register, on POWER it may have
3989 double-precision data in it, so truncate it to single
3990 precision. */
3991 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3992 {
3993 rtx newreg;
3994 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3995 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3996 operands[1] = newreg;
3997 }
3998 }
3999
4000 /* Recognize the case where operand[1] is a reference to thread-local
4001 data and load its address to a register. */
4002 if (rs6000_tls_referenced_p (operands[1]))
4003 {
4004 enum tls_model model;
4005 rtx tmp = operands[1];
4006 rtx addend = NULL;
4007
4008 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4009 {
4010 addend = XEXP (XEXP (tmp, 0), 1);
4011 tmp = XEXP (XEXP (tmp, 0), 0);
4012 }
4013
4014 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4015 model = SYMBOL_REF_TLS_MODEL (tmp);
4016 gcc_assert (model != 0);
4017
4018 tmp = rs6000_legitimize_tls_address (tmp, model);
4019 if (addend)
4020 {
4021 tmp = gen_rtx_PLUS (mode, tmp, addend);
4022 tmp = force_operand (tmp, operands[0]);
4023 }
4024 operands[1] = tmp;
4025 }
4026
4027 /* Handle the case where reload calls us with an invalid address. */
4028 if (reload_in_progress && mode == Pmode
4029 && (! general_operand (operands[1], mode)
4030 || ! nonimmediate_operand (operands[0], mode)))
4031 goto emit_set;
4032
4033 /* 128-bit constant floating-point values on Darwin should really be
4034 loaded as two parts. */
4035 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4036 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4037 {
4038 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4039 know how to get a DFmode SUBREG of a TFmode. */
4040 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4041 simplify_gen_subreg (DImode, operands[1], mode, 0),
4042 DImode);
4043 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4044 GET_MODE_SIZE (DImode)),
4045 simplify_gen_subreg (DImode, operands[1], mode,
4046 GET_MODE_SIZE (DImode)),
4047 DImode);
4048 return;
4049 }
4050
4051 /* FIXME: In the long term, this switch statement should go away
4052 and be replaced by a sequence of tests based on things like
4053 mode == Pmode. */
4054 switch (mode)
4055 {
4056 case HImode:
4057 case QImode:
4058 if (CONSTANT_P (operands[1])
4059 && GET_CODE (operands[1]) != CONST_INT)
4060 operands[1] = force_const_mem (mode, operands[1]);
4061 break;
4062
4063 case TFmode:
4064 rs6000_eliminate_indexed_memrefs (operands);
4065 /* fall through */
4066
4067 case DFmode:
4068 case SFmode:
4069 if (CONSTANT_P (operands[1])
4070 && ! easy_fp_constant (operands[1], mode))
4071 operands[1] = force_const_mem (mode, operands[1]);
4072 break;
4073
4074 case V16QImode:
4075 case V8HImode:
4076 case V4SFmode:
4077 case V4SImode:
4078 case V4HImode:
4079 case V2SFmode:
4080 case V2SImode:
4081 case V1DImode:
4082 if (CONSTANT_P (operands[1])
4083 && !easy_vector_constant (operands[1], mode))
4084 operands[1] = force_const_mem (mode, operands[1]);
4085 break;
4086
4087 case SImode:
4088 case DImode:
4089 /* Use default pattern for address of ELF small data */
4090 if (TARGET_ELF
4091 && mode == Pmode
4092 && DEFAULT_ABI == ABI_V4
4093 && (GET_CODE (operands[1]) == SYMBOL_REF
4094 || GET_CODE (operands[1]) == CONST)
4095 && small_data_operand (operands[1], mode))
4096 {
4097 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4098 return;
4099 }
4100
4101 if (DEFAULT_ABI == ABI_V4
4102 && mode == Pmode && mode == SImode
4103 && flag_pic == 1 && got_operand (operands[1], mode))
4104 {
4105 emit_insn (gen_movsi_got (operands[0], operands[1]));
4106 return;
4107 }
4108
4109 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4110 && TARGET_NO_TOC
4111 && ! flag_pic
4112 && mode == Pmode
4113 && CONSTANT_P (operands[1])
4114 && GET_CODE (operands[1]) != HIGH
4115 && GET_CODE (operands[1]) != CONST_INT)
4116 {
4117 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4118
4119 /* If this is a function address on -mcall-aixdesc,
4120 convert it to the address of the descriptor. */
4121 if (DEFAULT_ABI == ABI_AIX
4122 && GET_CODE (operands[1]) == SYMBOL_REF
4123 && XSTR (operands[1], 0)[0] == '.')
4124 {
4125 const char *name = XSTR (operands[1], 0);
4126 rtx new_ref;
4127 while (*name == '.')
4128 name++;
4129 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4130 CONSTANT_POOL_ADDRESS_P (new_ref)
4131 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4132 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4133 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4134 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4135 operands[1] = new_ref;
4136 }
4137
4138 if (DEFAULT_ABI == ABI_DARWIN)
4139 {
4140 #if TARGET_MACHO
4141 if (MACHO_DYNAMIC_NO_PIC_P)
4142 {
4143 /* Take care of any required data indirection. */
4144 operands[1] = rs6000_machopic_legitimize_pic_address (
4145 operands[1], mode, operands[0]);
4146 if (operands[0] != operands[1])
4147 emit_insn (gen_rtx_SET (VOIDmode,
4148 operands[0], operands[1]));
4149 return;
4150 }
4151 #endif
4152 emit_insn (gen_macho_high (target, operands[1]));
4153 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4154 return;
4155 }
4156
4157 emit_insn (gen_elf_high (target, operands[1]));
4158 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4159 return;
4160 }
4161
4162 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4163 and we have put it in the TOC, we just need to make a TOC-relative
4164 reference to it. */
4165 if (TARGET_TOC
4166 && GET_CODE (operands[1]) == SYMBOL_REF
4167 && constant_pool_expr_p (operands[1])
4168 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4169 get_pool_mode (operands[1])))
4170 {
4171 operands[1] = create_TOC_reference (operands[1]);
4172 }
4173 else if (mode == Pmode
4174 && CONSTANT_P (operands[1])
4175 && ((GET_CODE (operands[1]) != CONST_INT
4176 && ! easy_fp_constant (operands[1], mode))
4177 || (GET_CODE (operands[1]) == CONST_INT
4178 && num_insns_constant (operands[1], mode) > 2)
4179 || (GET_CODE (operands[0]) == REG
4180 && FP_REGNO_P (REGNO (operands[0]))))
4181 && GET_CODE (operands[1]) != HIGH
4182 && ! legitimate_constant_pool_address_p (operands[1])
4183 && ! toc_relative_expr_p (operands[1]))
4184 {
4185 /* Emit a USE operation so that the constant isn't deleted if
4186 expensive optimizations are turned on because nobody
4187 references it. This should only be done for operands that
4188 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4189 This should not be done for operands that contain LABEL_REFs.
4190 For now, we just handle the obvious case. */
4191 if (GET_CODE (operands[1]) != LABEL_REF)
4192 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4193
4194 #if TARGET_MACHO
4195 /* Darwin uses a special PIC legitimizer. */
4196 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4197 {
4198 operands[1] =
4199 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4200 operands[0]);
4201 if (operands[0] != operands[1])
4202 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4203 return;
4204 }
4205 #endif
4206
4207 /* If we are to limit the number of things we put in the TOC and
4208 this is a symbol plus a constant we can add in one insn,
4209 just put the symbol in the TOC and add the constant. Don't do
4210 this if reload is in progress. */
4211 if (GET_CODE (operands[1]) == CONST
4212 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4213 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4214 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4215 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4216 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4217 && ! side_effects_p (operands[0]))
4218 {
4219 rtx sym =
4220 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4221 rtx other = XEXP (XEXP (operands[1], 0), 1);
4222
4223 sym = force_reg (mode, sym);
4224 if (mode == SImode)
4225 emit_insn (gen_addsi3 (operands[0], sym, other));
4226 else
4227 emit_insn (gen_adddi3 (operands[0], sym, other));
4228 return;
4229 }
4230
4231 operands[1] = force_const_mem (mode, operands[1]);
4232
4233 if (TARGET_TOC
4234 && constant_pool_expr_p (XEXP (operands[1], 0))
4235 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4236 get_pool_constant (XEXP (operands[1], 0)),
4237 get_pool_mode (XEXP (operands[1], 0))))
4238 {
4239 operands[1]
4240 = gen_const_mem (mode,
4241 create_TOC_reference (XEXP (operands[1], 0)));
4242 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4243 }
4244 }
4245 break;
4246
4247 case TImode:
4248 rs6000_eliminate_indexed_memrefs (operands);
4249
4250 if (TARGET_POWER)
4251 {
4252 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4253 gen_rtvec (2,
4254 gen_rtx_SET (VOIDmode,
4255 operands[0], operands[1]),
4256 gen_rtx_CLOBBER (VOIDmode,
4257 gen_rtx_SCRATCH (SImode)))));
4258 return;
4259 }
4260 break;
4261
4262 default:
4263 gcc_unreachable ();
4264 }
4265
4266 /* Above, we may have called force_const_mem which may have returned
4267 an invalid address. If we can, fix this up; otherwise, reload will
4268 have to deal with it. */
4269 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4270 operands[1] = validize_mem (operands[1]);
4271
4272 emit_set:
4273 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4274 }
4275
4276 /* Nonzero if we can use a floating-point register to pass this arg. */
4277 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4278 (SCALAR_FLOAT_MODE_P (MODE) \
4279 && !DECIMAL_FLOAT_MODE_P (MODE) \
4280 && (CUM)->fregno <= FP_ARG_MAX_REG \
4281 && TARGET_HARD_FLOAT && TARGET_FPRS)
4282
4283 /* Nonzero if we can use an AltiVec register to pass this arg. */
4284 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4285 (ALTIVEC_VECTOR_MODE (MODE) \
4286 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4287 && TARGET_ALTIVEC_ABI \
4288 && (NAMED))
4289
4290 /* Return a nonzero value to say to return the function value in
4291 memory, just as large structures are always returned. TYPE will be
4292 the data type of the value, and FNTYPE will be the type of the
4293 function doing the returning, or @code{NULL} for libcalls.
4294
4295 The AIX ABI for the RS/6000 specifies that all structures are
4296 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4297 specifies that structures <= 8 bytes are returned in r3/r4, but a
4298 draft put them in memory, and GCC used to implement the draft
4299 instead of the final standard. Therefore, aix_struct_return
4300 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4301 compatibility can change DRAFT_V4_STRUCT_RET to override the
4302 default, and -m switches get the final word. See
4303 rs6000_override_options for more details.
4304
4305 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4306 long double support is enabled. These values are returned in memory.
4307
4308 int_size_in_bytes returns -1 for variable size objects, which go in
4309 memory always. The cast to unsigned makes -1 > 8. */
4310
4311 static bool
rs6000_return_in_memory(tree type,tree fntype ATTRIBUTE_UNUSED)4312 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4313 {
4314 /* In the darwin64 abi, try to use registers for larger structs
4315 if possible. */
4316 if (rs6000_darwin64_abi
4317 && TREE_CODE (type) == RECORD_TYPE
4318 && int_size_in_bytes (type) > 0)
4319 {
4320 CUMULATIVE_ARGS valcum;
4321 rtx valret;
4322
4323 valcum.words = 0;
4324 valcum.fregno = FP_ARG_MIN_REG;
4325 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4326 /* Do a trial code generation as if this were going to be passed
4327 as an argument; if any part goes in memory, we return NULL. */
4328 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4329 if (valret)
4330 return false;
4331 /* Otherwise fall through to more conventional ABI rules. */
4332 }
4333
4334 if (AGGREGATE_TYPE_P (type)
4335 && (aix_struct_return
4336 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4337 return true;
4338
4339 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4340 modes only exist for GCC vector types if -maltivec. */
4341 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4342 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4343 return false;
4344
4345 /* Return synthetic vectors in memory. */
4346 if (TREE_CODE (type) == VECTOR_TYPE
4347 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4348 {
4349 static bool warned_for_return_big_vectors = false;
4350 if (!warned_for_return_big_vectors)
4351 {
4352 warning (0, "GCC vector returned by reference: "
4353 "non-standard ABI extension with no compatibility guarantee");
4354 warned_for_return_big_vectors = true;
4355 }
4356 return true;
4357 }
4358
4359 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4360 return true;
4361
4362 return false;
4363 }
4364
4365 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4366 for a call to a function whose data type is FNTYPE.
4367 For a library call, FNTYPE is 0.
4368
4369 For incoming args we set the number of arguments in the prototype large
4370 so we never return a PARALLEL. */
4371
4372 void
init_cumulative_args(CUMULATIVE_ARGS * cum,tree fntype,rtx libname ATTRIBUTE_UNUSED,int incoming,int libcall,int n_named_args)4373 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4374 rtx libname ATTRIBUTE_UNUSED, int incoming,
4375 int libcall, int n_named_args)
4376 {
4377 static CUMULATIVE_ARGS zero_cumulative;
4378
4379 *cum = zero_cumulative;
4380 cum->words = 0;
4381 cum->fregno = FP_ARG_MIN_REG;
4382 cum->vregno = ALTIVEC_ARG_MIN_REG;
4383 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4384 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4385 ? CALL_LIBCALL : CALL_NORMAL);
4386 cum->sysv_gregno = GP_ARG_MIN_REG;
4387 cum->stdarg = fntype
4388 && (TYPE_ARG_TYPES (fntype) != 0
4389 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4390 != void_type_node));
4391
4392 cum->nargs_prototype = 0;
4393 if (incoming || cum->prototype)
4394 cum->nargs_prototype = n_named_args;
4395
4396 /* Check for a longcall attribute. */
4397 if ((!fntype && rs6000_default_long_calls)
4398 || (fntype
4399 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4400 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4401 cum->call_cookie |= CALL_LONG;
4402
4403 if (TARGET_DEBUG_ARG)
4404 {
4405 fprintf (stderr, "\ninit_cumulative_args:");
4406 if (fntype)
4407 {
4408 tree ret_type = TREE_TYPE (fntype);
4409 fprintf (stderr, " ret code = %s,",
4410 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4411 }
4412
4413 if (cum->call_cookie & CALL_LONG)
4414 fprintf (stderr, " longcall,");
4415
4416 fprintf (stderr, " proto = %d, nargs = %d\n",
4417 cum->prototype, cum->nargs_prototype);
4418 }
4419
4420 if (fntype
4421 && !TARGET_ALTIVEC
4422 && TARGET_ALTIVEC_ABI
4423 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4424 {
4425 error ("cannot return value in vector register because"
4426 " altivec instructions are disabled, use -maltivec"
4427 " to enable them");
4428 }
4429 }
4430
4431 /* Return true if TYPE must be passed on the stack and not in registers. */
4432
4433 static bool
rs6000_must_pass_in_stack(enum machine_mode mode,tree type)4434 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4435 {
4436 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4437 return must_pass_in_stack_var_size (mode, type);
4438 else
4439 return must_pass_in_stack_var_size_or_pad (mode, type);
4440 }
4441
4442 /* If defined, a C expression which determines whether, and in which
4443 direction, to pad out an argument with extra space. The value
4444 should be of type `enum direction': either `upward' to pad above
4445 the argument, `downward' to pad below, or `none' to inhibit
4446 padding.
4447
4448 For the AIX ABI structs are always stored left shifted in their
4449 argument slot. */
4450
4451 enum direction
function_arg_padding(enum machine_mode mode,tree type)4452 function_arg_padding (enum machine_mode mode, tree type)
4453 {
4454 #ifndef AGGREGATE_PADDING_FIXED
4455 #define AGGREGATE_PADDING_FIXED 0
4456 #endif
4457 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4458 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4459 #endif
4460
4461 if (!AGGREGATE_PADDING_FIXED)
4462 {
4463 /* GCC used to pass structures of the same size as integer types as
4464 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4465 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4466 passed padded downward, except that -mstrict-align further
4467 muddied the water in that multi-component structures of 2 and 4
4468 bytes in size were passed padded upward.
4469
4470 The following arranges for best compatibility with previous
4471 versions of gcc, but removes the -mstrict-align dependency. */
4472 if (BYTES_BIG_ENDIAN)
4473 {
4474 HOST_WIDE_INT size = 0;
4475
4476 if (mode == BLKmode)
4477 {
4478 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4479 size = int_size_in_bytes (type);
4480 }
4481 else
4482 size = GET_MODE_SIZE (mode);
4483
4484 if (size == 1 || size == 2 || size == 4)
4485 return downward;
4486 }
4487 return upward;
4488 }
4489
4490 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4491 {
4492 if (type != 0 && AGGREGATE_TYPE_P (type))
4493 return upward;
4494 }
4495
4496 /* Fall back to the default. */
4497 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4498 }
4499
4500 /* If defined, a C expression that gives the alignment boundary, in bits,
4501 of an argument with the specified mode and type. If it is not defined,
4502 PARM_BOUNDARY is used for all arguments.
4503
4504 V.4 wants long longs and doubles to be double word aligned. Just
4505 testing the mode size is a boneheaded way to do this as it means
4506 that other types such as complex int are also double word aligned.
4507 However, we're stuck with this because changing the ABI might break
4508 existing library interfaces.
4509
4510 Doubleword align SPE vectors.
4511 Quadword align Altivec vectors.
4512 Quadword align large synthetic vector types. */
4513
4514 int
function_arg_boundary(enum machine_mode mode,tree type)4515 function_arg_boundary (enum machine_mode mode, tree type)
4516 {
4517 if (DEFAULT_ABI == ABI_V4
4518 && (GET_MODE_SIZE (mode) == 8
4519 || (TARGET_HARD_FLOAT
4520 && TARGET_FPRS
4521 && mode == TFmode)))
4522 return 64;
4523 else if (SPE_VECTOR_MODE (mode)
4524 || (type && TREE_CODE (type) == VECTOR_TYPE
4525 && int_size_in_bytes (type) >= 8
4526 && int_size_in_bytes (type) < 16))
4527 return 64;
4528 else if (ALTIVEC_VECTOR_MODE (mode)
4529 || (type && TREE_CODE (type) == VECTOR_TYPE
4530 && int_size_in_bytes (type) >= 16))
4531 return 128;
4532 else if (rs6000_darwin64_abi && mode == BLKmode
4533 && type && TYPE_ALIGN (type) > 64)
4534 return 128;
4535 else
4536 return PARM_BOUNDARY;
4537 }
4538
4539 /* For a function parm of MODE and TYPE, return the starting word in
4540 the parameter area. NWORDS of the parameter area are already used. */
4541
4542 static unsigned int
rs6000_parm_start(enum machine_mode mode,tree type,unsigned int nwords)4543 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4544 {
4545 unsigned int align;
4546 unsigned int parm_offset;
4547
4548 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4549 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4550 return nwords + (-(parm_offset + nwords) & align);
4551 }
4552
4553 /* Compute the size (in words) of a function argument. */
4554
4555 static unsigned long
rs6000_arg_size(enum machine_mode mode,tree type)4556 rs6000_arg_size (enum machine_mode mode, tree type)
4557 {
4558 unsigned long size;
4559
4560 if (mode != BLKmode)
4561 size = GET_MODE_SIZE (mode);
4562 else
4563 size = int_size_in_bytes (type);
4564
4565 if (TARGET_32BIT)
4566 return (size + 3) >> 2;
4567 else
4568 return (size + 7) >> 3;
4569 }
4570
4571 /* Use this to flush pending int fields. */
4572
4573 static void
rs6000_darwin64_record_arg_advance_flush(CUMULATIVE_ARGS * cum,HOST_WIDE_INT bitpos)4574 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4575 HOST_WIDE_INT bitpos)
4576 {
4577 unsigned int startbit, endbit;
4578 int intregs, intoffset;
4579 enum machine_mode mode;
4580
4581 if (cum->intoffset == -1)
4582 return;
4583
4584 intoffset = cum->intoffset;
4585 cum->intoffset = -1;
4586
4587 if (intoffset % BITS_PER_WORD != 0)
4588 {
4589 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4590 MODE_INT, 0);
4591 if (mode == BLKmode)
4592 {
4593 /* We couldn't find an appropriate mode, which happens,
4594 e.g., in packed structs when there are 3 bytes to load.
4595 Back intoffset back to the beginning of the word in this
4596 case. */
4597 intoffset = intoffset & -BITS_PER_WORD;
4598 }
4599 }
4600
4601 startbit = intoffset & -BITS_PER_WORD;
4602 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4603 intregs = (endbit - startbit) / BITS_PER_WORD;
4604 cum->words += intregs;
4605 }
4606
4607 /* The darwin64 ABI calls for us to recurse down through structs,
4608 looking for elements passed in registers. Unfortunately, we have
4609 to track int register count here also because of misalignments
4610 in powerpc alignment mode. */
4611
4612 static void
rs6000_darwin64_record_arg_advance_recurse(CUMULATIVE_ARGS * cum,tree type,HOST_WIDE_INT startbitpos)4613 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4614 tree type,
4615 HOST_WIDE_INT startbitpos)
4616 {
4617 tree f;
4618
4619 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4620 if (TREE_CODE (f) == FIELD_DECL)
4621 {
4622 HOST_WIDE_INT bitpos = startbitpos;
4623 tree ftype = TREE_TYPE (f);
4624 enum machine_mode mode;
4625 if (ftype == error_mark_node)
4626 continue;
4627 mode = TYPE_MODE (ftype);
4628
4629 if (DECL_SIZE (f) != 0
4630 && host_integerp (bit_position (f), 1))
4631 bitpos += int_bit_position (f);
4632
4633 /* ??? FIXME: else assume zero offset. */
4634
4635 if (TREE_CODE (ftype) == RECORD_TYPE)
4636 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4637 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4638 {
4639 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4640 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4641 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4642 }
4643 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4644 {
4645 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4646 cum->vregno++;
4647 cum->words += 2;
4648 }
4649 else if (cum->intoffset == -1)
4650 cum->intoffset = bitpos;
4651 }
4652 }
4653
4654 /* Update the data in CUM to advance over an argument
4655 of mode MODE and data type TYPE.
4656 (TYPE is null for libcalls where that information may not be available.)
4657
4658 Note that for args passed by reference, function_arg will be called
4659 with MODE and TYPE set to that of the pointer to the arg, not the arg
4660 itself. */
4661
4662 void
function_arg_advance(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named,int depth)4663 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4664 tree type, int named, int depth)
4665 {
4666 int size;
4667
4668 /* Only tick off an argument if we're not recursing. */
4669 if (depth == 0)
4670 cum->nargs_prototype--;
4671
4672 if (TARGET_ALTIVEC_ABI
4673 && (ALTIVEC_VECTOR_MODE (mode)
4674 || (type && TREE_CODE (type) == VECTOR_TYPE
4675 && int_size_in_bytes (type) == 16)))
4676 {
4677 bool stack = false;
4678
4679 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4680 {
4681 cum->vregno++;
4682 if (!TARGET_ALTIVEC)
4683 error ("cannot pass argument in vector register because"
4684 " altivec instructions are disabled, use -maltivec"
4685 " to enable them");
4686
4687 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4688 even if it is going to be passed in a vector register.
4689 Darwin does the same for variable-argument functions. */
4690 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4691 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4692 stack = true;
4693 }
4694 else
4695 stack = true;
4696
4697 if (stack)
4698 {
4699 int align;
4700
4701 /* Vector parameters must be 16-byte aligned. This places
4702 them at 2 mod 4 in terms of words in 32-bit mode, since
4703 the parameter save area starts at offset 24 from the
4704 stack. In 64-bit mode, they just have to start on an
4705 even word, since the parameter save area is 16-byte
4706 aligned. Space for GPRs is reserved even if the argument
4707 will be passed in memory. */
4708 if (TARGET_32BIT)
4709 align = (2 - cum->words) & 3;
4710 else
4711 align = cum->words & 1;
4712 cum->words += align + rs6000_arg_size (mode, type);
4713
4714 if (TARGET_DEBUG_ARG)
4715 {
4716 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4717 cum->words, align);
4718 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4719 cum->nargs_prototype, cum->prototype,
4720 GET_MODE_NAME (mode));
4721 }
4722 }
4723 }
4724 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4725 && !cum->stdarg
4726 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4727 cum->sysv_gregno++;
4728
4729 else if (rs6000_darwin64_abi
4730 && mode == BLKmode
4731 && TREE_CODE (type) == RECORD_TYPE
4732 && (size = int_size_in_bytes (type)) > 0)
4733 {
4734 /* Variable sized types have size == -1 and are
4735 treated as if consisting entirely of ints.
4736 Pad to 16 byte boundary if needed. */
4737 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4738 && (cum->words % 2) != 0)
4739 cum->words++;
4740 /* For varargs, we can just go up by the size of the struct. */
4741 if (!named)
4742 cum->words += (size + 7) / 8;
4743 else
4744 {
4745 /* It is tempting to say int register count just goes up by
4746 sizeof(type)/8, but this is wrong in a case such as
4747 { int; double; int; } [powerpc alignment]. We have to
4748 grovel through the fields for these too. */
4749 cum->intoffset = 0;
4750 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4751 rs6000_darwin64_record_arg_advance_flush (cum,
4752 size * BITS_PER_UNIT);
4753 }
4754 }
4755 else if (DEFAULT_ABI == ABI_V4)
4756 {
4757 if (TARGET_HARD_FLOAT && TARGET_FPRS
4758 && (mode == SFmode || mode == DFmode
4759 || (mode == TFmode && !TARGET_IEEEQUAD)))
4760 {
4761 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
4762 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4763 else
4764 {
4765 cum->fregno = FP_ARG_V4_MAX_REG + 1;
4766 if (mode == DFmode || mode == TFmode)
4767 cum->words += cum->words & 1;
4768 cum->words += rs6000_arg_size (mode, type);
4769 }
4770 }
4771 else
4772 {
4773 int n_words = rs6000_arg_size (mode, type);
4774 int gregno = cum->sysv_gregno;
4775
4776 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4777 (r7,r8) or (r9,r10). As does any other 2 word item such
4778 as complex int due to a historical mistake. */
4779 if (n_words == 2)
4780 gregno += (1 - gregno) & 1;
4781
4782 /* Multi-reg args are not split between registers and stack. */
4783 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4784 {
4785 /* Long long and SPE vectors are aligned on the stack.
4786 So are other 2 word items such as complex int due to
4787 a historical mistake. */
4788 if (n_words == 2)
4789 cum->words += cum->words & 1;
4790 cum->words += n_words;
4791 }
4792
4793 /* Note: continuing to accumulate gregno past when we've started
4794 spilling to the stack indicates the fact that we've started
4795 spilling to the stack to expand_builtin_saveregs. */
4796 cum->sysv_gregno = gregno + n_words;
4797 }
4798
4799 if (TARGET_DEBUG_ARG)
4800 {
4801 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4802 cum->words, cum->fregno);
4803 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4804 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4805 fprintf (stderr, "mode = %4s, named = %d\n",
4806 GET_MODE_NAME (mode), named);
4807 }
4808 }
4809 else
4810 {
4811 int n_words = rs6000_arg_size (mode, type);
4812 int start_words = cum->words;
4813 int align_words = rs6000_parm_start (mode, type, start_words);
4814
4815 cum->words = align_words + n_words;
4816
4817 if (SCALAR_FLOAT_MODE_P (mode)
4818 && !DECIMAL_FLOAT_MODE_P (mode)
4819 && TARGET_HARD_FLOAT && TARGET_FPRS)
4820 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4821
4822 if (TARGET_DEBUG_ARG)
4823 {
4824 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4825 cum->words, cum->fregno);
4826 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4827 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4828 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4829 named, align_words - start_words, depth);
4830 }
4831 }
4832 }
4833
4834 static rtx
spe_build_register_parallel(enum machine_mode mode,int gregno)4835 spe_build_register_parallel (enum machine_mode mode, int gregno)
4836 {
4837 rtx r1, r3;
4838
4839 switch (mode)
4840 {
4841 case DFmode:
4842 r1 = gen_rtx_REG (DImode, gregno);
4843 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4844 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4845
4846 case DCmode:
4847 r1 = gen_rtx_REG (DImode, gregno);
4848 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4849 r3 = gen_rtx_REG (DImode, gregno + 2);
4850 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4851 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4852
4853 default:
4854 gcc_unreachable ();
4855 }
4856 }
4857
4858 /* Determine where to put a SIMD argument on the SPE. */
4859 static rtx
rs6000_spe_function_arg(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type)4860 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4861 tree type)
4862 {
4863 int gregno = cum->sysv_gregno;
4864
4865 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4866 are passed and returned in a pair of GPRs for ABI compatibility. */
4867 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4868 {
4869 int n_words = rs6000_arg_size (mode, type);
4870
4871 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4872 if (mode == DFmode)
4873 gregno += (1 - gregno) & 1;
4874
4875 /* Multi-reg args are not split between registers and stack. */
4876 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4877 return NULL_RTX;
4878
4879 return spe_build_register_parallel (mode, gregno);
4880 }
4881 if (cum->stdarg)
4882 {
4883 int n_words = rs6000_arg_size (mode, type);
4884
4885 /* SPE vectors are put in odd registers. */
4886 if (n_words == 2 && (gregno & 1) == 0)
4887 gregno += 1;
4888
4889 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4890 {
4891 rtx r1, r2;
4892 enum machine_mode m = SImode;
4893
4894 r1 = gen_rtx_REG (m, gregno);
4895 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4896 r2 = gen_rtx_REG (m, gregno + 1);
4897 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4898 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4899 }
4900 else
4901 return NULL_RTX;
4902 }
4903 else
4904 {
4905 if (gregno <= GP_ARG_MAX_REG)
4906 return gen_rtx_REG (mode, gregno);
4907 else
4908 return NULL_RTX;
4909 }
4910 }
4911
4912 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4913 structure between cum->intoffset and bitpos to integer registers. */
4914
4915 static void
rs6000_darwin64_record_arg_flush(CUMULATIVE_ARGS * cum,HOST_WIDE_INT bitpos,rtx rvec[],int * k)4916 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4917 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4918 {
4919 enum machine_mode mode;
4920 unsigned int regno;
4921 unsigned int startbit, endbit;
4922 int this_regno, intregs, intoffset;
4923 rtx reg;
4924
4925 if (cum->intoffset == -1)
4926 return;
4927
4928 intoffset = cum->intoffset;
4929 cum->intoffset = -1;
4930
4931 /* If this is the trailing part of a word, try to only load that
4932 much into the register. Otherwise load the whole register. Note
4933 that in the latter case we may pick up unwanted bits. It's not a
4934 problem at the moment but may wish to revisit. */
4935
4936 if (intoffset % BITS_PER_WORD != 0)
4937 {
4938 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4939 MODE_INT, 0);
4940 if (mode == BLKmode)
4941 {
4942 /* We couldn't find an appropriate mode, which happens,
4943 e.g., in packed structs when there are 3 bytes to load.
4944 Back intoffset back to the beginning of the word in this
4945 case. */
4946 intoffset = intoffset & -BITS_PER_WORD;
4947 mode = word_mode;
4948 }
4949 }
4950 else
4951 mode = word_mode;
4952
4953 startbit = intoffset & -BITS_PER_WORD;
4954 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4955 intregs = (endbit - startbit) / BITS_PER_WORD;
4956 this_regno = cum->words + intoffset / BITS_PER_WORD;
4957
4958 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4959 cum->use_stack = 1;
4960
4961 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4962 if (intregs <= 0)
4963 return;
4964
4965 intoffset /= BITS_PER_UNIT;
4966 do
4967 {
4968 regno = GP_ARG_MIN_REG + this_regno;
4969 reg = gen_rtx_REG (mode, regno);
4970 rvec[(*k)++] =
4971 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4972
4973 this_regno += 1;
4974 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4975 mode = word_mode;
4976 intregs -= 1;
4977 }
4978 while (intregs > 0);
4979 }
4980
4981 /* Recursive workhorse for the following. */
4982
4983 static void
rs6000_darwin64_record_arg_recurse(CUMULATIVE_ARGS * cum,tree type,HOST_WIDE_INT startbitpos,rtx rvec[],int * k)4984 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4985 HOST_WIDE_INT startbitpos, rtx rvec[],
4986 int *k)
4987 {
4988 tree f;
4989
4990 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4991 if (TREE_CODE (f) == FIELD_DECL)
4992 {
4993 HOST_WIDE_INT bitpos = startbitpos;
4994 tree ftype = TREE_TYPE (f);
4995 enum machine_mode mode;
4996 if (ftype == error_mark_node)
4997 continue;
4998 mode = TYPE_MODE (ftype);
4999
5000 if (DECL_SIZE (f) != 0
5001 && host_integerp (bit_position (f), 1))
5002 bitpos += int_bit_position (f);
5003
5004 /* ??? FIXME: else assume zero offset. */
5005
5006 if (TREE_CODE (ftype) == RECORD_TYPE)
5007 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5008 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5009 {
5010 #if 0
5011 switch (mode)
5012 {
5013 case SCmode: mode = SFmode; break;
5014 case DCmode: mode = DFmode; break;
5015 case TCmode: mode = TFmode; break;
5016 default: break;
5017 }
5018 #endif
5019 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5020 rvec[(*k)++]
5021 = gen_rtx_EXPR_LIST (VOIDmode,
5022 gen_rtx_REG (mode, cum->fregno++),
5023 GEN_INT (bitpos / BITS_PER_UNIT));
5024 if (mode == TFmode)
5025 cum->fregno++;
5026 }
5027 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5028 {
5029 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5030 rvec[(*k)++]
5031 = gen_rtx_EXPR_LIST (VOIDmode,
5032 gen_rtx_REG (mode, cum->vregno++),
5033 GEN_INT (bitpos / BITS_PER_UNIT));
5034 }
5035 else if (cum->intoffset == -1)
5036 cum->intoffset = bitpos;
5037 }
5038 }
5039
5040 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5041 the register(s) to be used for each field and subfield of a struct
5042 being passed by value, along with the offset of where the
5043 register's value may be found in the block. FP fields go in FP
5044 register, vector fields go in vector registers, and everything
5045 else goes in int registers, packed as in memory.
5046
5047 This code is also used for function return values. RETVAL indicates
5048 whether this is the case.
5049
5050 Much of this is taken from the SPARC V9 port, which has a similar
5051 calling convention. */
5052
5053 static rtx
rs6000_darwin64_record_arg(CUMULATIVE_ARGS * orig_cum,tree type,int named,bool retval)5054 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5055 int named, bool retval)
5056 {
5057 rtx rvec[FIRST_PSEUDO_REGISTER];
5058 int k = 1, kbase = 1;
5059 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5060 /* This is a copy; modifications are not visible to our caller. */
5061 CUMULATIVE_ARGS copy_cum = *orig_cum;
5062 CUMULATIVE_ARGS *cum = ©_cum;
5063
5064 /* Pad to 16 byte boundary if needed. */
5065 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5066 && (cum->words % 2) != 0)
5067 cum->words++;
5068
5069 cum->intoffset = 0;
5070 cum->use_stack = 0;
5071 cum->named = named;
5072
5073 /* Put entries into rvec[] for individual FP and vector fields, and
5074 for the chunks of memory that go in int regs. Note we start at
5075 element 1; 0 is reserved for an indication of using memory, and
5076 may or may not be filled in below. */
5077 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5078 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5079
5080 /* If any part of the struct went on the stack put all of it there.
5081 This hack is because the generic code for
5082 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5083 parts of the struct are not at the beginning. */
5084 if (cum->use_stack)
5085 {
5086 if (retval)
5087 return NULL_RTX; /* doesn't go in registers at all */
5088 kbase = 0;
5089 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5090 }
5091 if (k > 1 || cum->use_stack)
5092 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5093 else
5094 return NULL_RTX;
5095 }
5096
5097 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5098
5099 static rtx
rs6000_mixed_function_arg(enum machine_mode mode,tree type,int align_words)5100 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5101 {
5102 int n_units;
5103 int i, k;
5104 rtx rvec[GP_ARG_NUM_REG + 1];
5105
5106 if (align_words >= GP_ARG_NUM_REG)
5107 return NULL_RTX;
5108
5109 n_units = rs6000_arg_size (mode, type);
5110
5111 /* Optimize the simple case where the arg fits in one gpr, except in
5112 the case of BLKmode due to assign_parms assuming that registers are
5113 BITS_PER_WORD wide. */
5114 if (n_units == 0
5115 || (n_units == 1 && mode != BLKmode))
5116 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5117
5118 k = 0;
5119 if (align_words + n_units > GP_ARG_NUM_REG)
5120 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5121 using a magic NULL_RTX component.
5122 This is not strictly correct. Only some of the arg belongs in
5123 memory, not all of it. However, the normal scheme using
5124 function_arg_partial_nregs can result in unusual subregs, eg.
5125 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5126 store the whole arg to memory is often more efficient than code
5127 to store pieces, and we know that space is available in the right
5128 place for the whole arg. */
5129 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5130
5131 i = 0;
5132 do
5133 {
5134 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5135 rtx off = GEN_INT (i++ * 4);
5136 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5137 }
5138 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5139
5140 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5141 }
5142
5143 /* Determine where to put an argument to a function.
5144 Value is zero to push the argument on the stack,
5145 or a hard register in which to store the argument.
5146
5147 MODE is the argument's machine mode.
5148 TYPE is the data type of the argument (as a tree).
5149 This is null for libcalls where that information may
5150 not be available.
5151 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5152 the preceding args and about the function being called. It is
5153 not modified in this routine.
5154 NAMED is nonzero if this argument is a named parameter
5155 (otherwise it is an extra parameter matching an ellipsis).
5156
5157 On RS/6000 the first eight words of non-FP are normally in registers
5158 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5159 Under V.4, the first 8 FP args are in registers.
5160
5161 If this is floating-point and no prototype is specified, we use
5162 both an FP and integer register (or possibly FP reg and stack). Library
5163 functions (when CALL_LIBCALL is set) always have the proper types for args,
5164 so we can pass the FP value just in one register. emit_library_function
5165 doesn't support PARALLEL anyway.
5166
5167 Note that for args passed by reference, function_arg will be called
5168 with MODE and TYPE set to that of the pointer to the arg, not the arg
5169 itself. */
5170
5171 rtx
function_arg(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named)5172 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5173 tree type, int named)
5174 {
5175 enum rs6000_abi abi = DEFAULT_ABI;
5176
5177 /* Return a marker to indicate whether CR1 needs to set or clear the
5178 bit that V.4 uses to say fp args were passed in registers.
5179 Assume that we don't need the marker for software floating point,
5180 or compiler generated library calls. */
5181 if (mode == VOIDmode)
5182 {
5183 if (abi == ABI_V4
5184 && (cum->call_cookie & CALL_LIBCALL) == 0
5185 && (cum->stdarg
5186 || (cum->nargs_prototype < 0
5187 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5188 {
5189 /* For the SPE, we need to crxor CR6 always. */
5190 if (TARGET_SPE_ABI)
5191 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5192 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5193 return GEN_INT (cum->call_cookie
5194 | ((cum->fregno == FP_ARG_MIN_REG)
5195 ? CALL_V4_SET_FP_ARGS
5196 : CALL_V4_CLEAR_FP_ARGS));
5197 }
5198
5199 return GEN_INT (cum->call_cookie);
5200 }
5201
5202 if (rs6000_darwin64_abi && mode == BLKmode
5203 && TREE_CODE (type) == RECORD_TYPE)
5204 {
5205 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5206 if (rslt != NULL_RTX)
5207 return rslt;
5208 /* Else fall through to usual handling. */
5209 }
5210
5211 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5212 if (TARGET_64BIT && ! cum->prototype)
5213 {
5214 /* Vector parameters get passed in vector register
5215 and also in GPRs or memory, in absence of prototype. */
5216 int align_words;
5217 rtx slot;
5218 align_words = (cum->words + 1) & ~1;
5219
5220 if (align_words >= GP_ARG_NUM_REG)
5221 {
5222 slot = NULL_RTX;
5223 }
5224 else
5225 {
5226 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5227 }
5228 return gen_rtx_PARALLEL (mode,
5229 gen_rtvec (2,
5230 gen_rtx_EXPR_LIST (VOIDmode,
5231 slot, const0_rtx),
5232 gen_rtx_EXPR_LIST (VOIDmode,
5233 gen_rtx_REG (mode, cum->vregno),
5234 const0_rtx)));
5235 }
5236 else
5237 return gen_rtx_REG (mode, cum->vregno);
5238 else if (TARGET_ALTIVEC_ABI
5239 && (ALTIVEC_VECTOR_MODE (mode)
5240 || (type && TREE_CODE (type) == VECTOR_TYPE
5241 && int_size_in_bytes (type) == 16)))
5242 {
5243 if (named || abi == ABI_V4)
5244 return NULL_RTX;
5245 else
5246 {
5247 /* Vector parameters to varargs functions under AIX or Darwin
5248 get passed in memory and possibly also in GPRs. */
5249 int align, align_words, n_words;
5250 enum machine_mode part_mode;
5251
5252 /* Vector parameters must be 16-byte aligned. This places them at
5253 2 mod 4 in terms of words in 32-bit mode, since the parameter
5254 save area starts at offset 24 from the stack. In 64-bit mode,
5255 they just have to start on an even word, since the parameter
5256 save area is 16-byte aligned. */
5257 if (TARGET_32BIT)
5258 align = (2 - cum->words) & 3;
5259 else
5260 align = cum->words & 1;
5261 align_words = cum->words + align;
5262
5263 /* Out of registers? Memory, then. */
5264 if (align_words >= GP_ARG_NUM_REG)
5265 return NULL_RTX;
5266
5267 if (TARGET_32BIT && TARGET_POWERPC64)
5268 return rs6000_mixed_function_arg (mode, type, align_words);
5269
5270 /* The vector value goes in GPRs. Only the part of the
5271 value in GPRs is reported here. */
5272 part_mode = mode;
5273 n_words = rs6000_arg_size (mode, type);
5274 if (align_words + n_words > GP_ARG_NUM_REG)
5275 /* Fortunately, there are only two possibilities, the value
5276 is either wholly in GPRs or half in GPRs and half not. */
5277 part_mode = DImode;
5278
5279 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5280 }
5281 }
5282 else if (TARGET_SPE_ABI && TARGET_SPE
5283 && (SPE_VECTOR_MODE (mode)
5284 || (TARGET_E500_DOUBLE && (mode == DFmode
5285 || mode == DCmode))))
5286 return rs6000_spe_function_arg (cum, mode, type);
5287
5288 else if (abi == ABI_V4)
5289 {
5290 if (TARGET_HARD_FLOAT && TARGET_FPRS
5291 && (mode == SFmode || mode == DFmode
5292 || (mode == TFmode && !TARGET_IEEEQUAD)))
5293 {
5294 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5295 return gen_rtx_REG (mode, cum->fregno);
5296 else
5297 return NULL_RTX;
5298 }
5299 else
5300 {
5301 int n_words = rs6000_arg_size (mode, type);
5302 int gregno = cum->sysv_gregno;
5303
5304 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5305 (r7,r8) or (r9,r10). As does any other 2 word item such
5306 as complex int due to a historical mistake. */
5307 if (n_words == 2)
5308 gregno += (1 - gregno) & 1;
5309
5310 /* Multi-reg args are not split between registers and stack. */
5311 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5312 return NULL_RTX;
5313
5314 if (TARGET_32BIT && TARGET_POWERPC64)
5315 return rs6000_mixed_function_arg (mode, type,
5316 gregno - GP_ARG_MIN_REG);
5317 return gen_rtx_REG (mode, gregno);
5318 }
5319 }
5320 else
5321 {
5322 int align_words = rs6000_parm_start (mode, type, cum->words);
5323
5324 if (USE_FP_FOR_ARG_P (cum, mode, type))
5325 {
5326 rtx rvec[GP_ARG_NUM_REG + 1];
5327 rtx r;
5328 int k;
5329 bool needs_psave;
5330 enum machine_mode fmode = mode;
5331 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5332
5333 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5334 {
5335 /* Currently, we only ever need one reg here because complex
5336 doubles are split. */
5337 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5338
5339 /* Long double split over regs and memory. */
5340 fmode = DFmode;
5341 }
5342
5343 /* Do we also need to pass this arg in the parameter save
5344 area? */
5345 needs_psave = (type
5346 && (cum->nargs_prototype <= 0
5347 || (DEFAULT_ABI == ABI_AIX
5348 && TARGET_XL_COMPAT
5349 && align_words >= GP_ARG_NUM_REG)));
5350
5351 if (!needs_psave && mode == fmode)
5352 return gen_rtx_REG (fmode, cum->fregno);
5353
5354 k = 0;
5355 if (needs_psave)
5356 {
5357 /* Describe the part that goes in gprs or the stack.
5358 This piece must come first, before the fprs. */
5359 if (align_words < GP_ARG_NUM_REG)
5360 {
5361 unsigned long n_words = rs6000_arg_size (mode, type);
5362
5363 if (align_words + n_words > GP_ARG_NUM_REG
5364 || (TARGET_32BIT && TARGET_POWERPC64))
5365 {
5366 /* If this is partially on the stack, then we only
5367 include the portion actually in registers here. */
5368 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5369 rtx off;
5370 int i = 0;
5371 if (align_words + n_words > GP_ARG_NUM_REG)
5372 /* Not all of the arg fits in gprs. Say that it
5373 goes in memory too, using a magic NULL_RTX
5374 component. Also see comment in
5375 rs6000_mixed_function_arg for why the normal
5376 function_arg_partial_nregs scheme doesn't work
5377 in this case. */
5378 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5379 const0_rtx);
5380 do
5381 {
5382 r = gen_rtx_REG (rmode,
5383 GP_ARG_MIN_REG + align_words);
5384 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5385 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5386 }
5387 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5388 }
5389 else
5390 {
5391 /* The whole arg fits in gprs. */
5392 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5393 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5394 }
5395 }
5396 else
5397 /* It's entirely in memory. */
5398 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5399 }
5400
5401 /* Describe where this piece goes in the fprs. */
5402 r = gen_rtx_REG (fmode, cum->fregno);
5403 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5404
5405 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5406 }
5407 else if (align_words < GP_ARG_NUM_REG)
5408 {
5409 if (TARGET_32BIT && TARGET_POWERPC64)
5410 return rs6000_mixed_function_arg (mode, type, align_words);
5411
5412 if (mode == BLKmode)
5413 mode = Pmode;
5414
5415 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5416 }
5417 else
5418 return NULL_RTX;
5419 }
5420 }
5421
5422 /* For an arg passed partly in registers and partly in memory, this is
5423 the number of bytes passed in registers. For args passed entirely in
5424 registers or entirely in memory, zero. When an arg is described by a
5425 PARALLEL, perhaps using more than one register type, this function
5426 returns the number of bytes used by the first element of the PARALLEL. */
5427
5428 static int
rs6000_arg_partial_bytes(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,bool named)5429 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5430 tree type, bool named)
5431 {
5432 int ret = 0;
5433 int align_words;
5434
5435 if (DEFAULT_ABI == ABI_V4)
5436 return 0;
5437
5438 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5439 && cum->nargs_prototype >= 0)
5440 return 0;
5441
5442 /* In this complicated case we just disable the partial_nregs code. */
5443 if (rs6000_darwin64_abi && mode == BLKmode
5444 && TREE_CODE (type) == RECORD_TYPE
5445 && int_size_in_bytes (type) > 0)
5446 return 0;
5447
5448 align_words = rs6000_parm_start (mode, type, cum->words);
5449
5450 if (USE_FP_FOR_ARG_P (cum, mode, type))
5451 {
5452 /* If we are passing this arg in the fixed parameter save area
5453 (gprs or memory) as well as fprs, then this function should
5454 return the number of partial bytes passed in the parameter
5455 save area rather than partial bytes passed in fprs. */
5456 if (type
5457 && (cum->nargs_prototype <= 0
5458 || (DEFAULT_ABI == ABI_AIX
5459 && TARGET_XL_COMPAT
5460 && align_words >= GP_ARG_NUM_REG)))
5461 return 0;
5462 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5463 > FP_ARG_MAX_REG + 1)
5464 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5465 else if (cum->nargs_prototype >= 0)
5466 return 0;
5467 }
5468
5469 if (align_words < GP_ARG_NUM_REG
5470 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5471 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5472
5473 if (ret != 0 && TARGET_DEBUG_ARG)
5474 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5475
5476 return ret;
5477 }
5478
5479 /* A C expression that indicates when an argument must be passed by
5480 reference. If nonzero for an argument, a copy of that argument is
5481 made in memory and a pointer to the argument is passed instead of
5482 the argument itself. The pointer is passed in whatever way is
5483 appropriate for passing a pointer to that type.
5484
5485 Under V.4, aggregates and long double are passed by reference.
5486
5487 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5488 reference unless the AltiVec vector extension ABI is in force.
5489
5490 As an extension to all ABIs, variable sized types are passed by
5491 reference. */
5492
5493 static bool
rs6000_pass_by_reference(CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,enum machine_mode mode,tree type,bool named ATTRIBUTE_UNUSED)5494 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5495 enum machine_mode mode, tree type,
5496 bool named ATTRIBUTE_UNUSED)
5497 {
5498 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5499 {
5500 if (TARGET_DEBUG_ARG)
5501 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5502 return 1;
5503 }
5504
5505 if (!type)
5506 return 0;
5507
5508 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5509 {
5510 if (TARGET_DEBUG_ARG)
5511 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5512 return 1;
5513 }
5514
5515 if (int_size_in_bytes (type) < 0)
5516 {
5517 if (TARGET_DEBUG_ARG)
5518 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5519 return 1;
5520 }
5521
5522 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5523 modes only exist for GCC vector types if -maltivec. */
5524 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5525 {
5526 if (TARGET_DEBUG_ARG)
5527 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5528 return 1;
5529 }
5530
5531 /* Pass synthetic vectors in memory. */
5532 if (TREE_CODE (type) == VECTOR_TYPE
5533 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5534 {
5535 static bool warned_for_pass_big_vectors = false;
5536 if (TARGET_DEBUG_ARG)
5537 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5538 if (!warned_for_pass_big_vectors)
5539 {
5540 warning (0, "GCC vector passed by reference: "
5541 "non-standard ABI extension with no compatibility guarantee");
5542 warned_for_pass_big_vectors = true;
5543 }
5544 return 1;
5545 }
5546
5547 return 0;
5548 }
5549
5550 static void
rs6000_move_block_from_reg(int regno,rtx x,int nregs)5551 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5552 {
5553 int i;
5554 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5555
5556 if (nregs == 0)
5557 return;
5558
5559 for (i = 0; i < nregs; i++)
5560 {
5561 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5562 if (reload_completed)
5563 {
5564 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5565 tem = NULL_RTX;
5566 else
5567 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5568 i * GET_MODE_SIZE (reg_mode));
5569 }
5570 else
5571 tem = replace_equiv_address (tem, XEXP (tem, 0));
5572
5573 gcc_assert (tem);
5574
5575 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5576 }
5577 }
5578
5579 /* Perform any needed actions needed for a function that is receiving a
5580 variable number of arguments.
5581
5582 CUM is as above.
5583
5584 MODE and TYPE are the mode and type of the current parameter.
5585
5586 PRETEND_SIZE is a variable that should be set to the amount of stack
5587 that must be pushed by the prolog to pretend that our caller pushed
5588 it.
5589
5590 Normally, this macro will push all remaining incoming registers on the
5591 stack and set PRETEND_SIZE to the length of the registers pushed. */
5592
5593 static void
setup_incoming_varargs(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int * pretend_size ATTRIBUTE_UNUSED,int no_rtl)5594 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5595 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5596 int no_rtl)
5597 {
5598 CUMULATIVE_ARGS next_cum;
5599 int reg_size = TARGET_32BIT ? 4 : 8;
5600 rtx save_area = NULL_RTX, mem;
5601 int first_reg_offset, set;
5602
5603 /* Skip the last named argument. */
5604 next_cum = *cum;
5605 function_arg_advance (&next_cum, mode, type, 1, 0);
5606
5607 if (DEFAULT_ABI == ABI_V4)
5608 {
5609 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5610
5611 if (! no_rtl)
5612 {
5613 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5614 HOST_WIDE_INT offset = 0;
5615
5616 /* Try to optimize the size of the varargs save area.
5617 The ABI requires that ap.reg_save_area is doubleword
5618 aligned, but we don't need to allocate space for all
5619 the bytes, only those to which we actually will save
5620 anything. */
5621 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5622 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5623 if (TARGET_HARD_FLOAT && TARGET_FPRS
5624 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5625 && cfun->va_list_fpr_size)
5626 {
5627 if (gpr_reg_num)
5628 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5629 * UNITS_PER_FP_WORD;
5630 if (cfun->va_list_fpr_size
5631 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5632 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5633 else
5634 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5635 * UNITS_PER_FP_WORD;
5636 }
5637 if (gpr_reg_num)
5638 {
5639 offset = -((first_reg_offset * reg_size) & ~7);
5640 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5641 {
5642 gpr_reg_num = cfun->va_list_gpr_size;
5643 if (reg_size == 4 && (first_reg_offset & 1))
5644 gpr_reg_num++;
5645 }
5646 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5647 }
5648 else if (fpr_size)
5649 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5650 * UNITS_PER_FP_WORD
5651 - (int) (GP_ARG_NUM_REG * reg_size);
5652
5653 if (gpr_size + fpr_size)
5654 {
5655 rtx reg_save_area
5656 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5657 gcc_assert (GET_CODE (reg_save_area) == MEM);
5658 reg_save_area = XEXP (reg_save_area, 0);
5659 if (GET_CODE (reg_save_area) == PLUS)
5660 {
5661 gcc_assert (XEXP (reg_save_area, 0)
5662 == virtual_stack_vars_rtx);
5663 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5664 offset += INTVAL (XEXP (reg_save_area, 1));
5665 }
5666 else
5667 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5668 }
5669
5670 cfun->machine->varargs_save_offset = offset;
5671 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5672 }
5673 }
5674 else
5675 {
5676 first_reg_offset = next_cum.words;
5677 save_area = virtual_incoming_args_rtx;
5678
5679 if (targetm.calls.must_pass_in_stack (mode, type))
5680 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5681 }
5682
5683 set = get_varargs_alias_set ();
5684 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5685 && cfun->va_list_gpr_size)
5686 {
5687 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5688
5689 if (va_list_gpr_counter_field)
5690 {
5691 /* V4 va_list_gpr_size counts number of registers needed. */
5692 if (nregs > cfun->va_list_gpr_size)
5693 nregs = cfun->va_list_gpr_size;
5694 }
5695 else
5696 {
5697 /* char * va_list instead counts number of bytes needed. */
5698 if (nregs > cfun->va_list_gpr_size / reg_size)
5699 nregs = cfun->va_list_gpr_size / reg_size;
5700 }
5701
5702 mem = gen_rtx_MEM (BLKmode,
5703 plus_constant (save_area,
5704 first_reg_offset * reg_size));
5705 MEM_NOTRAP_P (mem) = 1;
5706 set_mem_alias_set (mem, set);
5707 set_mem_align (mem, BITS_PER_WORD);
5708
5709 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5710 nregs);
5711 }
5712
5713 /* Save FP registers if needed. */
5714 if (DEFAULT_ABI == ABI_V4
5715 && TARGET_HARD_FLOAT && TARGET_FPRS
5716 && ! no_rtl
5717 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5718 && cfun->va_list_fpr_size)
5719 {
5720 int fregno = next_cum.fregno, nregs;
5721 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5722 rtx lab = gen_label_rtx ();
5723 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5724 * UNITS_PER_FP_WORD);
5725
5726 emit_jump_insn
5727 (gen_rtx_SET (VOIDmode,
5728 pc_rtx,
5729 gen_rtx_IF_THEN_ELSE (VOIDmode,
5730 gen_rtx_NE (VOIDmode, cr1,
5731 const0_rtx),
5732 gen_rtx_LABEL_REF (VOIDmode, lab),
5733 pc_rtx)));
5734
5735 for (nregs = 0;
5736 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5737 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5738 {
5739 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5740 MEM_NOTRAP_P (mem) = 1;
5741 set_mem_alias_set (mem, set);
5742 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5743 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5744 }
5745
5746 emit_label (lab);
5747 }
5748 }
5749
5750 /* Create the va_list data type. */
5751
5752 static tree
rs6000_build_builtin_va_list(void)5753 rs6000_build_builtin_va_list (void)
5754 {
5755 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5756
5757 /* For AIX, prefer 'char *' because that's what the system
5758 header files like. */
5759 if (DEFAULT_ABI != ABI_V4)
5760 return build_pointer_type (char_type_node);
5761
5762 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5763 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5764
5765 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5766 unsigned_char_type_node);
5767 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5768 unsigned_char_type_node);
5769 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5770 every user file. */
5771 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5772 short_unsigned_type_node);
5773 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5774 ptr_type_node);
5775 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5776 ptr_type_node);
5777
5778 va_list_gpr_counter_field = f_gpr;
5779 va_list_fpr_counter_field = f_fpr;
5780
5781 DECL_FIELD_CONTEXT (f_gpr) = record;
5782 DECL_FIELD_CONTEXT (f_fpr) = record;
5783 DECL_FIELD_CONTEXT (f_res) = record;
5784 DECL_FIELD_CONTEXT (f_ovf) = record;
5785 DECL_FIELD_CONTEXT (f_sav) = record;
5786
5787 TREE_CHAIN (record) = type_decl;
5788 TYPE_NAME (record) = type_decl;
5789 TYPE_FIELDS (record) = f_gpr;
5790 TREE_CHAIN (f_gpr) = f_fpr;
5791 TREE_CHAIN (f_fpr) = f_res;
5792 TREE_CHAIN (f_res) = f_ovf;
5793 TREE_CHAIN (f_ovf) = f_sav;
5794
5795 layout_type (record);
5796
5797 /* The correct type is an array type of one element. */
5798 return build_array_type (record, build_index_type (size_zero_node));
5799 }
5800
5801 /* Implement va_start. */
5802
5803 void
rs6000_va_start(tree valist,rtx nextarg)5804 rs6000_va_start (tree valist, rtx nextarg)
5805 {
5806 HOST_WIDE_INT words, n_gpr, n_fpr;
5807 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5808 tree gpr, fpr, ovf, sav, t;
5809
5810 /* Only SVR4 needs something special. */
5811 if (DEFAULT_ABI != ABI_V4)
5812 {
5813 std_expand_builtin_va_start (valist, nextarg);
5814 return;
5815 }
5816
5817 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5818 f_fpr = TREE_CHAIN (f_gpr);
5819 f_res = TREE_CHAIN (f_fpr);
5820 f_ovf = TREE_CHAIN (f_res);
5821 f_sav = TREE_CHAIN (f_ovf);
5822
5823 valist = build_va_arg_indirect_ref (valist);
5824 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5825 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5826 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5827 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5828
5829 /* Count number of gp and fp argument registers used. */
5830 words = current_function_args_info.words;
5831 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5832 GP_ARG_NUM_REG);
5833 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5834 FP_ARG_NUM_REG);
5835
5836 if (TARGET_DEBUG_ARG)
5837 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5838 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5839 words, n_gpr, n_fpr);
5840
5841 if (cfun->va_list_gpr_size)
5842 {
5843 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5844 build_int_cst (NULL_TREE, n_gpr));
5845 TREE_SIDE_EFFECTS (t) = 1;
5846 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5847 }
5848
5849 if (cfun->va_list_fpr_size)
5850 {
5851 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5852 build_int_cst (NULL_TREE, n_fpr));
5853 TREE_SIDE_EFFECTS (t) = 1;
5854 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5855 }
5856
5857 /* Find the overflow area. */
5858 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5859 if (words != 0)
5860 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5861 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5862 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5863 TREE_SIDE_EFFECTS (t) = 1;
5864 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5865
5866 /* If there were no va_arg invocations, don't set up the register
5867 save area. */
5868 if (!cfun->va_list_gpr_size
5869 && !cfun->va_list_fpr_size
5870 && n_gpr < GP_ARG_NUM_REG
5871 && n_fpr < FP_ARG_V4_MAX_REG)
5872 return;
5873
5874 /* Find the register save area. */
5875 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5876 if (cfun->machine->varargs_save_offset)
5877 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5878 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5879 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5880 TREE_SIDE_EFFECTS (t) = 1;
5881 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5882 }
5883
5884 /* Implement va_arg. */
5885
5886 tree
rs6000_gimplify_va_arg(tree valist,tree type,tree * pre_p,tree * post_p)5887 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5888 {
5889 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5890 tree gpr, fpr, ovf, sav, reg, t, u;
5891 int size, rsize, n_reg, sav_ofs, sav_scale;
5892 tree lab_false, lab_over, addr;
5893 int align;
5894 tree ptrtype = build_pointer_type (type);
5895
5896 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5897 {
5898 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5899 return build_va_arg_indirect_ref (t);
5900 }
5901
5902 if (DEFAULT_ABI != ABI_V4)
5903 {
5904 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5905 {
5906 tree elem_type = TREE_TYPE (type);
5907 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5908 int elem_size = GET_MODE_SIZE (elem_mode);
5909
5910 if (elem_size < UNITS_PER_WORD)
5911 {
5912 tree real_part, imag_part;
5913 tree post = NULL_TREE;
5914
5915 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5916 &post);
5917 /* Copy the value into a temporary, lest the formal temporary
5918 be reused out from under us. */
5919 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5920 append_to_statement_list (post, pre_p);
5921
5922 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5923 post_p);
5924
5925 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5926 }
5927 }
5928
5929 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5930 }
5931
5932 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5933 f_fpr = TREE_CHAIN (f_gpr);
5934 f_res = TREE_CHAIN (f_fpr);
5935 f_ovf = TREE_CHAIN (f_res);
5936 f_sav = TREE_CHAIN (f_ovf);
5937
5938 valist = build_va_arg_indirect_ref (valist);
5939 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5940 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5941 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5942 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5943
5944 size = int_size_in_bytes (type);
5945 rsize = (size + 3) / 4;
5946 align = 1;
5947
5948 if (TARGET_HARD_FLOAT && TARGET_FPRS
5949 && (TYPE_MODE (type) == SFmode
5950 || TYPE_MODE (type) == DFmode
5951 || TYPE_MODE (type) == TFmode))
5952 {
5953 /* FP args go in FP registers, if present. */
5954 reg = fpr;
5955 n_reg = (size + 7) / 8;
5956 sav_ofs = 8*4;
5957 sav_scale = 8;
5958 if (TYPE_MODE (type) != SFmode)
5959 align = 8;
5960 }
5961 else
5962 {
5963 /* Otherwise into GP registers. */
5964 reg = gpr;
5965 n_reg = rsize;
5966 sav_ofs = 0;
5967 sav_scale = 4;
5968 if (n_reg == 2)
5969 align = 8;
5970 }
5971
5972 /* Pull the value out of the saved registers.... */
5973
5974 lab_over = NULL;
5975 addr = create_tmp_var (ptr_type_node, "addr");
5976 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5977
5978 /* AltiVec vectors never go in registers when -mabi=altivec. */
5979 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5980 align = 16;
5981 else
5982 {
5983 lab_false = create_artificial_label ();
5984 lab_over = create_artificial_label ();
5985
5986 /* Long long and SPE vectors are aligned in the registers.
5987 As are any other 2 gpr item such as complex int due to a
5988 historical mistake. */
5989 u = reg;
5990 if (n_reg == 2 && reg == gpr)
5991 {
5992 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5993 size_int (n_reg - 1));
5994 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5995 }
5996
5997 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5998 t = build2 (GE_EXPR, boolean_type_node, u, t);
5999 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6000 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6001 gimplify_and_add (t, pre_p);
6002
6003 t = sav;
6004 if (sav_ofs)
6005 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6006
6007 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6008 u = build1 (CONVERT_EXPR, integer_type_node, u);
6009 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6010 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6011
6012 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
6013 gimplify_and_add (t, pre_p);
6014
6015 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6016 gimplify_and_add (t, pre_p);
6017
6018 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6019 append_to_statement_list (t, pre_p);
6020
6021 if ((n_reg == 2 && reg != gpr) || n_reg > 2)
6022 {
6023 /* Ensure that we don't find any more args in regs.
6024 Alignment has taken care of the n_reg == 2 gpr case. */
6025 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
6026 gimplify_and_add (t, pre_p);
6027 }
6028 }
6029
6030 /* ... otherwise out of the overflow area. */
6031
6032 /* Care for on-stack alignment if needed. */
6033 t = ovf;
6034 if (align != 1)
6035 {
6036 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6037 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6038 build_int_cst (NULL_TREE, -align));
6039 }
6040 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6041
6042 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
6043 gimplify_and_add (u, pre_p);
6044
6045 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6046 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6047 gimplify_and_add (t, pre_p);
6048
6049 if (lab_over)
6050 {
6051 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6052 append_to_statement_list (t, pre_p);
6053 }
6054
6055 if (STRICT_ALIGNMENT
6056 && (TYPE_ALIGN (type)
6057 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6058 {
6059 /* The value (of type complex double, for example) may not be
6060 aligned in memory in the saved registers, so copy via a
6061 temporary. (This is the same code as used for SPARC.) */
6062 tree tmp = create_tmp_var (type, "va_arg_tmp");
6063 tree dest_addr = build_fold_addr_expr (tmp);
6064
6065 tree copy = build_function_call_expr
6066 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6067 tree_cons (NULL_TREE, dest_addr,
6068 tree_cons (NULL_TREE, addr,
6069 tree_cons (NULL_TREE, size_int (rsize * 4),
6070 NULL_TREE))));
6071
6072 gimplify_and_add (copy, pre_p);
6073 addr = dest_addr;
6074 }
6075
6076 addr = fold_convert (ptrtype, addr);
6077 return build_va_arg_indirect_ref (addr);
6078 }
6079
6080 /* Builtins. */
6081
6082 static void
def_builtin(int mask,const char * name,tree type,int code)6083 def_builtin (int mask, const char *name, tree type, int code)
6084 {
6085 if (mask & target_flags)
6086 {
6087 if (rs6000_builtin_decls[code])
6088 abort ();
6089
6090 rs6000_builtin_decls[code] =
6091 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
6092 NULL, NULL_TREE);
6093 }
6094 }
6095
6096 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6097
6098 static const struct builtin_description bdesc_3arg[] =
6099 {
6100 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6101 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6102 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6103 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6104 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6105 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6106 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6107 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6108 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6109 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6110 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6111 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6112 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6113 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6114 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6115 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6116 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6117 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6118 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6119 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6120 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6121 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6122 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6123
6124 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6125 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6126 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6127 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6128 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6129 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6130 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6131 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6132 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6133 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6134 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6135 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6136 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6137 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6138 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6139 };
6140
6141 /* DST operations: void foo (void *, const int, const char). */
6142
6143 static const struct builtin_description bdesc_dst[] =
6144 {
6145 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6146 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6147 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6148 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6149
6150 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6151 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6152 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6153 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6154 };
6155
6156 /* Simple binary operations: VECc = foo (VECa, VECb). */
6157
6158 static struct builtin_description bdesc_2arg[] =
6159 {
6160 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6161 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6162 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6163 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6164 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6165 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6166 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6167 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6168 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6169 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6170 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6171 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6172 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6173 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6174 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6175 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6176 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6177 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6178 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6179 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6180 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6181 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6182 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6183 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6184 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6185 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6186 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6187 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6188 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6189 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6190 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6191 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6192 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6193 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6194 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6195 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6196 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6197 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6198 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6199 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6200 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6201 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6202 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6203 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6204 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6205 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6206 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6207 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6208 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6209 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6210 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6211 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6212 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6213 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6214 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6215 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6216 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6217 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6218 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6219 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6220 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6221 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6222 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6223 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6224 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6225 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6226 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6227 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6228 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6229 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6230 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6231 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6232 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6233 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6234 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6235 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6236 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6237 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6238 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6239 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6240 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6241 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6242 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6243 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6244 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6245 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6246 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6247 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6248 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6249 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6250 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6251 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6252 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6253 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6254 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6255 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6256 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6257 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6258 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6259 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6260 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6261 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6262 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6263 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6264 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6265 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6266 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6267 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6268 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6269 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6270 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6271
6272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6283 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6284 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6285 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6286 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6287 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6288 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6289 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6290 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6291 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6292 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6293 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6294 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6295 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6296 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6303 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6304 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6305 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6306 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6307 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6308 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6309 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6310 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6311 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6312 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6313 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6314 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6315 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6316 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6317 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6318 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6319 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6320 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6321 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6322 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6323 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6324 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6325 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6326 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6327 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6328 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6329 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6330 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6331 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6332 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6333 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6334 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6335 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6336 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6337 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6338 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6339 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6340 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6341 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6342 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6343 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6344 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6345 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6346 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6347 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6348 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6349 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6350 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6351 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6352 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6353 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6354 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6355 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6356 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6357 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6358 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6359 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6360 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6361 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6362 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6363 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6364 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6365 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6366 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6367 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6368 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6369 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6370 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6371 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6372 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6373 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6374 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6375 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6376 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6377 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6378 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6379 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6380 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6381 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6382 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6383 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6384 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6385 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6386 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6387 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6388 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6389 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6390 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6391 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6392 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6393 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6394 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6395 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6396 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6397 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6398 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6399
6400 /* Place holder, leave as first spe builtin. */
6401 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6402 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6403 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6404 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6405 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6406 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6407 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6408 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6409 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6410 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6411 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6412 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6413 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6414 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6415 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6416 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6417 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6418 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6419 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6420 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6421 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6422 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6423 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6424 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6425 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6426 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6427 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6428 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6429 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6430 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6431 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6432 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6433 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6434 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6435 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6436 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6437 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6438 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6439 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6440 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6441 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6442 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6443 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6444 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6445 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6446 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6447 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6448 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6449 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6450 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6451 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6452 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6453 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6454 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6455 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6456 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6457 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6458 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6459 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6460 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6461 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6462 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6463 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6464 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6465 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6466 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6467 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6468 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6469 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6470 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6471 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6472 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6473 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6474 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6475 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6476 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6477 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6478 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6479 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6480 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6481 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6482 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6483 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6484 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6485 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6486 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6487 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6488 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6489 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6490 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6491 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6492 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6493 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6494 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6495 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6496 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6497 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6498 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6499 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6500 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6501 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6502 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6503 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6504 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6505 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6506 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6507 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6508 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6509 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6510
6511 /* SPE binary operations expecting a 5-bit unsigned literal. */
6512 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6513
6514 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6515 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6516 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6517 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6518 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6519 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6520 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6521 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6522 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6523 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6524 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6525 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6526 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6527 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6528 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6529 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6530 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6531 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6532 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6533 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6534 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6535 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6536 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6537 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6538 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6539 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6540
6541 /* Place-holder. Leave as last binary SPE builtin. */
6542 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6543 };
6544
6545 /* AltiVec predicates. */
6546
6547 struct builtin_description_predicates
6548 {
6549 const unsigned int mask;
6550 const enum insn_code icode;
6551 const char *opcode;
6552 const char *const name;
6553 const enum rs6000_builtins code;
6554 };
6555
6556 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6557 {
6558 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6559 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6560 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6561 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6562 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6563 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6564 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6565 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6566 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6567 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6568 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6569 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6570 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6571
6572 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6573 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6574 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6575 };
6576
6577 /* SPE predicates. */
6578 static struct builtin_description bdesc_spe_predicates[] =
6579 {
6580 /* Place-holder. Leave as first. */
6581 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6582 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6583 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6584 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6585 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6586 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6587 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6588 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6589 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6590 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6591 /* Place-holder. Leave as last. */
6592 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6593 };
6594
6595 /* SPE evsel predicates. */
6596 static struct builtin_description bdesc_spe_evsel[] =
6597 {
6598 /* Place-holder. Leave as first. */
6599 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6600 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6601 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6602 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6603 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6604 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6605 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6606 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6607 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6608 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6609 /* Place-holder. Leave as last. */
6610 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6611 };
6612
6613 /* ABS* operations. */
6614
6615 static const struct builtin_description bdesc_abs[] =
6616 {
6617 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6618 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6619 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6620 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6621 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6622 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6623 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6624 };
6625
6626 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6627 foo (VECa). */
6628
6629 static struct builtin_description bdesc_1arg[] =
6630 {
6631 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6632 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6633 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6634 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6635 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6636 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6637 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6638 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6639 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6640 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6641 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6642 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6643 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6644 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6645 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6646 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6647 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6648
6649 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6651 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6652 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6653 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6654 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6660 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6661 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6662 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6663 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6664 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6665 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6666 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6667 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6668
6669 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6670 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6671 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6672 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6673 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6674 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6675 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6676 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6677 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6678 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6679 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6680 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6681 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6682 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6683 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6684 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6685 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6686 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6687 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6688 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6689 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6690 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6691 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6692 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6693 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6694 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6695 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6696 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6697 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6698 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6699
6700 /* Place-holder. Leave as last unary SPE builtin. */
6701 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6702 };
6703
6704 static rtx
rs6000_expand_unop_builtin(enum insn_code icode,tree arglist,rtx target)6705 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6706 {
6707 rtx pat;
6708 tree arg0 = TREE_VALUE (arglist);
6709 rtx op0 = expand_normal (arg0);
6710 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6711 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6712
6713 if (icode == CODE_FOR_nothing)
6714 /* Builtin not supported on this processor. */
6715 return 0;
6716
6717 /* If we got invalid arguments bail out before generating bad rtl. */
6718 if (arg0 == error_mark_node)
6719 return const0_rtx;
6720
6721 if (icode == CODE_FOR_altivec_vspltisb
6722 || icode == CODE_FOR_altivec_vspltish
6723 || icode == CODE_FOR_altivec_vspltisw
6724 || icode == CODE_FOR_spe_evsplatfi
6725 || icode == CODE_FOR_spe_evsplati)
6726 {
6727 /* Only allow 5-bit *signed* literals. */
6728 if (GET_CODE (op0) != CONST_INT
6729 || INTVAL (op0) > 15
6730 || INTVAL (op0) < -16)
6731 {
6732 error ("argument 1 must be a 5-bit signed literal");
6733 return const0_rtx;
6734 }
6735 }
6736
6737 if (target == 0
6738 || GET_MODE (target) != tmode
6739 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6740 target = gen_reg_rtx (tmode);
6741
6742 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6743 op0 = copy_to_mode_reg (mode0, op0);
6744
6745 pat = GEN_FCN (icode) (target, op0);
6746 if (! pat)
6747 return 0;
6748 emit_insn (pat);
6749
6750 return target;
6751 }
6752
6753 static rtx
altivec_expand_abs_builtin(enum insn_code icode,tree arglist,rtx target)6754 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6755 {
6756 rtx pat, scratch1, scratch2;
6757 tree arg0 = TREE_VALUE (arglist);
6758 rtx op0 = expand_normal (arg0);
6759 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6760 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6761
6762 /* If we have invalid arguments, bail out before generating bad rtl. */
6763 if (arg0 == error_mark_node)
6764 return const0_rtx;
6765
6766 if (target == 0
6767 || GET_MODE (target) != tmode
6768 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6769 target = gen_reg_rtx (tmode);
6770
6771 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6772 op0 = copy_to_mode_reg (mode0, op0);
6773
6774 scratch1 = gen_reg_rtx (mode0);
6775 scratch2 = gen_reg_rtx (mode0);
6776
6777 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6778 if (! pat)
6779 return 0;
6780 emit_insn (pat);
6781
6782 return target;
6783 }
6784
6785 static rtx
rs6000_expand_binop_builtin(enum insn_code icode,tree arglist,rtx target)6786 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6787 {
6788 rtx pat;
6789 tree arg0 = TREE_VALUE (arglist);
6790 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6791 rtx op0 = expand_normal (arg0);
6792 rtx op1 = expand_normal (arg1);
6793 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6794 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6795 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6796
6797 if (icode == CODE_FOR_nothing)
6798 /* Builtin not supported on this processor. */
6799 return 0;
6800
6801 /* If we got invalid arguments bail out before generating bad rtl. */
6802 if (arg0 == error_mark_node || arg1 == error_mark_node)
6803 return const0_rtx;
6804
6805 if (icode == CODE_FOR_altivec_vcfux
6806 || icode == CODE_FOR_altivec_vcfsx
6807 || icode == CODE_FOR_altivec_vctsxs
6808 || icode == CODE_FOR_altivec_vctuxs
6809 || icode == CODE_FOR_altivec_vspltb
6810 || icode == CODE_FOR_altivec_vsplth
6811 || icode == CODE_FOR_altivec_vspltw
6812 || icode == CODE_FOR_spe_evaddiw
6813 || icode == CODE_FOR_spe_evldd
6814 || icode == CODE_FOR_spe_evldh
6815 || icode == CODE_FOR_spe_evldw
6816 || icode == CODE_FOR_spe_evlhhesplat
6817 || icode == CODE_FOR_spe_evlhhossplat
6818 || icode == CODE_FOR_spe_evlhhousplat
6819 || icode == CODE_FOR_spe_evlwhe
6820 || icode == CODE_FOR_spe_evlwhos
6821 || icode == CODE_FOR_spe_evlwhou
6822 || icode == CODE_FOR_spe_evlwhsplat
6823 || icode == CODE_FOR_spe_evlwwsplat
6824 || icode == CODE_FOR_spe_evrlwi
6825 || icode == CODE_FOR_spe_evslwi
6826 || icode == CODE_FOR_spe_evsrwis
6827 || icode == CODE_FOR_spe_evsubifw
6828 || icode == CODE_FOR_spe_evsrwiu)
6829 {
6830 /* Only allow 5-bit unsigned literals. */
6831 STRIP_NOPS (arg1);
6832 if (TREE_CODE (arg1) != INTEGER_CST
6833 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6834 {
6835 error ("argument 2 must be a 5-bit unsigned literal");
6836 return const0_rtx;
6837 }
6838 }
6839
6840 if (target == 0
6841 || GET_MODE (target) != tmode
6842 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6843 target = gen_reg_rtx (tmode);
6844
6845 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6846 op0 = copy_to_mode_reg (mode0, op0);
6847 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6848 op1 = copy_to_mode_reg (mode1, op1);
6849
6850 pat = GEN_FCN (icode) (target, op0, op1);
6851 if (! pat)
6852 return 0;
6853 emit_insn (pat);
6854
6855 return target;
6856 }
6857
6858 static rtx
altivec_expand_predicate_builtin(enum insn_code icode,const char * opcode,tree arglist,rtx target)6859 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6860 tree arglist, rtx target)
6861 {
6862 rtx pat, scratch;
6863 tree cr6_form = TREE_VALUE (arglist);
6864 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6865 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6866 rtx op0 = expand_normal (arg0);
6867 rtx op1 = expand_normal (arg1);
6868 enum machine_mode tmode = SImode;
6869 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6870 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6871 int cr6_form_int;
6872
6873 if (TREE_CODE (cr6_form) != INTEGER_CST)
6874 {
6875 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6876 return const0_rtx;
6877 }
6878 else
6879 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6880
6881 gcc_assert (mode0 == mode1);
6882
6883 /* If we have invalid arguments, bail out before generating bad rtl. */
6884 if (arg0 == error_mark_node || arg1 == error_mark_node)
6885 return const0_rtx;
6886
6887 if (target == 0
6888 || GET_MODE (target) != tmode
6889 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6890 target = gen_reg_rtx (tmode);
6891
6892 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6893 op0 = copy_to_mode_reg (mode0, op0);
6894 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6895 op1 = copy_to_mode_reg (mode1, op1);
6896
6897 scratch = gen_reg_rtx (mode0);
6898
6899 pat = GEN_FCN (icode) (scratch, op0, op1,
6900 gen_rtx_SYMBOL_REF (Pmode, opcode));
6901 if (! pat)
6902 return 0;
6903 emit_insn (pat);
6904
6905 /* The vec_any* and vec_all* predicates use the same opcodes for two
6906 different operations, but the bits in CR6 will be different
6907 depending on what information we want. So we have to play tricks
6908 with CR6 to get the right bits out.
6909
6910 If you think this is disgusting, look at the specs for the
6911 AltiVec predicates. */
6912
6913 switch (cr6_form_int)
6914 {
6915 case 0:
6916 emit_insn (gen_cr6_test_for_zero (target));
6917 break;
6918 case 1:
6919 emit_insn (gen_cr6_test_for_zero_reverse (target));
6920 break;
6921 case 2:
6922 emit_insn (gen_cr6_test_for_lt (target));
6923 break;
6924 case 3:
6925 emit_insn (gen_cr6_test_for_lt_reverse (target));
6926 break;
6927 default:
6928 error ("argument 1 of __builtin_altivec_predicate is out of range");
6929 break;
6930 }
6931
6932 return target;
6933 }
6934
6935 static rtx
altivec_expand_lv_builtin(enum insn_code icode,tree arglist,rtx target)6936 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6937 {
6938 rtx pat, addr;
6939 tree arg0 = TREE_VALUE (arglist);
6940 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6941 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6942 enum machine_mode mode0 = Pmode;
6943 enum machine_mode mode1 = Pmode;
6944 rtx op0 = expand_normal (arg0);
6945 rtx op1 = expand_normal (arg1);
6946
6947 if (icode == CODE_FOR_nothing)
6948 /* Builtin not supported on this processor. */
6949 return 0;
6950
6951 /* If we got invalid arguments bail out before generating bad rtl. */
6952 if (arg0 == error_mark_node || arg1 == error_mark_node)
6953 return const0_rtx;
6954
6955 if (target == 0
6956 || GET_MODE (target) != tmode
6957 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6958 target = gen_reg_rtx (tmode);
6959
6960 op1 = copy_to_mode_reg (mode1, op1);
6961
6962 if (op0 == const0_rtx)
6963 {
6964 addr = gen_rtx_MEM (tmode, op1);
6965 }
6966 else
6967 {
6968 op0 = copy_to_mode_reg (mode0, op0);
6969 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6970 }
6971
6972 pat = GEN_FCN (icode) (target, addr);
6973
6974 if (! pat)
6975 return 0;
6976 emit_insn (pat);
6977
6978 return target;
6979 }
6980
6981 static rtx
spe_expand_stv_builtin(enum insn_code icode,tree arglist)6982 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6983 {
6984 tree arg0 = TREE_VALUE (arglist);
6985 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6986 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6987 rtx op0 = expand_normal (arg0);
6988 rtx op1 = expand_normal (arg1);
6989 rtx op2 = expand_normal (arg2);
6990 rtx pat;
6991 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6992 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6993 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6994
6995 /* Invalid arguments. Bail before doing anything stoopid! */
6996 if (arg0 == error_mark_node
6997 || arg1 == error_mark_node
6998 || arg2 == error_mark_node)
6999 return const0_rtx;
7000
7001 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7002 op0 = copy_to_mode_reg (mode2, op0);
7003 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7004 op1 = copy_to_mode_reg (mode0, op1);
7005 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7006 op2 = copy_to_mode_reg (mode1, op2);
7007
7008 pat = GEN_FCN (icode) (op1, op2, op0);
7009 if (pat)
7010 emit_insn (pat);
7011 return NULL_RTX;
7012 }
7013
7014 static rtx
altivec_expand_stv_builtin(enum insn_code icode,tree arglist)7015 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
7016 {
7017 tree arg0 = TREE_VALUE (arglist);
7018 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7019 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7020 rtx op0 = expand_normal (arg0);
7021 rtx op1 = expand_normal (arg1);
7022 rtx op2 = expand_normal (arg2);
7023 rtx pat, addr;
7024 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7025 enum machine_mode mode1 = Pmode;
7026 enum machine_mode mode2 = Pmode;
7027
7028 /* Invalid arguments. Bail before doing anything stoopid! */
7029 if (arg0 == error_mark_node
7030 || arg1 == error_mark_node
7031 || arg2 == error_mark_node)
7032 return const0_rtx;
7033
7034 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7035 op0 = copy_to_mode_reg (tmode, op0);
7036
7037 op2 = copy_to_mode_reg (mode2, op2);
7038
7039 if (op1 == const0_rtx)
7040 {
7041 addr = gen_rtx_MEM (tmode, op2);
7042 }
7043 else
7044 {
7045 op1 = copy_to_mode_reg (mode1, op1);
7046 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7047 }
7048
7049 pat = GEN_FCN (icode) (addr, op0);
7050 if (pat)
7051 emit_insn (pat);
7052 return NULL_RTX;
7053 }
7054
7055 static rtx
rs6000_expand_ternop_builtin(enum insn_code icode,tree arglist,rtx target)7056 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
7057 {
7058 rtx pat;
7059 tree arg0 = TREE_VALUE (arglist);
7060 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7061 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7062 rtx op0 = expand_normal (arg0);
7063 rtx op1 = expand_normal (arg1);
7064 rtx op2 = expand_normal (arg2);
7065 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7066 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7067 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7068 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7069
7070 if (icode == CODE_FOR_nothing)
7071 /* Builtin not supported on this processor. */
7072 return 0;
7073
7074 /* If we got invalid arguments bail out before generating bad rtl. */
7075 if (arg0 == error_mark_node
7076 || arg1 == error_mark_node
7077 || arg2 == error_mark_node)
7078 return const0_rtx;
7079
7080 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7081 || icode == CODE_FOR_altivec_vsldoi_v4si
7082 || icode == CODE_FOR_altivec_vsldoi_v8hi
7083 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7084 {
7085 /* Only allow 4-bit unsigned literals. */
7086 STRIP_NOPS (arg2);
7087 if (TREE_CODE (arg2) != INTEGER_CST
7088 || TREE_INT_CST_LOW (arg2) & ~0xf)
7089 {
7090 error ("argument 3 must be a 4-bit unsigned literal");
7091 return const0_rtx;
7092 }
7093 }
7094
7095 if (target == 0
7096 || GET_MODE (target) != tmode
7097 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7098 target = gen_reg_rtx (tmode);
7099
7100 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7101 op0 = copy_to_mode_reg (mode0, op0);
7102 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7103 op1 = copy_to_mode_reg (mode1, op1);
7104 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7105 op2 = copy_to_mode_reg (mode2, op2);
7106
7107 pat = GEN_FCN (icode) (target, op0, op1, op2);
7108 if (! pat)
7109 return 0;
7110 emit_insn (pat);
7111
7112 return target;
7113 }
7114
7115 /* Expand the lvx builtins. */
7116 static rtx
altivec_expand_ld_builtin(tree exp,rtx target,bool * expandedp)7117 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7118 {
7119 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7120 tree arglist = TREE_OPERAND (exp, 1);
7121 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7122 tree arg0;
7123 enum machine_mode tmode, mode0;
7124 rtx pat, op0;
7125 enum insn_code icode;
7126
7127 switch (fcode)
7128 {
7129 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7130 icode = CODE_FOR_altivec_lvx_v16qi;
7131 break;
7132 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7133 icode = CODE_FOR_altivec_lvx_v8hi;
7134 break;
7135 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7136 icode = CODE_FOR_altivec_lvx_v4si;
7137 break;
7138 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7139 icode = CODE_FOR_altivec_lvx_v4sf;
7140 break;
7141 default:
7142 *expandedp = false;
7143 return NULL_RTX;
7144 }
7145
7146 *expandedp = true;
7147
7148 arg0 = TREE_VALUE (arglist);
7149 op0 = expand_normal (arg0);
7150 tmode = insn_data[icode].operand[0].mode;
7151 mode0 = insn_data[icode].operand[1].mode;
7152
7153 if (target == 0
7154 || GET_MODE (target) != tmode
7155 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7156 target = gen_reg_rtx (tmode);
7157
7158 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7159 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7160
7161 pat = GEN_FCN (icode) (target, op0);
7162 if (! pat)
7163 return 0;
7164 emit_insn (pat);
7165 return target;
7166 }
7167
7168 /* Expand the stvx builtins. */
7169 static rtx
altivec_expand_st_builtin(tree exp,rtx target ATTRIBUTE_UNUSED,bool * expandedp)7170 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7171 bool *expandedp)
7172 {
7173 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7174 tree arglist = TREE_OPERAND (exp, 1);
7175 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7176 tree arg0, arg1;
7177 enum machine_mode mode0, mode1;
7178 rtx pat, op0, op1;
7179 enum insn_code icode;
7180
7181 switch (fcode)
7182 {
7183 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7184 icode = CODE_FOR_altivec_stvx_v16qi;
7185 break;
7186 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7187 icode = CODE_FOR_altivec_stvx_v8hi;
7188 break;
7189 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7190 icode = CODE_FOR_altivec_stvx_v4si;
7191 break;
7192 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7193 icode = CODE_FOR_altivec_stvx_v4sf;
7194 break;
7195 default:
7196 *expandedp = false;
7197 return NULL_RTX;
7198 }
7199
7200 arg0 = TREE_VALUE (arglist);
7201 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7202 op0 = expand_normal (arg0);
7203 op1 = expand_normal (arg1);
7204 mode0 = insn_data[icode].operand[0].mode;
7205 mode1 = insn_data[icode].operand[1].mode;
7206
7207 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7208 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7209 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7210 op1 = copy_to_mode_reg (mode1, op1);
7211
7212 pat = GEN_FCN (icode) (op0, op1);
7213 if (pat)
7214 emit_insn (pat);
7215
7216 *expandedp = true;
7217 return NULL_RTX;
7218 }
7219
7220 /* Expand the dst builtins. */
7221 static rtx
altivec_expand_dst_builtin(tree exp,rtx target ATTRIBUTE_UNUSED,bool * expandedp)7222 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7223 bool *expandedp)
7224 {
7225 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7226 tree arglist = TREE_OPERAND (exp, 1);
7227 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7228 tree arg0, arg1, arg2;
7229 enum machine_mode mode0, mode1, mode2;
7230 rtx pat, op0, op1, op2;
7231 struct builtin_description *d;
7232 size_t i;
7233
7234 *expandedp = false;
7235
7236 /* Handle DST variants. */
7237 d = (struct builtin_description *) bdesc_dst;
7238 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7239 if (d->code == fcode)
7240 {
7241 arg0 = TREE_VALUE (arglist);
7242 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7243 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7244 op0 = expand_normal (arg0);
7245 op1 = expand_normal (arg1);
7246 op2 = expand_normal (arg2);
7247 mode0 = insn_data[d->icode].operand[0].mode;
7248 mode1 = insn_data[d->icode].operand[1].mode;
7249 mode2 = insn_data[d->icode].operand[2].mode;
7250
7251 /* Invalid arguments, bail out before generating bad rtl. */
7252 if (arg0 == error_mark_node
7253 || arg1 == error_mark_node
7254 || arg2 == error_mark_node)
7255 return const0_rtx;
7256
7257 *expandedp = true;
7258 STRIP_NOPS (arg2);
7259 if (TREE_CODE (arg2) != INTEGER_CST
7260 || TREE_INT_CST_LOW (arg2) & ~0x3)
7261 {
7262 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7263 return const0_rtx;
7264 }
7265
7266 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7267 op0 = copy_to_mode_reg (Pmode, op0);
7268 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7269 op1 = copy_to_mode_reg (mode1, op1);
7270
7271 pat = GEN_FCN (d->icode) (op0, op1, op2);
7272 if (pat != 0)
7273 emit_insn (pat);
7274
7275 return NULL_RTX;
7276 }
7277
7278 return NULL_RTX;
7279 }
7280
7281 /* Expand vec_init builtin. */
7282 static rtx
altivec_expand_vec_init_builtin(tree type,tree arglist,rtx target)7283 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7284 {
7285 enum machine_mode tmode = TYPE_MODE (type);
7286 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7287 int i, n_elt = GET_MODE_NUNITS (tmode);
7288 rtvec v = rtvec_alloc (n_elt);
7289
7290 gcc_assert (VECTOR_MODE_P (tmode));
7291
7292 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7293 {
7294 rtx x = expand_normal (TREE_VALUE (arglist));
7295 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7296 }
7297
7298 gcc_assert (arglist == NULL);
7299
7300 if (!target || !register_operand (target, tmode))
7301 target = gen_reg_rtx (tmode);
7302
7303 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7304 return target;
7305 }
7306
7307 /* Return the integer constant in ARG. Constrain it to be in the range
7308 of the subparts of VEC_TYPE; issue an error if not. */
7309
7310 static int
get_element_number(tree vec_type,tree arg)7311 get_element_number (tree vec_type, tree arg)
7312 {
7313 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7314
7315 if (!host_integerp (arg, 1)
7316 || (elt = tree_low_cst (arg, 1), elt > max))
7317 {
7318 error ("selector must be an integer constant in the range 0..%wi", max);
7319 return 0;
7320 }
7321
7322 return elt;
7323 }
7324
7325 /* Expand vec_set builtin. */
7326 static rtx
altivec_expand_vec_set_builtin(tree arglist)7327 altivec_expand_vec_set_builtin (tree arglist)
7328 {
7329 enum machine_mode tmode, mode1;
7330 tree arg0, arg1, arg2;
7331 int elt;
7332 rtx op0, op1;
7333
7334 arg0 = TREE_VALUE (arglist);
7335 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7336 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7337
7338 tmode = TYPE_MODE (TREE_TYPE (arg0));
7339 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7340 gcc_assert (VECTOR_MODE_P (tmode));
7341
7342 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7343 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7344 elt = get_element_number (TREE_TYPE (arg0), arg2);
7345
7346 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7347 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7348
7349 op0 = force_reg (tmode, op0);
7350 op1 = force_reg (mode1, op1);
7351
7352 rs6000_expand_vector_set (op0, op1, elt);
7353
7354 return op0;
7355 }
7356
7357 /* Expand vec_ext builtin. */
7358 static rtx
altivec_expand_vec_ext_builtin(tree arglist,rtx target)7359 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7360 {
7361 enum machine_mode tmode, mode0;
7362 tree arg0, arg1;
7363 int elt;
7364 rtx op0;
7365
7366 arg0 = TREE_VALUE (arglist);
7367 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7368
7369 op0 = expand_normal (arg0);
7370 elt = get_element_number (TREE_TYPE (arg0), arg1);
7371
7372 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7373 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7374 gcc_assert (VECTOR_MODE_P (mode0));
7375
7376 op0 = force_reg (mode0, op0);
7377
7378 if (optimize || !target || !register_operand (target, tmode))
7379 target = gen_reg_rtx (tmode);
7380
7381 rs6000_expand_vector_extract (target, op0, elt);
7382
7383 return target;
7384 }
7385
7386 /* Expand the builtin in EXP and store the result in TARGET. Store
7387 true in *EXPANDEDP if we found a builtin to expand. */
7388 static rtx
altivec_expand_builtin(tree exp,rtx target,bool * expandedp)7389 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7390 {
7391 struct builtin_description *d;
7392 struct builtin_description_predicates *dp;
7393 size_t i;
7394 enum insn_code icode;
7395 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7396 tree arglist = TREE_OPERAND (exp, 1);
7397 tree arg0;
7398 rtx op0, pat;
7399 enum machine_mode tmode, mode0;
7400 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7401
7402 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7403 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7404 {
7405 *expandedp = true;
7406 error ("unresolved overload for Altivec builtin %qF", fndecl);
7407 return const0_rtx;
7408 }
7409
7410 target = altivec_expand_ld_builtin (exp, target, expandedp);
7411 if (*expandedp)
7412 return target;
7413
7414 target = altivec_expand_st_builtin (exp, target, expandedp);
7415 if (*expandedp)
7416 return target;
7417
7418 target = altivec_expand_dst_builtin (exp, target, expandedp);
7419 if (*expandedp)
7420 return target;
7421
7422 *expandedp = true;
7423
7424 switch (fcode)
7425 {
7426 case ALTIVEC_BUILTIN_STVX:
7427 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7428 case ALTIVEC_BUILTIN_STVEBX:
7429 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7430 case ALTIVEC_BUILTIN_STVEHX:
7431 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7432 case ALTIVEC_BUILTIN_STVEWX:
7433 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7434 case ALTIVEC_BUILTIN_STVXL:
7435 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7436
7437 case ALTIVEC_BUILTIN_MFVSCR:
7438 icode = CODE_FOR_altivec_mfvscr;
7439 tmode = insn_data[icode].operand[0].mode;
7440
7441 if (target == 0
7442 || GET_MODE (target) != tmode
7443 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7444 target = gen_reg_rtx (tmode);
7445
7446 pat = GEN_FCN (icode) (target);
7447 if (! pat)
7448 return 0;
7449 emit_insn (pat);
7450 return target;
7451
7452 case ALTIVEC_BUILTIN_MTVSCR:
7453 icode = CODE_FOR_altivec_mtvscr;
7454 arg0 = TREE_VALUE (arglist);
7455 op0 = expand_normal (arg0);
7456 mode0 = insn_data[icode].operand[0].mode;
7457
7458 /* If we got invalid arguments bail out before generating bad rtl. */
7459 if (arg0 == error_mark_node)
7460 return const0_rtx;
7461
7462 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7463 op0 = copy_to_mode_reg (mode0, op0);
7464
7465 pat = GEN_FCN (icode) (op0);
7466 if (pat)
7467 emit_insn (pat);
7468 return NULL_RTX;
7469
7470 case ALTIVEC_BUILTIN_DSSALL:
7471 emit_insn (gen_altivec_dssall ());
7472 return NULL_RTX;
7473
7474 case ALTIVEC_BUILTIN_DSS:
7475 icode = CODE_FOR_altivec_dss;
7476 arg0 = TREE_VALUE (arglist);
7477 STRIP_NOPS (arg0);
7478 op0 = expand_normal (arg0);
7479 mode0 = insn_data[icode].operand[0].mode;
7480
7481 /* If we got invalid arguments bail out before generating bad rtl. */
7482 if (arg0 == error_mark_node)
7483 return const0_rtx;
7484
7485 if (TREE_CODE (arg0) != INTEGER_CST
7486 || TREE_INT_CST_LOW (arg0) & ~0x3)
7487 {
7488 error ("argument to dss must be a 2-bit unsigned literal");
7489 return const0_rtx;
7490 }
7491
7492 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7493 op0 = copy_to_mode_reg (mode0, op0);
7494
7495 emit_insn (gen_altivec_dss (op0));
7496 return NULL_RTX;
7497
7498 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7499 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7500 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7501 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7502 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7503
7504 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7505 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7506 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7507 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7508 return altivec_expand_vec_set_builtin (arglist);
7509
7510 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7511 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7512 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7513 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7514 return altivec_expand_vec_ext_builtin (arglist, target);
7515
7516 default:
7517 break;
7518 /* Fall through. */
7519 }
7520
7521 /* Expand abs* operations. */
7522 d = (struct builtin_description *) bdesc_abs;
7523 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7524 if (d->code == fcode)
7525 return altivec_expand_abs_builtin (d->icode, arglist, target);
7526
7527 /* Expand the AltiVec predicates. */
7528 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7529 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7530 if (dp->code == fcode)
7531 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7532 arglist, target);
7533
7534 /* LV* are funky. We initialized them differently. */
7535 switch (fcode)
7536 {
7537 case ALTIVEC_BUILTIN_LVSL:
7538 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7539 arglist, target);
7540 case ALTIVEC_BUILTIN_LVSR:
7541 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7542 arglist, target);
7543 case ALTIVEC_BUILTIN_LVEBX:
7544 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7545 arglist, target);
7546 case ALTIVEC_BUILTIN_LVEHX:
7547 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7548 arglist, target);
7549 case ALTIVEC_BUILTIN_LVEWX:
7550 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7551 arglist, target);
7552 case ALTIVEC_BUILTIN_LVXL:
7553 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7554 arglist, target);
7555 case ALTIVEC_BUILTIN_LVX:
7556 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7557 arglist, target);
7558 default:
7559 break;
7560 /* Fall through. */
7561 }
7562
7563 *expandedp = false;
7564 return NULL_RTX;
7565 }
7566
7567 /* Binops that need to be initialized manually, but can be expanded
7568 automagically by rs6000_expand_binop_builtin. */
7569 static struct builtin_description bdesc_2arg_spe[] =
7570 {
7571 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7572 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7573 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7574 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7575 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7576 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7577 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7578 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7579 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7580 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7581 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7582 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7583 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7584 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7585 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7586 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7587 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7588 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7589 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7590 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7591 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7592 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7593 };
7594
7595 /* Expand the builtin in EXP and store the result in TARGET. Store
7596 true in *EXPANDEDP if we found a builtin to expand.
7597
7598 This expands the SPE builtins that are not simple unary and binary
7599 operations. */
7600 static rtx
spe_expand_builtin(tree exp,rtx target,bool * expandedp)7601 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7602 {
7603 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7604 tree arglist = TREE_OPERAND (exp, 1);
7605 tree arg1, arg0;
7606 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7607 enum insn_code icode;
7608 enum machine_mode tmode, mode0;
7609 rtx pat, op0;
7610 struct builtin_description *d;
7611 size_t i;
7612
7613 *expandedp = true;
7614
7615 /* Syntax check for a 5-bit unsigned immediate. */
7616 switch (fcode)
7617 {
7618 case SPE_BUILTIN_EVSTDD:
7619 case SPE_BUILTIN_EVSTDH:
7620 case SPE_BUILTIN_EVSTDW:
7621 case SPE_BUILTIN_EVSTWHE:
7622 case SPE_BUILTIN_EVSTWHO:
7623 case SPE_BUILTIN_EVSTWWE:
7624 case SPE_BUILTIN_EVSTWWO:
7625 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7626 if (TREE_CODE (arg1) != INTEGER_CST
7627 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7628 {
7629 error ("argument 2 must be a 5-bit unsigned literal");
7630 return const0_rtx;
7631 }
7632 break;
7633 default:
7634 break;
7635 }
7636
7637 /* The evsplat*i instructions are not quite generic. */
7638 switch (fcode)
7639 {
7640 case SPE_BUILTIN_EVSPLATFI:
7641 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7642 arglist, target);
7643 case SPE_BUILTIN_EVSPLATI:
7644 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7645 arglist, target);
7646 default:
7647 break;
7648 }
7649
7650 d = (struct builtin_description *) bdesc_2arg_spe;
7651 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7652 if (d->code == fcode)
7653 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7654
7655 d = (struct builtin_description *) bdesc_spe_predicates;
7656 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7657 if (d->code == fcode)
7658 return spe_expand_predicate_builtin (d->icode, arglist, target);
7659
7660 d = (struct builtin_description *) bdesc_spe_evsel;
7661 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7662 if (d->code == fcode)
7663 return spe_expand_evsel_builtin (d->icode, arglist, target);
7664
7665 switch (fcode)
7666 {
7667 case SPE_BUILTIN_EVSTDDX:
7668 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7669 case SPE_BUILTIN_EVSTDHX:
7670 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7671 case SPE_BUILTIN_EVSTDWX:
7672 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7673 case SPE_BUILTIN_EVSTWHEX:
7674 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7675 case SPE_BUILTIN_EVSTWHOX:
7676 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7677 case SPE_BUILTIN_EVSTWWEX:
7678 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7679 case SPE_BUILTIN_EVSTWWOX:
7680 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7681 case SPE_BUILTIN_EVSTDD:
7682 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7683 case SPE_BUILTIN_EVSTDH:
7684 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7685 case SPE_BUILTIN_EVSTDW:
7686 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7687 case SPE_BUILTIN_EVSTWHE:
7688 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7689 case SPE_BUILTIN_EVSTWHO:
7690 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7691 case SPE_BUILTIN_EVSTWWE:
7692 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7693 case SPE_BUILTIN_EVSTWWO:
7694 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7695 case SPE_BUILTIN_MFSPEFSCR:
7696 icode = CODE_FOR_spe_mfspefscr;
7697 tmode = insn_data[icode].operand[0].mode;
7698
7699 if (target == 0
7700 || GET_MODE (target) != tmode
7701 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7702 target = gen_reg_rtx (tmode);
7703
7704 pat = GEN_FCN (icode) (target);
7705 if (! pat)
7706 return 0;
7707 emit_insn (pat);
7708 return target;
7709 case SPE_BUILTIN_MTSPEFSCR:
7710 icode = CODE_FOR_spe_mtspefscr;
7711 arg0 = TREE_VALUE (arglist);
7712 op0 = expand_normal (arg0);
7713 mode0 = insn_data[icode].operand[0].mode;
7714
7715 if (arg0 == error_mark_node)
7716 return const0_rtx;
7717
7718 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7719 op0 = copy_to_mode_reg (mode0, op0);
7720
7721 pat = GEN_FCN (icode) (op0);
7722 if (pat)
7723 emit_insn (pat);
7724 return NULL_RTX;
7725 default:
7726 break;
7727 }
7728
7729 *expandedp = false;
7730 return NULL_RTX;
7731 }
7732
7733 static rtx
spe_expand_predicate_builtin(enum insn_code icode,tree arglist,rtx target)7734 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7735 {
7736 rtx pat, scratch, tmp;
7737 tree form = TREE_VALUE (arglist);
7738 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7739 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7740 rtx op0 = expand_normal (arg0);
7741 rtx op1 = expand_normal (arg1);
7742 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7743 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7744 int form_int;
7745 enum rtx_code code;
7746
7747 if (TREE_CODE (form) != INTEGER_CST)
7748 {
7749 error ("argument 1 of __builtin_spe_predicate must be a constant");
7750 return const0_rtx;
7751 }
7752 else
7753 form_int = TREE_INT_CST_LOW (form);
7754
7755 gcc_assert (mode0 == mode1);
7756
7757 if (arg0 == error_mark_node || arg1 == error_mark_node)
7758 return const0_rtx;
7759
7760 if (target == 0
7761 || GET_MODE (target) != SImode
7762 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7763 target = gen_reg_rtx (SImode);
7764
7765 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7766 op0 = copy_to_mode_reg (mode0, op0);
7767 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7768 op1 = copy_to_mode_reg (mode1, op1);
7769
7770 scratch = gen_reg_rtx (CCmode);
7771
7772 pat = GEN_FCN (icode) (scratch, op0, op1);
7773 if (! pat)
7774 return const0_rtx;
7775 emit_insn (pat);
7776
7777 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7778 _lower_. We use one compare, but look in different bits of the
7779 CR for each variant.
7780
7781 There are 2 elements in each SPE simd type (upper/lower). The CR
7782 bits are set as follows:
7783
7784 BIT0 | BIT 1 | BIT 2 | BIT 3
7785 U | L | (U | L) | (U & L)
7786
7787 So, for an "all" relationship, BIT 3 would be set.
7788 For an "any" relationship, BIT 2 would be set. Etc.
7789
7790 Following traditional nomenclature, these bits map to:
7791
7792 BIT0 | BIT 1 | BIT 2 | BIT 3
7793 LT | GT | EQ | OV
7794
7795 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7796 */
7797
7798 switch (form_int)
7799 {
7800 /* All variant. OV bit. */
7801 case 0:
7802 /* We need to get to the OV bit, which is the ORDERED bit. We
7803 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7804 that's ugly and will make validate_condition_mode die.
7805 So let's just use another pattern. */
7806 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7807 return target;
7808 /* Any variant. EQ bit. */
7809 case 1:
7810 code = EQ;
7811 break;
7812 /* Upper variant. LT bit. */
7813 case 2:
7814 code = LT;
7815 break;
7816 /* Lower variant. GT bit. */
7817 case 3:
7818 code = GT;
7819 break;
7820 default:
7821 error ("argument 1 of __builtin_spe_predicate is out of range");
7822 return const0_rtx;
7823 }
7824
7825 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7826 emit_move_insn (target, tmp);
7827
7828 return target;
7829 }
7830
7831 /* The evsel builtins look like this:
7832
7833 e = __builtin_spe_evsel_OP (a, b, c, d);
7834
7835 and work like this:
7836
7837 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7838 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7839 */
7840
7841 static rtx
spe_expand_evsel_builtin(enum insn_code icode,tree arglist,rtx target)7842 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7843 {
7844 rtx pat, scratch;
7845 tree arg0 = TREE_VALUE (arglist);
7846 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7847 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7848 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7849 rtx op0 = expand_normal (arg0);
7850 rtx op1 = expand_normal (arg1);
7851 rtx op2 = expand_normal (arg2);
7852 rtx op3 = expand_normal (arg3);
7853 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7854 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7855
7856 gcc_assert (mode0 == mode1);
7857
7858 if (arg0 == error_mark_node || arg1 == error_mark_node
7859 || arg2 == error_mark_node || arg3 == error_mark_node)
7860 return const0_rtx;
7861
7862 if (target == 0
7863 || GET_MODE (target) != mode0
7864 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7865 target = gen_reg_rtx (mode0);
7866
7867 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7868 op0 = copy_to_mode_reg (mode0, op0);
7869 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7870 op1 = copy_to_mode_reg (mode0, op1);
7871 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7872 op2 = copy_to_mode_reg (mode0, op2);
7873 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7874 op3 = copy_to_mode_reg (mode0, op3);
7875
7876 /* Generate the compare. */
7877 scratch = gen_reg_rtx (CCmode);
7878 pat = GEN_FCN (icode) (scratch, op0, op1);
7879 if (! pat)
7880 return const0_rtx;
7881 emit_insn (pat);
7882
7883 if (mode0 == V2SImode)
7884 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7885 else
7886 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7887
7888 return target;
7889 }
7890
7891 /* Expand an expression EXP that calls a built-in function,
7892 with result going to TARGET if that's convenient
7893 (and in mode MODE if that's convenient).
7894 SUBTARGET may be used as the target for computing one of EXP's operands.
7895 IGNORE is nonzero if the value is to be ignored. */
7896
7897 static rtx
rs6000_expand_builtin(tree exp,rtx target,rtx subtarget ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED,int ignore ATTRIBUTE_UNUSED)7898 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7899 enum machine_mode mode ATTRIBUTE_UNUSED,
7900 int ignore ATTRIBUTE_UNUSED)
7901 {
7902 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7903 tree arglist = TREE_OPERAND (exp, 1);
7904 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7905 struct builtin_description *d;
7906 size_t i;
7907 rtx ret;
7908 bool success;
7909
7910 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7911 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7912 {
7913 int icode = (int) CODE_FOR_altivec_lvsr;
7914 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7915 enum machine_mode mode = insn_data[icode].operand[1].mode;
7916 tree arg;
7917 rtx op, addr, pat;
7918
7919 gcc_assert (TARGET_ALTIVEC);
7920
7921 arg = TREE_VALUE (arglist);
7922 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7923 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7924 addr = memory_address (mode, op);
7925 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7926 op = addr;
7927 else
7928 {
7929 /* For the load case need to negate the address. */
7930 op = gen_reg_rtx (GET_MODE (addr));
7931 emit_insn (gen_rtx_SET (VOIDmode, op,
7932 gen_rtx_NEG (GET_MODE (addr), addr)));
7933 }
7934 op = gen_rtx_MEM (mode, op);
7935
7936 if (target == 0
7937 || GET_MODE (target) != tmode
7938 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7939 target = gen_reg_rtx (tmode);
7940
7941 /*pat = gen_altivec_lvsr (target, op);*/
7942 pat = GEN_FCN (icode) (target, op);
7943 if (!pat)
7944 return 0;
7945 emit_insn (pat);
7946
7947 return target;
7948 }
7949
7950 if (TARGET_ALTIVEC)
7951 {
7952 ret = altivec_expand_builtin (exp, target, &success);
7953
7954 if (success)
7955 return ret;
7956 }
7957 if (TARGET_SPE)
7958 {
7959 ret = spe_expand_builtin (exp, target, &success);
7960
7961 if (success)
7962 return ret;
7963 }
7964
7965 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7966
7967 /* Handle simple unary operations. */
7968 d = (struct builtin_description *) bdesc_1arg;
7969 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7970 if (d->code == fcode)
7971 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7972
7973 /* Handle simple binary operations. */
7974 d = (struct builtin_description *) bdesc_2arg;
7975 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7976 if (d->code == fcode)
7977 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7978
7979 /* Handle simple ternary operations. */
7980 d = (struct builtin_description *) bdesc_3arg;
7981 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7982 if (d->code == fcode)
7983 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7984
7985 gcc_unreachable ();
7986 }
7987
7988 static tree
build_opaque_vector_type(tree node,int nunits)7989 build_opaque_vector_type (tree node, int nunits)
7990 {
7991 node = copy_node (node);
7992 TYPE_MAIN_VARIANT (node) = node;
7993 return build_vector_type (node, nunits);
7994 }
7995
7996 static void
rs6000_init_builtins(void)7997 rs6000_init_builtins (void)
7998 {
7999 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8000 V2SF_type_node = build_vector_type (float_type_node, 2);
8001 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8002 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8003 V4SF_type_node = build_vector_type (float_type_node, 4);
8004 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8005 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8006
8007 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8008 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8009 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8010
8011 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8012 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8013 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8014 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8015
8016 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8017 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8018 'vector unsigned short'. */
8019
8020 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8021 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8022 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8023 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8024
8025 long_integer_type_internal_node = long_integer_type_node;
8026 long_unsigned_type_internal_node = long_unsigned_type_node;
8027 intQI_type_internal_node = intQI_type_node;
8028 uintQI_type_internal_node = unsigned_intQI_type_node;
8029 intHI_type_internal_node = intHI_type_node;
8030 uintHI_type_internal_node = unsigned_intHI_type_node;
8031 intSI_type_internal_node = intSI_type_node;
8032 uintSI_type_internal_node = unsigned_intSI_type_node;
8033 float_type_internal_node = float_type_node;
8034 void_type_internal_node = void_type_node;
8035
8036 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8037 get_identifier ("__bool char"),
8038 bool_char_type_node));
8039 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8040 get_identifier ("__bool short"),
8041 bool_short_type_node));
8042 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8043 get_identifier ("__bool int"),
8044 bool_int_type_node));
8045 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8046 get_identifier ("__pixel"),
8047 pixel_type_node));
8048
8049 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8050 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8051 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8052 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8053
8054 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8055 get_identifier ("__vector unsigned char"),
8056 unsigned_V16QI_type_node));
8057 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8058 get_identifier ("__vector signed char"),
8059 V16QI_type_node));
8060 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8061 get_identifier ("__vector __bool char"),
8062 bool_V16QI_type_node));
8063
8064 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8065 get_identifier ("__vector unsigned short"),
8066 unsigned_V8HI_type_node));
8067 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8068 get_identifier ("__vector signed short"),
8069 V8HI_type_node));
8070 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8071 get_identifier ("__vector __bool short"),
8072 bool_V8HI_type_node));
8073
8074 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8075 get_identifier ("__vector unsigned int"),
8076 unsigned_V4SI_type_node));
8077 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8078 get_identifier ("__vector signed int"),
8079 V4SI_type_node));
8080 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8081 get_identifier ("__vector __bool int"),
8082 bool_V4SI_type_node));
8083
8084 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8085 get_identifier ("__vector float"),
8086 V4SF_type_node));
8087 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8088 get_identifier ("__vector __pixel"),
8089 pixel_V8HI_type_node));
8090
8091 if (TARGET_SPE)
8092 spe_init_builtins ();
8093 if (TARGET_ALTIVEC)
8094 altivec_init_builtins ();
8095 if (TARGET_ALTIVEC || TARGET_SPE)
8096 rs6000_common_init_builtins ();
8097
8098 #if TARGET_XCOFF
8099 /* AIX libm provides clog as __clog. */
8100 if (built_in_decls [BUILT_IN_CLOG])
8101 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8102 #endif
8103 }
8104
8105 /* Search through a set of builtins and enable the mask bits.
8106 DESC is an array of builtins.
8107 SIZE is the total number of builtins.
8108 START is the builtin enum at which to start.
8109 END is the builtin enum at which to end. */
8110 static void
enable_mask_for_builtins(struct builtin_description * desc,int size,enum rs6000_builtins start,enum rs6000_builtins end)8111 enable_mask_for_builtins (struct builtin_description *desc, int size,
8112 enum rs6000_builtins start,
8113 enum rs6000_builtins end)
8114 {
8115 int i;
8116
8117 for (i = 0; i < size; ++i)
8118 if (desc[i].code == start)
8119 break;
8120
8121 if (i == size)
8122 return;
8123
8124 for (; i < size; ++i)
8125 {
8126 /* Flip all the bits on. */
8127 desc[i].mask = target_flags;
8128 if (desc[i].code == end)
8129 break;
8130 }
8131 }
8132
8133 static void
spe_init_builtins(void)8134 spe_init_builtins (void)
8135 {
8136 tree endlink = void_list_node;
8137 tree puint_type_node = build_pointer_type (unsigned_type_node);
8138 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8139 struct builtin_description *d;
8140 size_t i;
8141
8142 tree v2si_ftype_4_v2si
8143 = build_function_type
8144 (opaque_V2SI_type_node,
8145 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8146 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8147 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8148 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8149 endlink)))));
8150
8151 tree v2sf_ftype_4_v2sf
8152 = build_function_type
8153 (opaque_V2SF_type_node,
8154 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8155 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8156 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8157 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8158 endlink)))));
8159
8160 tree int_ftype_int_v2si_v2si
8161 = build_function_type
8162 (integer_type_node,
8163 tree_cons (NULL_TREE, integer_type_node,
8164 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8165 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8166 endlink))));
8167
8168 tree int_ftype_int_v2sf_v2sf
8169 = build_function_type
8170 (integer_type_node,
8171 tree_cons (NULL_TREE, integer_type_node,
8172 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8173 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8174 endlink))));
8175
8176 tree void_ftype_v2si_puint_int
8177 = build_function_type (void_type_node,
8178 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8179 tree_cons (NULL_TREE, puint_type_node,
8180 tree_cons (NULL_TREE,
8181 integer_type_node,
8182 endlink))));
8183
8184 tree void_ftype_v2si_puint_char
8185 = build_function_type (void_type_node,
8186 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8187 tree_cons (NULL_TREE, puint_type_node,
8188 tree_cons (NULL_TREE,
8189 char_type_node,
8190 endlink))));
8191
8192 tree void_ftype_v2si_pv2si_int
8193 = build_function_type (void_type_node,
8194 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8195 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8196 tree_cons (NULL_TREE,
8197 integer_type_node,
8198 endlink))));
8199
8200 tree void_ftype_v2si_pv2si_char
8201 = build_function_type (void_type_node,
8202 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8203 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8204 tree_cons (NULL_TREE,
8205 char_type_node,
8206 endlink))));
8207
8208 tree void_ftype_int
8209 = build_function_type (void_type_node,
8210 tree_cons (NULL_TREE, integer_type_node, endlink));
8211
8212 tree int_ftype_void
8213 = build_function_type (integer_type_node, endlink);
8214
8215 tree v2si_ftype_pv2si_int
8216 = build_function_type (opaque_V2SI_type_node,
8217 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8218 tree_cons (NULL_TREE, integer_type_node,
8219 endlink)));
8220
8221 tree v2si_ftype_puint_int
8222 = build_function_type (opaque_V2SI_type_node,
8223 tree_cons (NULL_TREE, puint_type_node,
8224 tree_cons (NULL_TREE, integer_type_node,
8225 endlink)));
8226
8227 tree v2si_ftype_pushort_int
8228 = build_function_type (opaque_V2SI_type_node,
8229 tree_cons (NULL_TREE, pushort_type_node,
8230 tree_cons (NULL_TREE, integer_type_node,
8231 endlink)));
8232
8233 tree v2si_ftype_signed_char
8234 = build_function_type (opaque_V2SI_type_node,
8235 tree_cons (NULL_TREE, signed_char_type_node,
8236 endlink));
8237
8238 /* The initialization of the simple binary and unary builtins is
8239 done in rs6000_common_init_builtins, but we have to enable the
8240 mask bits here manually because we have run out of `target_flags'
8241 bits. We really need to redesign this mask business. */
8242
8243 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8244 ARRAY_SIZE (bdesc_2arg),
8245 SPE_BUILTIN_EVADDW,
8246 SPE_BUILTIN_EVXOR);
8247 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8248 ARRAY_SIZE (bdesc_1arg),
8249 SPE_BUILTIN_EVABS,
8250 SPE_BUILTIN_EVSUBFUSIAAW);
8251 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8252 ARRAY_SIZE (bdesc_spe_predicates),
8253 SPE_BUILTIN_EVCMPEQ,
8254 SPE_BUILTIN_EVFSTSTLT);
8255 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8256 ARRAY_SIZE (bdesc_spe_evsel),
8257 SPE_BUILTIN_EVSEL_CMPGTS,
8258 SPE_BUILTIN_EVSEL_FSTSTEQ);
8259
8260 (*lang_hooks.decls.pushdecl)
8261 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8262 opaque_V2SI_type_node));
8263
8264 /* Initialize irregular SPE builtins. */
8265
8266 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8267 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8268 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8269 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8270 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8271 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8272 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8273 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8274 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8275 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8276 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8277 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8278 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8279 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8280 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8281 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8282 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8283 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8284
8285 /* Loads. */
8286 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8287 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8288 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8289 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8290 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8291 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8292 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8293 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8294 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8295 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8296 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8297 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8298 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8299 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8300 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8301 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8302 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8303 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8304 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8305 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8306 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8307 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8308
8309 /* Predicates. */
8310 d = (struct builtin_description *) bdesc_spe_predicates;
8311 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8312 {
8313 tree type;
8314
8315 switch (insn_data[d->icode].operand[1].mode)
8316 {
8317 case V2SImode:
8318 type = int_ftype_int_v2si_v2si;
8319 break;
8320 case V2SFmode:
8321 type = int_ftype_int_v2sf_v2sf;
8322 break;
8323 default:
8324 gcc_unreachable ();
8325 }
8326
8327 def_builtin (d->mask, d->name, type, d->code);
8328 }
8329
8330 /* Evsel predicates. */
8331 d = (struct builtin_description *) bdesc_spe_evsel;
8332 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8333 {
8334 tree type;
8335
8336 switch (insn_data[d->icode].operand[1].mode)
8337 {
8338 case V2SImode:
8339 type = v2si_ftype_4_v2si;
8340 break;
8341 case V2SFmode:
8342 type = v2sf_ftype_4_v2sf;
8343 break;
8344 default:
8345 gcc_unreachable ();
8346 }
8347
8348 def_builtin (d->mask, d->name, type, d->code);
8349 }
8350 }
8351
8352 static void
altivec_init_builtins(void)8353 altivec_init_builtins (void)
8354 {
8355 struct builtin_description *d;
8356 struct builtin_description_predicates *dp;
8357 size_t i;
8358 tree ftype;
8359
8360 tree pfloat_type_node = build_pointer_type (float_type_node);
8361 tree pint_type_node = build_pointer_type (integer_type_node);
8362 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8363 tree pchar_type_node = build_pointer_type (char_type_node);
8364
8365 tree pvoid_type_node = build_pointer_type (void_type_node);
8366
8367 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8368 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8369 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8370 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8371
8372 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8373
8374 tree int_ftype_opaque
8375 = build_function_type_list (integer_type_node,
8376 opaque_V4SI_type_node, NULL_TREE);
8377
8378 tree opaque_ftype_opaque_int
8379 = build_function_type_list (opaque_V4SI_type_node,
8380 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8381 tree opaque_ftype_opaque_opaque_int
8382 = build_function_type_list (opaque_V4SI_type_node,
8383 opaque_V4SI_type_node, opaque_V4SI_type_node,
8384 integer_type_node, NULL_TREE);
8385 tree int_ftype_int_opaque_opaque
8386 = build_function_type_list (integer_type_node,
8387 integer_type_node, opaque_V4SI_type_node,
8388 opaque_V4SI_type_node, NULL_TREE);
8389 tree int_ftype_int_v4si_v4si
8390 = build_function_type_list (integer_type_node,
8391 integer_type_node, V4SI_type_node,
8392 V4SI_type_node, NULL_TREE);
8393 tree v4sf_ftype_pcfloat
8394 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8395 tree void_ftype_pfloat_v4sf
8396 = build_function_type_list (void_type_node,
8397 pfloat_type_node, V4SF_type_node, NULL_TREE);
8398 tree v4si_ftype_pcint
8399 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8400 tree void_ftype_pint_v4si
8401 = build_function_type_list (void_type_node,
8402 pint_type_node, V4SI_type_node, NULL_TREE);
8403 tree v8hi_ftype_pcshort
8404 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8405 tree void_ftype_pshort_v8hi
8406 = build_function_type_list (void_type_node,
8407 pshort_type_node, V8HI_type_node, NULL_TREE);
8408 tree v16qi_ftype_pcchar
8409 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8410 tree void_ftype_pchar_v16qi
8411 = build_function_type_list (void_type_node,
8412 pchar_type_node, V16QI_type_node, NULL_TREE);
8413 tree void_ftype_v4si
8414 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8415 tree v8hi_ftype_void
8416 = build_function_type (V8HI_type_node, void_list_node);
8417 tree void_ftype_void
8418 = build_function_type (void_type_node, void_list_node);
8419 tree void_ftype_int
8420 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8421
8422 tree opaque_ftype_long_pcvoid
8423 = build_function_type_list (opaque_V4SI_type_node,
8424 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8425 tree v16qi_ftype_long_pcvoid
8426 = build_function_type_list (V16QI_type_node,
8427 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8428 tree v8hi_ftype_long_pcvoid
8429 = build_function_type_list (V8HI_type_node,
8430 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8431 tree v4si_ftype_long_pcvoid
8432 = build_function_type_list (V4SI_type_node,
8433 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8434
8435 tree void_ftype_opaque_long_pvoid
8436 = build_function_type_list (void_type_node,
8437 opaque_V4SI_type_node, long_integer_type_node,
8438 pvoid_type_node, NULL_TREE);
8439 tree void_ftype_v4si_long_pvoid
8440 = build_function_type_list (void_type_node,
8441 V4SI_type_node, long_integer_type_node,
8442 pvoid_type_node, NULL_TREE);
8443 tree void_ftype_v16qi_long_pvoid
8444 = build_function_type_list (void_type_node,
8445 V16QI_type_node, long_integer_type_node,
8446 pvoid_type_node, NULL_TREE);
8447 tree void_ftype_v8hi_long_pvoid
8448 = build_function_type_list (void_type_node,
8449 V8HI_type_node, long_integer_type_node,
8450 pvoid_type_node, NULL_TREE);
8451 tree int_ftype_int_v8hi_v8hi
8452 = build_function_type_list (integer_type_node,
8453 integer_type_node, V8HI_type_node,
8454 V8HI_type_node, NULL_TREE);
8455 tree int_ftype_int_v16qi_v16qi
8456 = build_function_type_list (integer_type_node,
8457 integer_type_node, V16QI_type_node,
8458 V16QI_type_node, NULL_TREE);
8459 tree int_ftype_int_v4sf_v4sf
8460 = build_function_type_list (integer_type_node,
8461 integer_type_node, V4SF_type_node,
8462 V4SF_type_node, NULL_TREE);
8463 tree v4si_ftype_v4si
8464 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8465 tree v8hi_ftype_v8hi
8466 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8467 tree v16qi_ftype_v16qi
8468 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8469 tree v4sf_ftype_v4sf
8470 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8471 tree void_ftype_pcvoid_int_int
8472 = build_function_type_list (void_type_node,
8473 pcvoid_type_node, integer_type_node,
8474 integer_type_node, NULL_TREE);
8475
8476 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8477 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8478 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8479 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8480 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8481 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8482 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8483 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8484 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8485 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8486 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8487 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8488 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8489 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8490 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8491 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8492 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8493 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8494 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8495 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8496 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8497 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8498 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8499 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8500 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8501 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8502 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8503 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8504 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8505 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8506 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8507 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8508 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8509 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8510 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8511 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8512 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8513 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8514 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8515 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8516 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8517 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8518 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8519 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8520 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8521 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8522
8523 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8524
8525 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8526 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8527 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8528 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8529 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8530 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8531 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8532 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8533 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8534 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8535
8536 /* Add the DST variants. */
8537 d = (struct builtin_description *) bdesc_dst;
8538 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8539 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8540
8541 /* Initialize the predicates. */
8542 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8543 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8544 {
8545 enum machine_mode mode1;
8546 tree type;
8547 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8548 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8549
8550 if (is_overloaded)
8551 mode1 = VOIDmode;
8552 else
8553 mode1 = insn_data[dp->icode].operand[1].mode;
8554
8555 switch (mode1)
8556 {
8557 case VOIDmode:
8558 type = int_ftype_int_opaque_opaque;
8559 break;
8560 case V4SImode:
8561 type = int_ftype_int_v4si_v4si;
8562 break;
8563 case V8HImode:
8564 type = int_ftype_int_v8hi_v8hi;
8565 break;
8566 case V16QImode:
8567 type = int_ftype_int_v16qi_v16qi;
8568 break;
8569 case V4SFmode:
8570 type = int_ftype_int_v4sf_v4sf;
8571 break;
8572 default:
8573 gcc_unreachable ();
8574 }
8575
8576 def_builtin (dp->mask, dp->name, type, dp->code);
8577 }
8578
8579 /* Initialize the abs* operators. */
8580 d = (struct builtin_description *) bdesc_abs;
8581 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8582 {
8583 enum machine_mode mode0;
8584 tree type;
8585
8586 mode0 = insn_data[d->icode].operand[0].mode;
8587
8588 switch (mode0)
8589 {
8590 case V4SImode:
8591 type = v4si_ftype_v4si;
8592 break;
8593 case V8HImode:
8594 type = v8hi_ftype_v8hi;
8595 break;
8596 case V16QImode:
8597 type = v16qi_ftype_v16qi;
8598 break;
8599 case V4SFmode:
8600 type = v4sf_ftype_v4sf;
8601 break;
8602 default:
8603 gcc_unreachable ();
8604 }
8605
8606 def_builtin (d->mask, d->name, type, d->code);
8607 }
8608
8609 if (TARGET_ALTIVEC)
8610 {
8611 tree decl;
8612
8613 /* Initialize target builtin that implements
8614 targetm.vectorize.builtin_mask_for_load. */
8615
8616 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8617 v16qi_ftype_long_pcvoid,
8618 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8619 BUILT_IN_MD, NULL,
8620 tree_cons (get_identifier ("const"),
8621 NULL_TREE, NULL_TREE));
8622 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8623 altivec_builtin_mask_for_load = decl;
8624 }
8625
8626 /* Access to the vec_init patterns. */
8627 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8628 integer_type_node, integer_type_node,
8629 integer_type_node, NULL_TREE);
8630 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8631 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8632
8633 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8634 short_integer_type_node,
8635 short_integer_type_node,
8636 short_integer_type_node,
8637 short_integer_type_node,
8638 short_integer_type_node,
8639 short_integer_type_node,
8640 short_integer_type_node, NULL_TREE);
8641 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8642 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8643
8644 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8645 char_type_node, char_type_node,
8646 char_type_node, char_type_node,
8647 char_type_node, char_type_node,
8648 char_type_node, char_type_node,
8649 char_type_node, char_type_node,
8650 char_type_node, char_type_node,
8651 char_type_node, char_type_node,
8652 char_type_node, NULL_TREE);
8653 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8654 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8655
8656 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8657 float_type_node, float_type_node,
8658 float_type_node, NULL_TREE);
8659 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8660 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8661
8662 /* Access to the vec_set patterns. */
8663 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8664 intSI_type_node,
8665 integer_type_node, NULL_TREE);
8666 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8667 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8668
8669 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8670 intHI_type_node,
8671 integer_type_node, NULL_TREE);
8672 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8673 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8674
8675 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8676 intQI_type_node,
8677 integer_type_node, NULL_TREE);
8678 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8679 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8680
8681 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8682 float_type_node,
8683 integer_type_node, NULL_TREE);
8684 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8685 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8686
8687 /* Access to the vec_extract patterns. */
8688 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8689 integer_type_node, NULL_TREE);
8690 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8691 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8692
8693 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8694 integer_type_node, NULL_TREE);
8695 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8696 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8697
8698 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8699 integer_type_node, NULL_TREE);
8700 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8701 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8702
8703 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8704 integer_type_node, NULL_TREE);
8705 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8706 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8707 }
8708
8709 static void
rs6000_common_init_builtins(void)8710 rs6000_common_init_builtins (void)
8711 {
8712 struct builtin_description *d;
8713 size_t i;
8714
8715 tree v4sf_ftype_v4sf_v4sf_v16qi
8716 = build_function_type_list (V4SF_type_node,
8717 V4SF_type_node, V4SF_type_node,
8718 V16QI_type_node, NULL_TREE);
8719 tree v4si_ftype_v4si_v4si_v16qi
8720 = build_function_type_list (V4SI_type_node,
8721 V4SI_type_node, V4SI_type_node,
8722 V16QI_type_node, NULL_TREE);
8723 tree v8hi_ftype_v8hi_v8hi_v16qi
8724 = build_function_type_list (V8HI_type_node,
8725 V8HI_type_node, V8HI_type_node,
8726 V16QI_type_node, NULL_TREE);
8727 tree v16qi_ftype_v16qi_v16qi_v16qi
8728 = build_function_type_list (V16QI_type_node,
8729 V16QI_type_node, V16QI_type_node,
8730 V16QI_type_node, NULL_TREE);
8731 tree v4si_ftype_int
8732 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8733 tree v8hi_ftype_int
8734 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8735 tree v16qi_ftype_int
8736 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8737 tree v8hi_ftype_v16qi
8738 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8739 tree v4sf_ftype_v4sf
8740 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8741
8742 tree v2si_ftype_v2si_v2si
8743 = build_function_type_list (opaque_V2SI_type_node,
8744 opaque_V2SI_type_node,
8745 opaque_V2SI_type_node, NULL_TREE);
8746
8747 tree v2sf_ftype_v2sf_v2sf
8748 = build_function_type_list (opaque_V2SF_type_node,
8749 opaque_V2SF_type_node,
8750 opaque_V2SF_type_node, NULL_TREE);
8751
8752 tree v2si_ftype_int_int
8753 = build_function_type_list (opaque_V2SI_type_node,
8754 integer_type_node, integer_type_node,
8755 NULL_TREE);
8756
8757 tree opaque_ftype_opaque
8758 = build_function_type_list (opaque_V4SI_type_node,
8759 opaque_V4SI_type_node, NULL_TREE);
8760
8761 tree v2si_ftype_v2si
8762 = build_function_type_list (opaque_V2SI_type_node,
8763 opaque_V2SI_type_node, NULL_TREE);
8764
8765 tree v2sf_ftype_v2sf
8766 = build_function_type_list (opaque_V2SF_type_node,
8767 opaque_V2SF_type_node, NULL_TREE);
8768
8769 tree v2sf_ftype_v2si
8770 = build_function_type_list (opaque_V2SF_type_node,
8771 opaque_V2SI_type_node, NULL_TREE);
8772
8773 tree v2si_ftype_v2sf
8774 = build_function_type_list (opaque_V2SI_type_node,
8775 opaque_V2SF_type_node, NULL_TREE);
8776
8777 tree v2si_ftype_v2si_char
8778 = build_function_type_list (opaque_V2SI_type_node,
8779 opaque_V2SI_type_node,
8780 char_type_node, NULL_TREE);
8781
8782 tree v2si_ftype_int_char
8783 = build_function_type_list (opaque_V2SI_type_node,
8784 integer_type_node, char_type_node, NULL_TREE);
8785
8786 tree v2si_ftype_char
8787 = build_function_type_list (opaque_V2SI_type_node,
8788 char_type_node, NULL_TREE);
8789
8790 tree int_ftype_int_int
8791 = build_function_type_list (integer_type_node,
8792 integer_type_node, integer_type_node,
8793 NULL_TREE);
8794
8795 tree opaque_ftype_opaque_opaque
8796 = build_function_type_list (opaque_V4SI_type_node,
8797 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8798 tree v4si_ftype_v4si_v4si
8799 = build_function_type_list (V4SI_type_node,
8800 V4SI_type_node, V4SI_type_node, NULL_TREE);
8801 tree v4sf_ftype_v4si_int
8802 = build_function_type_list (V4SF_type_node,
8803 V4SI_type_node, integer_type_node, NULL_TREE);
8804 tree v4si_ftype_v4sf_int
8805 = build_function_type_list (V4SI_type_node,
8806 V4SF_type_node, integer_type_node, NULL_TREE);
8807 tree v4si_ftype_v4si_int
8808 = build_function_type_list (V4SI_type_node,
8809 V4SI_type_node, integer_type_node, NULL_TREE);
8810 tree v8hi_ftype_v8hi_int
8811 = build_function_type_list (V8HI_type_node,
8812 V8HI_type_node, integer_type_node, NULL_TREE);
8813 tree v16qi_ftype_v16qi_int
8814 = build_function_type_list (V16QI_type_node,
8815 V16QI_type_node, integer_type_node, NULL_TREE);
8816 tree v16qi_ftype_v16qi_v16qi_int
8817 = build_function_type_list (V16QI_type_node,
8818 V16QI_type_node, V16QI_type_node,
8819 integer_type_node, NULL_TREE);
8820 tree v8hi_ftype_v8hi_v8hi_int
8821 = build_function_type_list (V8HI_type_node,
8822 V8HI_type_node, V8HI_type_node,
8823 integer_type_node, NULL_TREE);
8824 tree v4si_ftype_v4si_v4si_int
8825 = build_function_type_list (V4SI_type_node,
8826 V4SI_type_node, V4SI_type_node,
8827 integer_type_node, NULL_TREE);
8828 tree v4sf_ftype_v4sf_v4sf_int
8829 = build_function_type_list (V4SF_type_node,
8830 V4SF_type_node, V4SF_type_node,
8831 integer_type_node, NULL_TREE);
8832 tree v4sf_ftype_v4sf_v4sf
8833 = build_function_type_list (V4SF_type_node,
8834 V4SF_type_node, V4SF_type_node, NULL_TREE);
8835 tree opaque_ftype_opaque_opaque_opaque
8836 = build_function_type_list (opaque_V4SI_type_node,
8837 opaque_V4SI_type_node, opaque_V4SI_type_node,
8838 opaque_V4SI_type_node, NULL_TREE);
8839 tree v4sf_ftype_v4sf_v4sf_v4si
8840 = build_function_type_list (V4SF_type_node,
8841 V4SF_type_node, V4SF_type_node,
8842 V4SI_type_node, NULL_TREE);
8843 tree v4sf_ftype_v4sf_v4sf_v4sf
8844 = build_function_type_list (V4SF_type_node,
8845 V4SF_type_node, V4SF_type_node,
8846 V4SF_type_node, NULL_TREE);
8847 tree v4si_ftype_v4si_v4si_v4si
8848 = build_function_type_list (V4SI_type_node,
8849 V4SI_type_node, V4SI_type_node,
8850 V4SI_type_node, NULL_TREE);
8851 tree v8hi_ftype_v8hi_v8hi
8852 = build_function_type_list (V8HI_type_node,
8853 V8HI_type_node, V8HI_type_node, NULL_TREE);
8854 tree v8hi_ftype_v8hi_v8hi_v8hi
8855 = build_function_type_list (V8HI_type_node,
8856 V8HI_type_node, V8HI_type_node,
8857 V8HI_type_node, NULL_TREE);
8858 tree v4si_ftype_v8hi_v8hi_v4si
8859 = build_function_type_list (V4SI_type_node,
8860 V8HI_type_node, V8HI_type_node,
8861 V4SI_type_node, NULL_TREE);
8862 tree v4si_ftype_v16qi_v16qi_v4si
8863 = build_function_type_list (V4SI_type_node,
8864 V16QI_type_node, V16QI_type_node,
8865 V4SI_type_node, NULL_TREE);
8866 tree v16qi_ftype_v16qi_v16qi
8867 = build_function_type_list (V16QI_type_node,
8868 V16QI_type_node, V16QI_type_node, NULL_TREE);
8869 tree v4si_ftype_v4sf_v4sf
8870 = build_function_type_list (V4SI_type_node,
8871 V4SF_type_node, V4SF_type_node, NULL_TREE);
8872 tree v8hi_ftype_v16qi_v16qi
8873 = build_function_type_list (V8HI_type_node,
8874 V16QI_type_node, V16QI_type_node, NULL_TREE);
8875 tree v4si_ftype_v8hi_v8hi
8876 = build_function_type_list (V4SI_type_node,
8877 V8HI_type_node, V8HI_type_node, NULL_TREE);
8878 tree v8hi_ftype_v4si_v4si
8879 = build_function_type_list (V8HI_type_node,
8880 V4SI_type_node, V4SI_type_node, NULL_TREE);
8881 tree v16qi_ftype_v8hi_v8hi
8882 = build_function_type_list (V16QI_type_node,
8883 V8HI_type_node, V8HI_type_node, NULL_TREE);
8884 tree v4si_ftype_v16qi_v4si
8885 = build_function_type_list (V4SI_type_node,
8886 V16QI_type_node, V4SI_type_node, NULL_TREE);
8887 tree v4si_ftype_v16qi_v16qi
8888 = build_function_type_list (V4SI_type_node,
8889 V16QI_type_node, V16QI_type_node, NULL_TREE);
8890 tree v4si_ftype_v8hi_v4si
8891 = build_function_type_list (V4SI_type_node,
8892 V8HI_type_node, V4SI_type_node, NULL_TREE);
8893 tree v4si_ftype_v8hi
8894 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8895 tree int_ftype_v4si_v4si
8896 = build_function_type_list (integer_type_node,
8897 V4SI_type_node, V4SI_type_node, NULL_TREE);
8898 tree int_ftype_v4sf_v4sf
8899 = build_function_type_list (integer_type_node,
8900 V4SF_type_node, V4SF_type_node, NULL_TREE);
8901 tree int_ftype_v16qi_v16qi
8902 = build_function_type_list (integer_type_node,
8903 V16QI_type_node, V16QI_type_node, NULL_TREE);
8904 tree int_ftype_v8hi_v8hi
8905 = build_function_type_list (integer_type_node,
8906 V8HI_type_node, V8HI_type_node, NULL_TREE);
8907
8908 /* Add the simple ternary operators. */
8909 d = (struct builtin_description *) bdesc_3arg;
8910 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8911 {
8912 enum machine_mode mode0, mode1, mode2, mode3;
8913 tree type;
8914 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8915 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8916
8917 if (is_overloaded)
8918 {
8919 mode0 = VOIDmode;
8920 mode1 = VOIDmode;
8921 mode2 = VOIDmode;
8922 mode3 = VOIDmode;
8923 }
8924 else
8925 {
8926 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8927 continue;
8928
8929 mode0 = insn_data[d->icode].operand[0].mode;
8930 mode1 = insn_data[d->icode].operand[1].mode;
8931 mode2 = insn_data[d->icode].operand[2].mode;
8932 mode3 = insn_data[d->icode].operand[3].mode;
8933 }
8934
8935 /* When all four are of the same mode. */
8936 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8937 {
8938 switch (mode0)
8939 {
8940 case VOIDmode:
8941 type = opaque_ftype_opaque_opaque_opaque;
8942 break;
8943 case V4SImode:
8944 type = v4si_ftype_v4si_v4si_v4si;
8945 break;
8946 case V4SFmode:
8947 type = v4sf_ftype_v4sf_v4sf_v4sf;
8948 break;
8949 case V8HImode:
8950 type = v8hi_ftype_v8hi_v8hi_v8hi;
8951 break;
8952 case V16QImode:
8953 type = v16qi_ftype_v16qi_v16qi_v16qi;
8954 break;
8955 default:
8956 gcc_unreachable ();
8957 }
8958 }
8959 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8960 {
8961 switch (mode0)
8962 {
8963 case V4SImode:
8964 type = v4si_ftype_v4si_v4si_v16qi;
8965 break;
8966 case V4SFmode:
8967 type = v4sf_ftype_v4sf_v4sf_v16qi;
8968 break;
8969 case V8HImode:
8970 type = v8hi_ftype_v8hi_v8hi_v16qi;
8971 break;
8972 case V16QImode:
8973 type = v16qi_ftype_v16qi_v16qi_v16qi;
8974 break;
8975 default:
8976 gcc_unreachable ();
8977 }
8978 }
8979 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8980 && mode3 == V4SImode)
8981 type = v4si_ftype_v16qi_v16qi_v4si;
8982 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8983 && mode3 == V4SImode)
8984 type = v4si_ftype_v8hi_v8hi_v4si;
8985 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8986 && mode3 == V4SImode)
8987 type = v4sf_ftype_v4sf_v4sf_v4si;
8988
8989 /* vchar, vchar, vchar, 4 bit literal. */
8990 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8991 && mode3 == QImode)
8992 type = v16qi_ftype_v16qi_v16qi_int;
8993
8994 /* vshort, vshort, vshort, 4 bit literal. */
8995 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8996 && mode3 == QImode)
8997 type = v8hi_ftype_v8hi_v8hi_int;
8998
8999 /* vint, vint, vint, 4 bit literal. */
9000 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9001 && mode3 == QImode)
9002 type = v4si_ftype_v4si_v4si_int;
9003
9004 /* vfloat, vfloat, vfloat, 4 bit literal. */
9005 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9006 && mode3 == QImode)
9007 type = v4sf_ftype_v4sf_v4sf_int;
9008
9009 else
9010 gcc_unreachable ();
9011
9012 def_builtin (d->mask, d->name, type, d->code);
9013 }
9014
9015 /* Add the simple binary operators. */
9016 d = (struct builtin_description *) bdesc_2arg;
9017 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9018 {
9019 enum machine_mode mode0, mode1, mode2;
9020 tree type;
9021 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9022 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9023
9024 if (is_overloaded)
9025 {
9026 mode0 = VOIDmode;
9027 mode1 = VOIDmode;
9028 mode2 = VOIDmode;
9029 }
9030 else
9031 {
9032 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9033 continue;
9034
9035 mode0 = insn_data[d->icode].operand[0].mode;
9036 mode1 = insn_data[d->icode].operand[1].mode;
9037 mode2 = insn_data[d->icode].operand[2].mode;
9038 }
9039
9040 /* When all three operands are of the same mode. */
9041 if (mode0 == mode1 && mode1 == mode2)
9042 {
9043 switch (mode0)
9044 {
9045 case VOIDmode:
9046 type = opaque_ftype_opaque_opaque;
9047 break;
9048 case V4SFmode:
9049 type = v4sf_ftype_v4sf_v4sf;
9050 break;
9051 case V4SImode:
9052 type = v4si_ftype_v4si_v4si;
9053 break;
9054 case V16QImode:
9055 type = v16qi_ftype_v16qi_v16qi;
9056 break;
9057 case V8HImode:
9058 type = v8hi_ftype_v8hi_v8hi;
9059 break;
9060 case V2SImode:
9061 type = v2si_ftype_v2si_v2si;
9062 break;
9063 case V2SFmode:
9064 type = v2sf_ftype_v2sf_v2sf;
9065 break;
9066 case SImode:
9067 type = int_ftype_int_int;
9068 break;
9069 default:
9070 gcc_unreachable ();
9071 }
9072 }
9073
9074 /* A few other combos we really don't want to do manually. */
9075
9076 /* vint, vfloat, vfloat. */
9077 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9078 type = v4si_ftype_v4sf_v4sf;
9079
9080 /* vshort, vchar, vchar. */
9081 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9082 type = v8hi_ftype_v16qi_v16qi;
9083
9084 /* vint, vshort, vshort. */
9085 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9086 type = v4si_ftype_v8hi_v8hi;
9087
9088 /* vshort, vint, vint. */
9089 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9090 type = v8hi_ftype_v4si_v4si;
9091
9092 /* vchar, vshort, vshort. */
9093 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9094 type = v16qi_ftype_v8hi_v8hi;
9095
9096 /* vint, vchar, vint. */
9097 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9098 type = v4si_ftype_v16qi_v4si;
9099
9100 /* vint, vchar, vchar. */
9101 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9102 type = v4si_ftype_v16qi_v16qi;
9103
9104 /* vint, vshort, vint. */
9105 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9106 type = v4si_ftype_v8hi_v4si;
9107
9108 /* vint, vint, 5 bit literal. */
9109 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9110 type = v4si_ftype_v4si_int;
9111
9112 /* vshort, vshort, 5 bit literal. */
9113 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9114 type = v8hi_ftype_v8hi_int;
9115
9116 /* vchar, vchar, 5 bit literal. */
9117 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9118 type = v16qi_ftype_v16qi_int;
9119
9120 /* vfloat, vint, 5 bit literal. */
9121 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9122 type = v4sf_ftype_v4si_int;
9123
9124 /* vint, vfloat, 5 bit literal. */
9125 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9126 type = v4si_ftype_v4sf_int;
9127
9128 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9129 type = v2si_ftype_int_int;
9130
9131 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9132 type = v2si_ftype_v2si_char;
9133
9134 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9135 type = v2si_ftype_int_char;
9136
9137 else
9138 {
9139 /* int, x, x. */
9140 gcc_assert (mode0 == SImode);
9141 switch (mode1)
9142 {
9143 case V4SImode:
9144 type = int_ftype_v4si_v4si;
9145 break;
9146 case V4SFmode:
9147 type = int_ftype_v4sf_v4sf;
9148 break;
9149 case V16QImode:
9150 type = int_ftype_v16qi_v16qi;
9151 break;
9152 case V8HImode:
9153 type = int_ftype_v8hi_v8hi;
9154 break;
9155 default:
9156 gcc_unreachable ();
9157 }
9158 }
9159
9160 def_builtin (d->mask, d->name, type, d->code);
9161 }
9162
9163 /* Add the simple unary operators. */
9164 d = (struct builtin_description *) bdesc_1arg;
9165 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9166 {
9167 enum machine_mode mode0, mode1;
9168 tree type;
9169 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9170 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9171
9172 if (is_overloaded)
9173 {
9174 mode0 = VOIDmode;
9175 mode1 = VOIDmode;
9176 }
9177 else
9178 {
9179 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9180 continue;
9181
9182 mode0 = insn_data[d->icode].operand[0].mode;
9183 mode1 = insn_data[d->icode].operand[1].mode;
9184 }
9185
9186 if (mode0 == V4SImode && mode1 == QImode)
9187 type = v4si_ftype_int;
9188 else if (mode0 == V8HImode && mode1 == QImode)
9189 type = v8hi_ftype_int;
9190 else if (mode0 == V16QImode && mode1 == QImode)
9191 type = v16qi_ftype_int;
9192 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9193 type = opaque_ftype_opaque;
9194 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9195 type = v4sf_ftype_v4sf;
9196 else if (mode0 == V8HImode && mode1 == V16QImode)
9197 type = v8hi_ftype_v16qi;
9198 else if (mode0 == V4SImode && mode1 == V8HImode)
9199 type = v4si_ftype_v8hi;
9200 else if (mode0 == V2SImode && mode1 == V2SImode)
9201 type = v2si_ftype_v2si;
9202 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9203 type = v2sf_ftype_v2sf;
9204 else if (mode0 == V2SFmode && mode1 == V2SImode)
9205 type = v2sf_ftype_v2si;
9206 else if (mode0 == V2SImode && mode1 == V2SFmode)
9207 type = v2si_ftype_v2sf;
9208 else if (mode0 == V2SImode && mode1 == QImode)
9209 type = v2si_ftype_char;
9210 else
9211 gcc_unreachable ();
9212
9213 def_builtin (d->mask, d->name, type, d->code);
9214 }
9215 }
9216
9217 static void
rs6000_init_libfuncs(void)9218 rs6000_init_libfuncs (void)
9219 {
9220 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9221 && !TARGET_POWER2 && !TARGET_POWERPC)
9222 {
9223 /* AIX library routines for float->int conversion. */
9224 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9225 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9226 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9227 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9228 }
9229
9230 if (!TARGET_IEEEQUAD)
9231 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9232 if (!TARGET_XL_COMPAT)
9233 {
9234 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9235 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9236 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9237 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9238
9239 if (TARGET_SOFT_FLOAT)
9240 {
9241 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9242 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9243 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9244 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9245 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9246 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9247 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9248 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9249
9250 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9251 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9252 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9253 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9254 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9255 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9256 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9257 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9258 }
9259 }
9260 else
9261 {
9262 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9263 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9264 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9265 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9266 }
9267 else
9268 {
9269 /* 32-bit SVR4 quad floating point routines. */
9270
9271 set_optab_libfunc (add_optab, TFmode, "_q_add");
9272 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9273 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9274 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9275 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9276 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9277 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9278
9279 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9280 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9281 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9282 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9283 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9284 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9285
9286 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9287 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9288 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9289 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9290 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9291 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9292 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9293 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9294 }
9295 }
9296
9297
9298 /* Expand a block clear operation, and return 1 if successful. Return 0
9299 if we should let the compiler generate normal code.
9300
9301 operands[0] is the destination
9302 operands[1] is the length
9303 operands[3] is the alignment */
9304
9305 int
expand_block_clear(rtx operands[])9306 expand_block_clear (rtx operands[])
9307 {
9308 rtx orig_dest = operands[0];
9309 rtx bytes_rtx = operands[1];
9310 rtx align_rtx = operands[3];
9311 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9312 HOST_WIDE_INT align;
9313 HOST_WIDE_INT bytes;
9314 int offset;
9315 int clear_bytes;
9316 int clear_step;
9317
9318 /* If this is not a fixed size move, just call memcpy */
9319 if (! constp)
9320 return 0;
9321
9322 /* This must be a fixed size alignment */
9323 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9324 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9325
9326 /* Anything to clear? */
9327 bytes = INTVAL (bytes_rtx);
9328 if (bytes <= 0)
9329 return 1;
9330
9331 /* Use the builtin memset after a point, to avoid huge code bloat.
9332 When optimize_size, avoid any significant code bloat; calling
9333 memset is about 4 instructions, so allow for one instruction to
9334 load zero and three to do clearing. */
9335 if (TARGET_ALTIVEC && align >= 128)
9336 clear_step = 16;
9337 else if (TARGET_POWERPC64 && align >= 32)
9338 clear_step = 8;
9339 else
9340 clear_step = 4;
9341
9342 if (optimize_size && bytes > 3 * clear_step)
9343 return 0;
9344 if (! optimize_size && bytes > 8 * clear_step)
9345 return 0;
9346
9347 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9348 {
9349 enum machine_mode mode = BLKmode;
9350 rtx dest;
9351
9352 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9353 {
9354 clear_bytes = 16;
9355 mode = V4SImode;
9356 }
9357 else if (bytes >= 8 && TARGET_POWERPC64
9358 /* 64-bit loads and stores require word-aligned
9359 displacements. */
9360 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9361 {
9362 clear_bytes = 8;
9363 mode = DImode;
9364 }
9365 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9366 { /* move 4 bytes */
9367 clear_bytes = 4;
9368 mode = SImode;
9369 }
9370 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9371 { /* move 2 bytes */
9372 clear_bytes = 2;
9373 mode = HImode;
9374 }
9375 else /* move 1 byte at a time */
9376 {
9377 clear_bytes = 1;
9378 mode = QImode;
9379 }
9380
9381 dest = adjust_address (orig_dest, mode, offset);
9382
9383 emit_move_insn (dest, CONST0_RTX (mode));
9384 }
9385
9386 return 1;
9387 }
9388
9389
9390 /* Expand a block move operation, and return 1 if successful. Return 0
9391 if we should let the compiler generate normal code.
9392
9393 operands[0] is the destination
9394 operands[1] is the source
9395 operands[2] is the length
9396 operands[3] is the alignment */
9397
9398 #define MAX_MOVE_REG 4
9399
9400 int
expand_block_move(rtx operands[])9401 expand_block_move (rtx operands[])
9402 {
9403 rtx orig_dest = operands[0];
9404 rtx orig_src = operands[1];
9405 rtx bytes_rtx = operands[2];
9406 rtx align_rtx = operands[3];
9407 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9408 int align;
9409 int bytes;
9410 int offset;
9411 int move_bytes;
9412 rtx stores[MAX_MOVE_REG];
9413 int num_reg = 0;
9414
9415 /* If this is not a fixed size move, just call memcpy */
9416 if (! constp)
9417 return 0;
9418
9419 /* This must be a fixed size alignment */
9420 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9421 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9422
9423 /* Anything to move? */
9424 bytes = INTVAL (bytes_rtx);
9425 if (bytes <= 0)
9426 return 1;
9427
9428 /* store_one_arg depends on expand_block_move to handle at least the size of
9429 reg_parm_stack_space. */
9430 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9431 return 0;
9432
9433 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9434 {
9435 union {
9436 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9437 rtx (*mov) (rtx, rtx);
9438 } gen_func;
9439 enum machine_mode mode = BLKmode;
9440 rtx src, dest;
9441
9442 /* Altivec first, since it will be faster than a string move
9443 when it applies, and usually not significantly larger. */
9444 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9445 {
9446 move_bytes = 16;
9447 mode = V4SImode;
9448 gen_func.mov = gen_movv4si;
9449 }
9450 else if (TARGET_STRING
9451 && bytes > 24 /* move up to 32 bytes at a time */
9452 && ! fixed_regs[5]
9453 && ! fixed_regs[6]
9454 && ! fixed_regs[7]
9455 && ! fixed_regs[8]
9456 && ! fixed_regs[9]
9457 && ! fixed_regs[10]
9458 && ! fixed_regs[11]
9459 && ! fixed_regs[12])
9460 {
9461 move_bytes = (bytes > 32) ? 32 : bytes;
9462 gen_func.movmemsi = gen_movmemsi_8reg;
9463 }
9464 else if (TARGET_STRING
9465 && bytes > 16 /* move up to 24 bytes at a time */
9466 && ! fixed_regs[5]
9467 && ! fixed_regs[6]
9468 && ! fixed_regs[7]
9469 && ! fixed_regs[8]
9470 && ! fixed_regs[9]
9471 && ! fixed_regs[10])
9472 {
9473 move_bytes = (bytes > 24) ? 24 : bytes;
9474 gen_func.movmemsi = gen_movmemsi_6reg;
9475 }
9476 else if (TARGET_STRING
9477 && bytes > 8 /* move up to 16 bytes at a time */
9478 && ! fixed_regs[5]
9479 && ! fixed_regs[6]
9480 && ! fixed_regs[7]
9481 && ! fixed_regs[8])
9482 {
9483 move_bytes = (bytes > 16) ? 16 : bytes;
9484 gen_func.movmemsi = gen_movmemsi_4reg;
9485 }
9486 else if (bytes >= 8 && TARGET_POWERPC64
9487 /* 64-bit loads and stores require word-aligned
9488 displacements. */
9489 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9490 {
9491 move_bytes = 8;
9492 mode = DImode;
9493 gen_func.mov = gen_movdi;
9494 }
9495 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9496 { /* move up to 8 bytes at a time */
9497 move_bytes = (bytes > 8) ? 8 : bytes;
9498 gen_func.movmemsi = gen_movmemsi_2reg;
9499 }
9500 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9501 { /* move 4 bytes */
9502 move_bytes = 4;
9503 mode = SImode;
9504 gen_func.mov = gen_movsi;
9505 }
9506 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9507 { /* move 2 bytes */
9508 move_bytes = 2;
9509 mode = HImode;
9510 gen_func.mov = gen_movhi;
9511 }
9512 else if (TARGET_STRING && bytes > 1)
9513 { /* move up to 4 bytes at a time */
9514 move_bytes = (bytes > 4) ? 4 : bytes;
9515 gen_func.movmemsi = gen_movmemsi_1reg;
9516 }
9517 else /* move 1 byte at a time */
9518 {
9519 move_bytes = 1;
9520 mode = QImode;
9521 gen_func.mov = gen_movqi;
9522 }
9523
9524 src = adjust_address (orig_src, mode, offset);
9525 dest = adjust_address (orig_dest, mode, offset);
9526
9527 if (mode != BLKmode)
9528 {
9529 rtx tmp_reg = gen_reg_rtx (mode);
9530
9531 emit_insn ((*gen_func.mov) (tmp_reg, src));
9532 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9533 }
9534
9535 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9536 {
9537 int i;
9538 for (i = 0; i < num_reg; i++)
9539 emit_insn (stores[i]);
9540 num_reg = 0;
9541 }
9542
9543 if (mode == BLKmode)
9544 {
9545 /* Move the address into scratch registers. The movmemsi
9546 patterns require zero offset. */
9547 if (!REG_P (XEXP (src, 0)))
9548 {
9549 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9550 src = replace_equiv_address (src, src_reg);
9551 }
9552 set_mem_size (src, GEN_INT (move_bytes));
9553
9554 if (!REG_P (XEXP (dest, 0)))
9555 {
9556 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9557 dest = replace_equiv_address (dest, dest_reg);
9558 }
9559 set_mem_size (dest, GEN_INT (move_bytes));
9560
9561 emit_insn ((*gen_func.movmemsi) (dest, src,
9562 GEN_INT (move_bytes & 31),
9563 align_rtx));
9564 }
9565 }
9566
9567 return 1;
9568 }
9569
9570
9571 /* Return a string to perform a load_multiple operation.
9572 operands[0] is the vector.
9573 operands[1] is the source address.
9574 operands[2] is the first destination register. */
9575
9576 const char *
rs6000_output_load_multiple(rtx operands[3])9577 rs6000_output_load_multiple (rtx operands[3])
9578 {
9579 /* We have to handle the case where the pseudo used to contain the address
9580 is assigned to one of the output registers. */
9581 int i, j;
9582 int words = XVECLEN (operands[0], 0);
9583 rtx xop[10];
9584
9585 if (XVECLEN (operands[0], 0) == 1)
9586 return "{l|lwz} %2,0(%1)";
9587
9588 for (i = 0; i < words; i++)
9589 if (refers_to_regno_p (REGNO (operands[2]) + i,
9590 REGNO (operands[2]) + i + 1, operands[1], 0))
9591 {
9592 if (i == words-1)
9593 {
9594 xop[0] = GEN_INT (4 * (words-1));
9595 xop[1] = operands[1];
9596 xop[2] = operands[2];
9597 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9598 return "";
9599 }
9600 else if (i == 0)
9601 {
9602 xop[0] = GEN_INT (4 * (words-1));
9603 xop[1] = operands[1];
9604 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9605 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9606 return "";
9607 }
9608 else
9609 {
9610 for (j = 0; j < words; j++)
9611 if (j != i)
9612 {
9613 xop[0] = GEN_INT (j * 4);
9614 xop[1] = operands[1];
9615 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9616 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9617 }
9618 xop[0] = GEN_INT (i * 4);
9619 xop[1] = operands[1];
9620 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9621 return "";
9622 }
9623 }
9624
9625 return "{lsi|lswi} %2,%1,%N0";
9626 }
9627
9628
9629 /* A validation routine: say whether CODE, a condition code, and MODE
9630 match. The other alternatives either don't make sense or should
9631 never be generated. */
9632
9633 void
validate_condition_mode(enum rtx_code code,enum machine_mode mode)9634 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9635 {
9636 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9637 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9638 && GET_MODE_CLASS (mode) == MODE_CC);
9639
9640 /* These don't make sense. */
9641 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9642 || mode != CCUNSmode);
9643
9644 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9645 || mode == CCUNSmode);
9646
9647 gcc_assert (mode == CCFPmode
9648 || (code != ORDERED && code != UNORDERED
9649 && code != UNEQ && code != LTGT
9650 && code != UNGT && code != UNLT
9651 && code != UNGE && code != UNLE));
9652
9653 /* These should never be generated except for
9654 flag_finite_math_only. */
9655 gcc_assert (mode != CCFPmode
9656 || flag_finite_math_only
9657 || (code != LE && code != GE
9658 && code != UNEQ && code != LTGT
9659 && code != UNGT && code != UNLT));
9660
9661 /* These are invalid; the information is not there. */
9662 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9663 }
9664
9665
9666 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9667 mask required to convert the result of a rotate insn into a shift
9668 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9669
9670 int
includes_lshift_p(rtx shiftop,rtx andop)9671 includes_lshift_p (rtx shiftop, rtx andop)
9672 {
9673 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9674
9675 shift_mask <<= INTVAL (shiftop);
9676
9677 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9678 }
9679
9680 /* Similar, but for right shift. */
9681
9682 int
includes_rshift_p(rtx shiftop,rtx andop)9683 includes_rshift_p (rtx shiftop, rtx andop)
9684 {
9685 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9686
9687 shift_mask >>= INTVAL (shiftop);
9688
9689 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9690 }
9691
9692 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9693 to perform a left shift. It must have exactly SHIFTOP least
9694 significant 0's, then one or more 1's, then zero or more 0's. */
9695
9696 int
includes_rldic_lshift_p(rtx shiftop,rtx andop)9697 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9698 {
9699 if (GET_CODE (andop) == CONST_INT)
9700 {
9701 HOST_WIDE_INT c, lsb, shift_mask;
9702
9703 c = INTVAL (andop);
9704 if (c == 0 || c == ~0)
9705 return 0;
9706
9707 shift_mask = ~0;
9708 shift_mask <<= INTVAL (shiftop);
9709
9710 /* Find the least significant one bit. */
9711 lsb = c & -c;
9712
9713 /* It must coincide with the LSB of the shift mask. */
9714 if (-lsb != shift_mask)
9715 return 0;
9716
9717 /* Invert to look for the next transition (if any). */
9718 c = ~c;
9719
9720 /* Remove the low group of ones (originally low group of zeros). */
9721 c &= -lsb;
9722
9723 /* Again find the lsb, and check we have all 1's above. */
9724 lsb = c & -c;
9725 return c == -lsb;
9726 }
9727 else if (GET_CODE (andop) == CONST_DOUBLE
9728 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9729 {
9730 HOST_WIDE_INT low, high, lsb;
9731 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9732
9733 low = CONST_DOUBLE_LOW (andop);
9734 if (HOST_BITS_PER_WIDE_INT < 64)
9735 high = CONST_DOUBLE_HIGH (andop);
9736
9737 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9738 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9739 return 0;
9740
9741 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9742 {
9743 shift_mask_high = ~0;
9744 if (INTVAL (shiftop) > 32)
9745 shift_mask_high <<= INTVAL (shiftop) - 32;
9746
9747 lsb = high & -high;
9748
9749 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9750 return 0;
9751
9752 high = ~high;
9753 high &= -lsb;
9754
9755 lsb = high & -high;
9756 return high == -lsb;
9757 }
9758
9759 shift_mask_low = ~0;
9760 shift_mask_low <<= INTVAL (shiftop);
9761
9762 lsb = low & -low;
9763
9764 if (-lsb != shift_mask_low)
9765 return 0;
9766
9767 if (HOST_BITS_PER_WIDE_INT < 64)
9768 high = ~high;
9769 low = ~low;
9770 low &= -lsb;
9771
9772 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9773 {
9774 lsb = high & -high;
9775 return high == -lsb;
9776 }
9777
9778 lsb = low & -low;
9779 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9780 }
9781 else
9782 return 0;
9783 }
9784
9785 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9786 to perform a left shift. It must have SHIFTOP or more least
9787 significant 0's, with the remainder of the word 1's. */
9788
9789 int
includes_rldicr_lshift_p(rtx shiftop,rtx andop)9790 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9791 {
9792 if (GET_CODE (andop) == CONST_INT)
9793 {
9794 HOST_WIDE_INT c, lsb, shift_mask;
9795
9796 shift_mask = ~0;
9797 shift_mask <<= INTVAL (shiftop);
9798 c = INTVAL (andop);
9799
9800 /* Find the least significant one bit. */
9801 lsb = c & -c;
9802
9803 /* It must be covered by the shift mask.
9804 This test also rejects c == 0. */
9805 if ((lsb & shift_mask) == 0)
9806 return 0;
9807
9808 /* Check we have all 1's above the transition, and reject all 1's. */
9809 return c == -lsb && lsb != 1;
9810 }
9811 else if (GET_CODE (andop) == CONST_DOUBLE
9812 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9813 {
9814 HOST_WIDE_INT low, lsb, shift_mask_low;
9815
9816 low = CONST_DOUBLE_LOW (andop);
9817
9818 if (HOST_BITS_PER_WIDE_INT < 64)
9819 {
9820 HOST_WIDE_INT high, shift_mask_high;
9821
9822 high = CONST_DOUBLE_HIGH (andop);
9823
9824 if (low == 0)
9825 {
9826 shift_mask_high = ~0;
9827 if (INTVAL (shiftop) > 32)
9828 shift_mask_high <<= INTVAL (shiftop) - 32;
9829
9830 lsb = high & -high;
9831
9832 if ((lsb & shift_mask_high) == 0)
9833 return 0;
9834
9835 return high == -lsb;
9836 }
9837 if (high != ~0)
9838 return 0;
9839 }
9840
9841 shift_mask_low = ~0;
9842 shift_mask_low <<= INTVAL (shiftop);
9843
9844 lsb = low & -low;
9845
9846 if ((lsb & shift_mask_low) == 0)
9847 return 0;
9848
9849 return low == -lsb && lsb != 1;
9850 }
9851 else
9852 return 0;
9853 }
9854
9855 /* Return 1 if operands will generate a valid arguments to rlwimi
9856 instruction for insert with right shift in 64-bit mode. The mask may
9857 not start on the first bit or stop on the last bit because wrap-around
9858 effects of instruction do not correspond to semantics of RTL insn. */
9859
9860 int
insvdi_rshift_rlwimi_p(rtx sizeop,rtx startop,rtx shiftop)9861 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9862 {
9863 if (INTVAL (startop) > 32
9864 && INTVAL (startop) < 64
9865 && INTVAL (sizeop) > 1
9866 && INTVAL (sizeop) + INTVAL (startop) < 64
9867 && INTVAL (shiftop) > 0
9868 && INTVAL (sizeop) + INTVAL (shiftop) < 32
9869 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9870 return 1;
9871
9872 return 0;
9873 }
9874
9875 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9876 for lfq and stfq insns iff the registers are hard registers. */
9877
9878 int
registers_ok_for_quad_peep(rtx reg1,rtx reg2)9879 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9880 {
9881 /* We might have been passed a SUBREG. */
9882 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9883 return 0;
9884
9885 /* We might have been passed non floating point registers. */
9886 if (!FP_REGNO_P (REGNO (reg1))
9887 || !FP_REGNO_P (REGNO (reg2)))
9888 return 0;
9889
9890 return (REGNO (reg1) == REGNO (reg2) - 1);
9891 }
9892
9893 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9894 addr1 and addr2 must be in consecutive memory locations
9895 (addr2 == addr1 + 8). */
9896
9897 int
mems_ok_for_quad_peep(rtx mem1,rtx mem2)9898 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9899 {
9900 rtx addr1, addr2;
9901 unsigned int reg1, reg2;
9902 int offset1, offset2;
9903
9904 /* The mems cannot be volatile. */
9905 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9906 return 0;
9907
9908 addr1 = XEXP (mem1, 0);
9909 addr2 = XEXP (mem2, 0);
9910
9911 /* Extract an offset (if used) from the first addr. */
9912 if (GET_CODE (addr1) == PLUS)
9913 {
9914 /* If not a REG, return zero. */
9915 if (GET_CODE (XEXP (addr1, 0)) != REG)
9916 return 0;
9917 else
9918 {
9919 reg1 = REGNO (XEXP (addr1, 0));
9920 /* The offset must be constant! */
9921 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9922 return 0;
9923 offset1 = INTVAL (XEXP (addr1, 1));
9924 }
9925 }
9926 else if (GET_CODE (addr1) != REG)
9927 return 0;
9928 else
9929 {
9930 reg1 = REGNO (addr1);
9931 /* This was a simple (mem (reg)) expression. Offset is 0. */
9932 offset1 = 0;
9933 }
9934
9935 /* And now for the second addr. */
9936 if (GET_CODE (addr2) == PLUS)
9937 {
9938 /* If not a REG, return zero. */
9939 if (GET_CODE (XEXP (addr2, 0)) != REG)
9940 return 0;
9941 else
9942 {
9943 reg2 = REGNO (XEXP (addr2, 0));
9944 /* The offset must be constant. */
9945 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9946 return 0;
9947 offset2 = INTVAL (XEXP (addr2, 1));
9948 }
9949 }
9950 else if (GET_CODE (addr2) != REG)
9951 return 0;
9952 else
9953 {
9954 reg2 = REGNO (addr2);
9955 /* This was a simple (mem (reg)) expression. Offset is 0. */
9956 offset2 = 0;
9957 }
9958
9959 /* Both of these must have the same base register. */
9960 if (reg1 != reg2)
9961 return 0;
9962
9963 /* The offset for the second addr must be 8 more than the first addr. */
9964 if (offset2 != offset1 + 8)
9965 return 0;
9966
9967 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9968 instructions. */
9969 return 1;
9970 }
9971
9972 /* Return the register class of a scratch register needed to copy IN into
9973 or out of a register in CLASS in MODE. If it can be done directly,
9974 NO_REGS is returned. */
9975
9976 enum reg_class
rs6000_secondary_reload_class(enum reg_class class,enum machine_mode mode ATTRIBUTE_UNUSED,rtx in)9977 rs6000_secondary_reload_class (enum reg_class class,
9978 enum machine_mode mode ATTRIBUTE_UNUSED,
9979 rtx in)
9980 {
9981 int regno;
9982
9983 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9984 #if TARGET_MACHO
9985 && MACHOPIC_INDIRECT
9986 #endif
9987 ))
9988 {
9989 /* We cannot copy a symbolic operand directly into anything
9990 other than BASE_REGS for TARGET_ELF. So indicate that a
9991 register from BASE_REGS is needed as an intermediate
9992 register.
9993
9994 On Darwin, pic addresses require a load from memory, which
9995 needs a base register. */
9996 if (class != BASE_REGS
9997 && (GET_CODE (in) == SYMBOL_REF
9998 || GET_CODE (in) == HIGH
9999 || GET_CODE (in) == LABEL_REF
10000 || GET_CODE (in) == CONST))
10001 return BASE_REGS;
10002 }
10003
10004 if (GET_CODE (in) == REG)
10005 {
10006 regno = REGNO (in);
10007 if (regno >= FIRST_PSEUDO_REGISTER)
10008 {
10009 regno = true_regnum (in);
10010 if (regno >= FIRST_PSEUDO_REGISTER)
10011 regno = -1;
10012 }
10013 }
10014 else if (GET_CODE (in) == SUBREG)
10015 {
10016 regno = true_regnum (in);
10017 if (regno >= FIRST_PSEUDO_REGISTER)
10018 regno = -1;
10019 }
10020 else
10021 regno = -1;
10022
10023 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10024 into anything. */
10025 if (class == GENERAL_REGS || class == BASE_REGS
10026 || (regno >= 0 && INT_REGNO_P (regno)))
10027 return NO_REGS;
10028
10029 /* Constants, memory, and FP registers can go into FP registers. */
10030 if ((regno == -1 || FP_REGNO_P (regno))
10031 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10032 return NO_REGS;
10033
10034 /* Memory, and AltiVec registers can go into AltiVec registers. */
10035 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10036 && class == ALTIVEC_REGS)
10037 return NO_REGS;
10038
10039 /* We can copy among the CR registers. */
10040 if ((class == CR_REGS || class == CR0_REGS)
10041 && regno >= 0 && CR_REGNO_P (regno))
10042 return NO_REGS;
10043
10044 /* Otherwise, we need GENERAL_REGS. */
10045 return GENERAL_REGS;
10046 }
10047
10048 /* Given a comparison operation, return the bit number in CCR to test. We
10049 know this is a valid comparison.
10050
10051 SCC_P is 1 if this is for an scc. That means that %D will have been
10052 used instead of %C, so the bits will be in different places.
10053
10054 Return -1 if OP isn't a valid comparison for some reason. */
10055
10056 int
ccr_bit(rtx op,int scc_p)10057 ccr_bit (rtx op, int scc_p)
10058 {
10059 enum rtx_code code = GET_CODE (op);
10060 enum machine_mode cc_mode;
10061 int cc_regnum;
10062 int base_bit;
10063 rtx reg;
10064
10065 if (!COMPARISON_P (op))
10066 return -1;
10067
10068 reg = XEXP (op, 0);
10069
10070 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10071
10072 cc_mode = GET_MODE (reg);
10073 cc_regnum = REGNO (reg);
10074 base_bit = 4 * (cc_regnum - CR0_REGNO);
10075
10076 validate_condition_mode (code, cc_mode);
10077
10078 /* When generating a sCOND operation, only positive conditions are
10079 allowed. */
10080 gcc_assert (!scc_p
10081 || code == EQ || code == GT || code == LT || code == UNORDERED
10082 || code == GTU || code == LTU);
10083
10084 switch (code)
10085 {
10086 case NE:
10087 return scc_p ? base_bit + 3 : base_bit + 2;
10088 case EQ:
10089 return base_bit + 2;
10090 case GT: case GTU: case UNLE:
10091 return base_bit + 1;
10092 case LT: case LTU: case UNGE:
10093 return base_bit;
10094 case ORDERED: case UNORDERED:
10095 return base_bit + 3;
10096
10097 case GE: case GEU:
10098 /* If scc, we will have done a cror to put the bit in the
10099 unordered position. So test that bit. For integer, this is ! LT
10100 unless this is an scc insn. */
10101 return scc_p ? base_bit + 3 : base_bit;
10102
10103 case LE: case LEU:
10104 return scc_p ? base_bit + 3 : base_bit + 1;
10105
10106 default:
10107 gcc_unreachable ();
10108 }
10109 }
10110
10111 /* Return the GOT register. */
10112
10113 rtx
rs6000_got_register(rtx value ATTRIBUTE_UNUSED)10114 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10115 {
10116 /* The second flow pass currently (June 1999) can't update
10117 regs_ever_live without disturbing other parts of the compiler, so
10118 update it here to make the prolog/epilogue code happy. */
10119 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10120 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10121
10122 current_function_uses_pic_offset_table = 1;
10123
10124 return pic_offset_table_rtx;
10125 }
10126
10127 /* Function to init struct machine_function.
10128 This will be called, via a pointer variable,
10129 from push_function_context. */
10130
10131 static struct machine_function *
rs6000_init_machine_status(void)10132 rs6000_init_machine_status (void)
10133 {
10134 return ggc_alloc_cleared (sizeof (machine_function));
10135 }
10136
10137 /* These macros test for integers and extract the low-order bits. */
10138 #define INT_P(X) \
10139 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10140 && GET_MODE (X) == VOIDmode)
10141
10142 #define INT_LOWPART(X) \
10143 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10144
10145 int
extract_MB(rtx op)10146 extract_MB (rtx op)
10147 {
10148 int i;
10149 unsigned long val = INT_LOWPART (op);
10150
10151 /* If the high bit is zero, the value is the first 1 bit we find
10152 from the left. */
10153 if ((val & 0x80000000) == 0)
10154 {
10155 gcc_assert (val & 0xffffffff);
10156
10157 i = 1;
10158 while (((val <<= 1) & 0x80000000) == 0)
10159 ++i;
10160 return i;
10161 }
10162
10163 /* If the high bit is set and the low bit is not, or the mask is all
10164 1's, the value is zero. */
10165 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10166 return 0;
10167
10168 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10169 from the right. */
10170 i = 31;
10171 while (((val >>= 1) & 1) != 0)
10172 --i;
10173
10174 return i;
10175 }
10176
10177 int
extract_ME(rtx op)10178 extract_ME (rtx op)
10179 {
10180 int i;
10181 unsigned long val = INT_LOWPART (op);
10182
10183 /* If the low bit is zero, the value is the first 1 bit we find from
10184 the right. */
10185 if ((val & 1) == 0)
10186 {
10187 gcc_assert (val & 0xffffffff);
10188
10189 i = 30;
10190 while (((val >>= 1) & 1) == 0)
10191 --i;
10192
10193 return i;
10194 }
10195
10196 /* If the low bit is set and the high bit is not, or the mask is all
10197 1's, the value is 31. */
10198 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10199 return 31;
10200
10201 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10202 from the left. */
10203 i = 0;
10204 while (((val <<= 1) & 0x80000000) != 0)
10205 ++i;
10206
10207 return i;
10208 }
10209
10210 /* Locate some local-dynamic symbol still in use by this function
10211 so that we can print its name in some tls_ld pattern. */
10212
10213 static const char *
rs6000_get_some_local_dynamic_name(void)10214 rs6000_get_some_local_dynamic_name (void)
10215 {
10216 rtx insn;
10217
10218 if (cfun->machine->some_ld_name)
10219 return cfun->machine->some_ld_name;
10220
10221 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10222 if (INSN_P (insn)
10223 && for_each_rtx (&PATTERN (insn),
10224 rs6000_get_some_local_dynamic_name_1, 0))
10225 return cfun->machine->some_ld_name;
10226
10227 gcc_unreachable ();
10228 }
10229
10230 /* Helper function for rs6000_get_some_local_dynamic_name. */
10231
10232 static int
rs6000_get_some_local_dynamic_name_1(rtx * px,void * data ATTRIBUTE_UNUSED)10233 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10234 {
10235 rtx x = *px;
10236
10237 if (GET_CODE (x) == SYMBOL_REF)
10238 {
10239 const char *str = XSTR (x, 0);
10240 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10241 {
10242 cfun->machine->some_ld_name = str;
10243 return 1;
10244 }
10245 }
10246
10247 return 0;
10248 }
10249
10250 /* Write out a function code label. */
10251
10252 void
rs6000_output_function_entry(FILE * file,const char * fname)10253 rs6000_output_function_entry (FILE *file, const char *fname)
10254 {
10255 if (fname[0] != '.')
10256 {
10257 switch (DEFAULT_ABI)
10258 {
10259 default:
10260 gcc_unreachable ();
10261
10262 case ABI_AIX:
10263 if (DOT_SYMBOLS)
10264 putc ('.', file);
10265 else
10266 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10267 break;
10268
10269 case ABI_V4:
10270 case ABI_DARWIN:
10271 break;
10272 }
10273 }
10274 if (TARGET_AIX)
10275 RS6000_OUTPUT_BASENAME (file, fname);
10276 else
10277 assemble_name (file, fname);
10278 }
10279
10280 /* Print an operand. Recognize special options, documented below. */
10281
10282 #if TARGET_ELF
10283 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10284 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10285 #else
10286 #define SMALL_DATA_RELOC "sda21"
10287 #define SMALL_DATA_REG 0
10288 #endif
10289
10290 void
print_operand(FILE * file,rtx x,int code)10291 print_operand (FILE *file, rtx x, int code)
10292 {
10293 int i;
10294 HOST_WIDE_INT val;
10295 unsigned HOST_WIDE_INT uval;
10296
10297 switch (code)
10298 {
10299 case '.':
10300 /* Write out an instruction after the call which may be replaced
10301 with glue code by the loader. This depends on the AIX version. */
10302 asm_fprintf (file, RS6000_CALL_GLUE);
10303 return;
10304
10305 /* %a is output_address. */
10306
10307 case 'A':
10308 /* If X is a constant integer whose low-order 5 bits are zero,
10309 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10310 in the AIX assembler where "sri" with a zero shift count
10311 writes a trash instruction. */
10312 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10313 putc ('l', file);
10314 else
10315 putc ('r', file);
10316 return;
10317
10318 case 'b':
10319 /* If constant, low-order 16 bits of constant, unsigned.
10320 Otherwise, write normally. */
10321 if (INT_P (x))
10322 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10323 else
10324 print_operand (file, x, 0);
10325 return;
10326
10327 case 'B':
10328 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10329 for 64-bit mask direction. */
10330 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10331 return;
10332
10333 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10334 output_operand. */
10335
10336 case 'c':
10337 /* X is a CR register. Print the number of the GT bit of the CR. */
10338 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10339 output_operand_lossage ("invalid %%E value");
10340 else
10341 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10342 return;
10343
10344 case 'D':
10345 /* Like 'J' but get to the GT bit only. */
10346 gcc_assert (GET_CODE (x) == REG);
10347
10348 /* Bit 1 is GT bit. */
10349 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10350
10351 /* Add one for shift count in rlinm for scc. */
10352 fprintf (file, "%d", i + 1);
10353 return;
10354
10355 case 'E':
10356 /* X is a CR register. Print the number of the EQ bit of the CR */
10357 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10358 output_operand_lossage ("invalid %%E value");
10359 else
10360 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10361 return;
10362
10363 case 'f':
10364 /* X is a CR register. Print the shift count needed to move it
10365 to the high-order four bits. */
10366 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10367 output_operand_lossage ("invalid %%f value");
10368 else
10369 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10370 return;
10371
10372 case 'F':
10373 /* Similar, but print the count for the rotate in the opposite
10374 direction. */
10375 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10376 output_operand_lossage ("invalid %%F value");
10377 else
10378 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10379 return;
10380
10381 case 'G':
10382 /* X is a constant integer. If it is negative, print "m",
10383 otherwise print "z". This is to make an aze or ame insn. */
10384 if (GET_CODE (x) != CONST_INT)
10385 output_operand_lossage ("invalid %%G value");
10386 else if (INTVAL (x) >= 0)
10387 putc ('z', file);
10388 else
10389 putc ('m', file);
10390 return;
10391
10392 case 'h':
10393 /* If constant, output low-order five bits. Otherwise, write
10394 normally. */
10395 if (INT_P (x))
10396 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10397 else
10398 print_operand (file, x, 0);
10399 return;
10400
10401 case 'H':
10402 /* If constant, output low-order six bits. Otherwise, write
10403 normally. */
10404 if (INT_P (x))
10405 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10406 else
10407 print_operand (file, x, 0);
10408 return;
10409
10410 case 'I':
10411 /* Print `i' if this is a constant, else nothing. */
10412 if (INT_P (x))
10413 putc ('i', file);
10414 return;
10415
10416 case 'j':
10417 /* Write the bit number in CCR for jump. */
10418 i = ccr_bit (x, 0);
10419 if (i == -1)
10420 output_operand_lossage ("invalid %%j code");
10421 else
10422 fprintf (file, "%d", i);
10423 return;
10424
10425 case 'J':
10426 /* Similar, but add one for shift count in rlinm for scc and pass
10427 scc flag to `ccr_bit'. */
10428 i = ccr_bit (x, 1);
10429 if (i == -1)
10430 output_operand_lossage ("invalid %%J code");
10431 else
10432 /* If we want bit 31, write a shift count of zero, not 32. */
10433 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10434 return;
10435
10436 case 'k':
10437 /* X must be a constant. Write the 1's complement of the
10438 constant. */
10439 if (! INT_P (x))
10440 output_operand_lossage ("invalid %%k value");
10441 else
10442 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10443 return;
10444
10445 case 'K':
10446 /* X must be a symbolic constant on ELF. Write an
10447 expression suitable for an 'addi' that adds in the low 16
10448 bits of the MEM. */
10449 if (GET_CODE (x) != CONST)
10450 {
10451 print_operand_address (file, x);
10452 fputs ("@l", file);
10453 }
10454 else
10455 {
10456 if (GET_CODE (XEXP (x, 0)) != PLUS
10457 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10458 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10459 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10460 output_operand_lossage ("invalid %%K value");
10461 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10462 fputs ("@l", file);
10463 /* For GNU as, there must be a non-alphanumeric character
10464 between 'l' and the number. The '-' is added by
10465 print_operand() already. */
10466 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10467 fputs ("+", file);
10468 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10469 }
10470 return;
10471
10472 /* %l is output_asm_label. */
10473
10474 case 'L':
10475 /* Write second word of DImode or DFmode reference. Works on register
10476 or non-indexed memory only. */
10477 if (GET_CODE (x) == REG)
10478 fputs (reg_names[REGNO (x) + 1], file);
10479 else if (GET_CODE (x) == MEM)
10480 {
10481 /* Handle possible auto-increment. Since it is pre-increment and
10482 we have already done it, we can just use an offset of word. */
10483 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10484 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10485 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10486 UNITS_PER_WORD));
10487 else
10488 output_address (XEXP (adjust_address_nv (x, SImode,
10489 UNITS_PER_WORD),
10490 0));
10491
10492 if (small_data_operand (x, GET_MODE (x)))
10493 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10494 reg_names[SMALL_DATA_REG]);
10495 }
10496 return;
10497
10498 case 'm':
10499 /* MB value for a mask operand. */
10500 if (! mask_operand (x, SImode))
10501 output_operand_lossage ("invalid %%m value");
10502
10503 fprintf (file, "%d", extract_MB (x));
10504 return;
10505
10506 case 'M':
10507 /* ME value for a mask operand. */
10508 if (! mask_operand (x, SImode))
10509 output_operand_lossage ("invalid %%M value");
10510
10511 fprintf (file, "%d", extract_ME (x));
10512 return;
10513
10514 /* %n outputs the negative of its operand. */
10515
10516 case 'N':
10517 /* Write the number of elements in the vector times 4. */
10518 if (GET_CODE (x) != PARALLEL)
10519 output_operand_lossage ("invalid %%N value");
10520 else
10521 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10522 return;
10523
10524 case 'O':
10525 /* Similar, but subtract 1 first. */
10526 if (GET_CODE (x) != PARALLEL)
10527 output_operand_lossage ("invalid %%O value");
10528 else
10529 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10530 return;
10531
10532 case 'p':
10533 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10534 if (! INT_P (x)
10535 || INT_LOWPART (x) < 0
10536 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10537 output_operand_lossage ("invalid %%p value");
10538 else
10539 fprintf (file, "%d", i);
10540 return;
10541
10542 case 'P':
10543 /* The operand must be an indirect memory reference. The result
10544 is the register name. */
10545 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10546 || REGNO (XEXP (x, 0)) >= 32)
10547 output_operand_lossage ("invalid %%P value");
10548 else
10549 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10550 return;
10551
10552 case 'q':
10553 /* This outputs the logical code corresponding to a boolean
10554 expression. The expression may have one or both operands
10555 negated (if one, only the first one). For condition register
10556 logical operations, it will also treat the negated
10557 CR codes as NOTs, but not handle NOTs of them. */
10558 {
10559 const char *const *t = 0;
10560 const char *s;
10561 enum rtx_code code = GET_CODE (x);
10562 static const char * const tbl[3][3] = {
10563 { "and", "andc", "nor" },
10564 { "or", "orc", "nand" },
10565 { "xor", "eqv", "xor" } };
10566
10567 if (code == AND)
10568 t = tbl[0];
10569 else if (code == IOR)
10570 t = tbl[1];
10571 else if (code == XOR)
10572 t = tbl[2];
10573 else
10574 output_operand_lossage ("invalid %%q value");
10575
10576 if (GET_CODE (XEXP (x, 0)) != NOT)
10577 s = t[0];
10578 else
10579 {
10580 if (GET_CODE (XEXP (x, 1)) == NOT)
10581 s = t[2];
10582 else
10583 s = t[1];
10584 }
10585
10586 fputs (s, file);
10587 }
10588 return;
10589
10590 case 'Q':
10591 if (TARGET_MFCRF)
10592 fputc (',', file);
10593 /* FALLTHRU */
10594 else
10595 return;
10596
10597 case 'R':
10598 /* X is a CR register. Print the mask for `mtcrf'. */
10599 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10600 output_operand_lossage ("invalid %%R value");
10601 else
10602 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10603 return;
10604
10605 case 's':
10606 /* Low 5 bits of 32 - value */
10607 if (! INT_P (x))
10608 output_operand_lossage ("invalid %%s value");
10609 else
10610 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10611 return;
10612
10613 case 'S':
10614 /* PowerPC64 mask position. All 0's is excluded.
10615 CONST_INT 32-bit mask is considered sign-extended so any
10616 transition must occur within the CONST_INT, not on the boundary. */
10617 if (! mask64_operand (x, DImode))
10618 output_operand_lossage ("invalid %%S value");
10619
10620 uval = INT_LOWPART (x);
10621
10622 if (uval & 1) /* Clear Left */
10623 {
10624 #if HOST_BITS_PER_WIDE_INT > 64
10625 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10626 #endif
10627 i = 64;
10628 }
10629 else /* Clear Right */
10630 {
10631 uval = ~uval;
10632 #if HOST_BITS_PER_WIDE_INT > 64
10633 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10634 #endif
10635 i = 63;
10636 }
10637 while (uval != 0)
10638 --i, uval >>= 1;
10639 gcc_assert (i >= 0);
10640 fprintf (file, "%d", i);
10641 return;
10642
10643 case 't':
10644 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10645 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10646
10647 /* Bit 3 is OV bit. */
10648 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10649
10650 /* If we want bit 31, write a shift count of zero, not 32. */
10651 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10652 return;
10653
10654 case 'T':
10655 /* Print the symbolic name of a branch target register. */
10656 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10657 && REGNO (x) != COUNT_REGISTER_REGNUM))
10658 output_operand_lossage ("invalid %%T value");
10659 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10660 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10661 else
10662 fputs ("ctr", file);
10663 return;
10664
10665 case 'u':
10666 /* High-order 16 bits of constant for use in unsigned operand. */
10667 if (! INT_P (x))
10668 output_operand_lossage ("invalid %%u value");
10669 else
10670 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10671 (INT_LOWPART (x) >> 16) & 0xffff);
10672 return;
10673
10674 case 'v':
10675 /* High-order 16 bits of constant for use in signed operand. */
10676 if (! INT_P (x))
10677 output_operand_lossage ("invalid %%v value");
10678 else
10679 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10680 (INT_LOWPART (x) >> 16) & 0xffff);
10681 return;
10682
10683 case 'U':
10684 /* Print `u' if this has an auto-increment or auto-decrement. */
10685 if (GET_CODE (x) == MEM
10686 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10687 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10688 putc ('u', file);
10689 return;
10690
10691 case 'V':
10692 /* Print the trap code for this operand. */
10693 switch (GET_CODE (x))
10694 {
10695 case EQ:
10696 fputs ("eq", file); /* 4 */
10697 break;
10698 case NE:
10699 fputs ("ne", file); /* 24 */
10700 break;
10701 case LT:
10702 fputs ("lt", file); /* 16 */
10703 break;
10704 case LE:
10705 fputs ("le", file); /* 20 */
10706 break;
10707 case GT:
10708 fputs ("gt", file); /* 8 */
10709 break;
10710 case GE:
10711 fputs ("ge", file); /* 12 */
10712 break;
10713 case LTU:
10714 fputs ("llt", file); /* 2 */
10715 break;
10716 case LEU:
10717 fputs ("lle", file); /* 6 */
10718 break;
10719 case GTU:
10720 fputs ("lgt", file); /* 1 */
10721 break;
10722 case GEU:
10723 fputs ("lge", file); /* 5 */
10724 break;
10725 default:
10726 gcc_unreachable ();
10727 }
10728 break;
10729
10730 case 'w':
10731 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10732 normally. */
10733 if (INT_P (x))
10734 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10735 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10736 else
10737 print_operand (file, x, 0);
10738 return;
10739
10740 case 'W':
10741 /* MB value for a PowerPC64 rldic operand. */
10742 val = (GET_CODE (x) == CONST_INT
10743 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10744
10745 if (val < 0)
10746 i = -1;
10747 else
10748 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10749 if ((val <<= 1) < 0)
10750 break;
10751
10752 #if HOST_BITS_PER_WIDE_INT == 32
10753 if (GET_CODE (x) == CONST_INT && i >= 0)
10754 i += 32; /* zero-extend high-part was all 0's */
10755 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10756 {
10757 val = CONST_DOUBLE_LOW (x);
10758
10759 gcc_assert (val);
10760 if (val < 0)
10761 --i;
10762 else
10763 for ( ; i < 64; i++)
10764 if ((val <<= 1) < 0)
10765 break;
10766 }
10767 #endif
10768
10769 fprintf (file, "%d", i + 1);
10770 return;
10771
10772 case 'X':
10773 if (GET_CODE (x) == MEM
10774 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10775 putc ('x', file);
10776 return;
10777
10778 case 'Y':
10779 /* Like 'L', for third word of TImode */
10780 if (GET_CODE (x) == REG)
10781 fputs (reg_names[REGNO (x) + 2], file);
10782 else if (GET_CODE (x) == MEM)
10783 {
10784 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10785 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10786 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10787 else
10788 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10789 if (small_data_operand (x, GET_MODE (x)))
10790 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10791 reg_names[SMALL_DATA_REG]);
10792 }
10793 return;
10794
10795 case 'z':
10796 /* X is a SYMBOL_REF. Write out the name preceded by a
10797 period and without any trailing data in brackets. Used for function
10798 names. If we are configured for System V (or the embedded ABI) on
10799 the PowerPC, do not emit the period, since those systems do not use
10800 TOCs and the like. */
10801 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10802
10803 /* Mark the decl as referenced so that cgraph will output the
10804 function. */
10805 if (SYMBOL_REF_DECL (x))
10806 mark_decl_referenced (SYMBOL_REF_DECL (x));
10807
10808 /* For macho, check to see if we need a stub. */
10809 if (TARGET_MACHO)
10810 {
10811 const char *name = XSTR (x, 0);
10812 #if TARGET_MACHO
10813 if (MACHOPIC_INDIRECT
10814 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10815 name = machopic_indirection_name (x, /*stub_p=*/true);
10816 #endif
10817 assemble_name (file, name);
10818 }
10819 else if (!DOT_SYMBOLS)
10820 assemble_name (file, XSTR (x, 0));
10821 else
10822 rs6000_output_function_entry (file, XSTR (x, 0));
10823 return;
10824
10825 case 'Z':
10826 /* Like 'L', for last word of TImode. */
10827 if (GET_CODE (x) == REG)
10828 fputs (reg_names[REGNO (x) + 3], file);
10829 else if (GET_CODE (x) == MEM)
10830 {
10831 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10832 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10833 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10834 else
10835 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10836 if (small_data_operand (x, GET_MODE (x)))
10837 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10838 reg_names[SMALL_DATA_REG]);
10839 }
10840 return;
10841
10842 /* Print AltiVec or SPE memory operand. */
10843 case 'y':
10844 {
10845 rtx tmp;
10846
10847 gcc_assert (GET_CODE (x) == MEM);
10848
10849 tmp = XEXP (x, 0);
10850
10851 /* Ugly hack because %y is overloaded. */
10852 if (TARGET_E500 && GET_MODE_SIZE (GET_MODE (x)) == 8)
10853 {
10854 /* Handle [reg]. */
10855 if (GET_CODE (tmp) == REG)
10856 {
10857 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10858 break;
10859 }
10860 /* Handle [reg+UIMM]. */
10861 else if (GET_CODE (tmp) == PLUS &&
10862 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10863 {
10864 int x;
10865
10866 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10867
10868 x = INTVAL (XEXP (tmp, 1));
10869 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10870 break;
10871 }
10872
10873 /* Fall through. Must be [reg+reg]. */
10874 }
10875 if (TARGET_ALTIVEC
10876 && GET_CODE (tmp) == AND
10877 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10878 && INTVAL (XEXP (tmp, 1)) == -16)
10879 tmp = XEXP (tmp, 0);
10880 if (GET_CODE (tmp) == REG)
10881 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10882 else
10883 {
10884 gcc_assert (GET_CODE (tmp) == PLUS
10885 && REG_P (XEXP (tmp, 0))
10886 && REG_P (XEXP (tmp, 1)));
10887
10888 if (REGNO (XEXP (tmp, 0)) == 0)
10889 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10890 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10891 else
10892 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10893 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10894 }
10895 break;
10896 }
10897
10898 case 0:
10899 if (GET_CODE (x) == REG)
10900 fprintf (file, "%s", reg_names[REGNO (x)]);
10901 else if (GET_CODE (x) == MEM)
10902 {
10903 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10904 know the width from the mode. */
10905 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10906 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10907 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10908 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10909 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10910 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10911 else
10912 output_address (XEXP (x, 0));
10913 }
10914 else
10915 output_addr_const (file, x);
10916 return;
10917
10918 case '&':
10919 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10920 return;
10921
10922 default:
10923 output_operand_lossage ("invalid %%xn code");
10924 }
10925 }
10926
10927 /* Print the address of an operand. */
10928
10929 void
print_operand_address(FILE * file,rtx x)10930 print_operand_address (FILE *file, rtx x)
10931 {
10932 if (GET_CODE (x) == REG)
10933 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10934 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10935 || GET_CODE (x) == LABEL_REF)
10936 {
10937 output_addr_const (file, x);
10938 if (small_data_operand (x, GET_MODE (x)))
10939 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10940 reg_names[SMALL_DATA_REG]);
10941 else
10942 gcc_assert (!TARGET_TOC);
10943 }
10944 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10945 {
10946 gcc_assert (REG_P (XEXP (x, 0)));
10947 if (REGNO (XEXP (x, 0)) == 0)
10948 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10949 reg_names[ REGNO (XEXP (x, 0)) ]);
10950 else
10951 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10952 reg_names[ REGNO (XEXP (x, 1)) ]);
10953 }
10954 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10955 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10956 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10957 #if TARGET_ELF
10958 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10959 && CONSTANT_P (XEXP (x, 1)))
10960 {
10961 output_addr_const (file, XEXP (x, 1));
10962 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10963 }
10964 #endif
10965 #if TARGET_MACHO
10966 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10967 && CONSTANT_P (XEXP (x, 1)))
10968 {
10969 fprintf (file, "lo16(");
10970 output_addr_const (file, XEXP (x, 1));
10971 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10972 }
10973 #endif
10974 else if (legitimate_constant_pool_address_p (x))
10975 {
10976 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10977 {
10978 rtx contains_minus = XEXP (x, 1);
10979 rtx minus, symref;
10980 const char *name;
10981
10982 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10983 turn it into (sym) for output_addr_const. */
10984 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10985 contains_minus = XEXP (contains_minus, 0);
10986
10987 minus = XEXP (contains_minus, 0);
10988 symref = XEXP (minus, 0);
10989 XEXP (contains_minus, 0) = symref;
10990 if (TARGET_ELF)
10991 {
10992 char *newname;
10993
10994 name = XSTR (symref, 0);
10995 newname = alloca (strlen (name) + sizeof ("@toc"));
10996 strcpy (newname, name);
10997 strcat (newname, "@toc");
10998 XSTR (symref, 0) = newname;
10999 }
11000 output_addr_const (file, XEXP (x, 1));
11001 if (TARGET_ELF)
11002 XSTR (symref, 0) = name;
11003 XEXP (contains_minus, 0) = minus;
11004 }
11005 else
11006 output_addr_const (file, XEXP (x, 1));
11007
11008 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11009 }
11010 else
11011 gcc_unreachable ();
11012 }
11013
11014 /* Target hook for assembling integer objects. The PowerPC version has
11015 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11016 is defined. It also needs to handle DI-mode objects on 64-bit
11017 targets. */
11018
11019 static bool
rs6000_assemble_integer(rtx x,unsigned int size,int aligned_p)11020 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11021 {
11022 #ifdef RELOCATABLE_NEEDS_FIXUP
11023 /* Special handling for SI values. */
11024 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11025 {
11026 static int recurse = 0;
11027
11028 /* For -mrelocatable, we mark all addresses that need to be fixed up
11029 in the .fixup section. */
11030 if (TARGET_RELOCATABLE
11031 && in_section != toc_section
11032 && in_section != text_section
11033 && !unlikely_text_section_p (in_section)
11034 && !recurse
11035 && GET_CODE (x) != CONST_INT
11036 && GET_CODE (x) != CONST_DOUBLE
11037 && CONSTANT_P (x))
11038 {
11039 char buf[256];
11040
11041 recurse = 1;
11042 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11043 fixuplabelno++;
11044 ASM_OUTPUT_LABEL (asm_out_file, buf);
11045 fprintf (asm_out_file, "\t.long\t(");
11046 output_addr_const (asm_out_file, x);
11047 fprintf (asm_out_file, ")@fixup\n");
11048 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11049 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11050 fprintf (asm_out_file, "\t.long\t");
11051 assemble_name (asm_out_file, buf);
11052 fprintf (asm_out_file, "\n\t.previous\n");
11053 recurse = 0;
11054 return true;
11055 }
11056 /* Remove initial .'s to turn a -mcall-aixdesc function
11057 address into the address of the descriptor, not the function
11058 itself. */
11059 else if (GET_CODE (x) == SYMBOL_REF
11060 && XSTR (x, 0)[0] == '.'
11061 && DEFAULT_ABI == ABI_AIX)
11062 {
11063 const char *name = XSTR (x, 0);
11064 while (*name == '.')
11065 name++;
11066
11067 fprintf (asm_out_file, "\t.long\t%s\n", name);
11068 return true;
11069 }
11070 }
11071 #endif /* RELOCATABLE_NEEDS_FIXUP */
11072 return default_assemble_integer (x, size, aligned_p);
11073 }
11074
11075 #ifdef HAVE_GAS_HIDDEN
11076 /* Emit an assembler directive to set symbol visibility for DECL to
11077 VISIBILITY_TYPE. */
11078
11079 static void
rs6000_assemble_visibility(tree decl,int vis)11080 rs6000_assemble_visibility (tree decl, int vis)
11081 {
11082 /* Functions need to have their entry point symbol visibility set as
11083 well as their descriptor symbol visibility. */
11084 if (DEFAULT_ABI == ABI_AIX
11085 && DOT_SYMBOLS
11086 && TREE_CODE (decl) == FUNCTION_DECL)
11087 {
11088 static const char * const visibility_types[] = {
11089 NULL, "internal", "hidden", "protected"
11090 };
11091
11092 const char *name, *type;
11093
11094 name = ((* targetm.strip_name_encoding)
11095 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11096 type = visibility_types[vis];
11097
11098 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11099 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11100 }
11101 else
11102 default_assemble_visibility (decl, vis);
11103 }
11104 #endif
11105
11106 enum rtx_code
rs6000_reverse_condition(enum machine_mode mode,enum rtx_code code)11107 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11108 {
11109 /* Reversal of FP compares takes care -- an ordered compare
11110 becomes an unordered compare and vice versa. */
11111 if (mode == CCFPmode
11112 && (!flag_finite_math_only
11113 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11114 || code == UNEQ || code == LTGT))
11115 return reverse_condition_maybe_unordered (code);
11116 else
11117 return reverse_condition (code);
11118 }
11119
11120 /* Generate a compare for CODE. Return a brand-new rtx that
11121 represents the result of the compare. */
11122
11123 static rtx
rs6000_generate_compare(enum rtx_code code)11124 rs6000_generate_compare (enum rtx_code code)
11125 {
11126 enum machine_mode comp_mode;
11127 rtx compare_result;
11128
11129 if (rs6000_compare_fp_p)
11130 comp_mode = CCFPmode;
11131 else if (code == GTU || code == LTU
11132 || code == GEU || code == LEU)
11133 comp_mode = CCUNSmode;
11134 else if ((code == EQ || code == NE)
11135 && GET_CODE (rs6000_compare_op0) == SUBREG
11136 && GET_CODE (rs6000_compare_op1) == SUBREG
11137 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11138 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11139 /* These are unsigned values, perhaps there will be a later
11140 ordering compare that can be shared with this one.
11141 Unfortunately we cannot detect the signedness of the operands
11142 for non-subregs. */
11143 comp_mode = CCUNSmode;
11144 else
11145 comp_mode = CCmode;
11146
11147 /* First, the compare. */
11148 compare_result = gen_reg_rtx (comp_mode);
11149
11150 /* E500 FP compare instructions on the GPRs. Yuck! */
11151 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11152 && rs6000_compare_fp_p)
11153 {
11154 rtx cmp, or_result, compare_result2;
11155 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11156
11157 if (op_mode == VOIDmode)
11158 op_mode = GET_MODE (rs6000_compare_op1);
11159
11160 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11161 This explains the following mess. */
11162
11163 switch (code)
11164 {
11165 case EQ: case UNEQ: case NE: case LTGT:
11166 switch (op_mode)
11167 {
11168 case SFmode:
11169 cmp = flag_unsafe_math_optimizations
11170 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11171 rs6000_compare_op1)
11172 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11173 rs6000_compare_op1);
11174 break;
11175
11176 case DFmode:
11177 cmp = flag_unsafe_math_optimizations
11178 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11179 rs6000_compare_op1)
11180 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11181 rs6000_compare_op1);
11182 break;
11183
11184 default:
11185 gcc_unreachable ();
11186 }
11187 break;
11188
11189 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11190 switch (op_mode)
11191 {
11192 case SFmode:
11193 cmp = flag_unsafe_math_optimizations
11194 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11195 rs6000_compare_op1)
11196 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11197 rs6000_compare_op1);
11198 break;
11199
11200 case DFmode:
11201 cmp = flag_unsafe_math_optimizations
11202 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11203 rs6000_compare_op1)
11204 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11205 rs6000_compare_op1);
11206 break;
11207
11208 default:
11209 gcc_unreachable ();
11210 }
11211 break;
11212
11213 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11214 switch (op_mode)
11215 {
11216 case SFmode:
11217 cmp = flag_unsafe_math_optimizations
11218 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11219 rs6000_compare_op1)
11220 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11221 rs6000_compare_op1);
11222 break;
11223
11224 case DFmode:
11225 cmp = flag_unsafe_math_optimizations
11226 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11227 rs6000_compare_op1)
11228 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11229 rs6000_compare_op1);
11230 break;
11231
11232 default:
11233 gcc_unreachable ();
11234 }
11235 break;
11236 default:
11237 gcc_unreachable ();
11238 }
11239
11240 /* Synthesize LE and GE from LT/GT || EQ. */
11241 if (code == LE || code == GE || code == LEU || code == GEU)
11242 {
11243 emit_insn (cmp);
11244
11245 switch (code)
11246 {
11247 case LE: code = LT; break;
11248 case GE: code = GT; break;
11249 case LEU: code = LT; break;
11250 case GEU: code = GT; break;
11251 default: gcc_unreachable ();
11252 }
11253
11254 compare_result2 = gen_reg_rtx (CCFPmode);
11255
11256 /* Do the EQ. */
11257 switch (op_mode)
11258 {
11259 case SFmode:
11260 cmp = flag_unsafe_math_optimizations
11261 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11262 rs6000_compare_op1)
11263 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11264 rs6000_compare_op1);
11265 break;
11266
11267 case DFmode:
11268 cmp = flag_unsafe_math_optimizations
11269 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11270 rs6000_compare_op1)
11271 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11272 rs6000_compare_op1);
11273 break;
11274
11275 default:
11276 gcc_unreachable ();
11277 }
11278 emit_insn (cmp);
11279
11280 /* OR them together. */
11281 or_result = gen_reg_rtx (CCFPmode);
11282 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11283 compare_result2);
11284 compare_result = or_result;
11285 code = EQ;
11286 }
11287 else
11288 {
11289 if (code == NE || code == LTGT)
11290 code = NE;
11291 else
11292 code = EQ;
11293 }
11294
11295 emit_insn (cmp);
11296 }
11297 else
11298 {
11299 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11300 CLOBBERs to match cmptf_internal2 pattern. */
11301 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11302 && GET_MODE (rs6000_compare_op0) == TFmode
11303 && !TARGET_IEEEQUAD
11304 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11305 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11306 gen_rtvec (9,
11307 gen_rtx_SET (VOIDmode,
11308 compare_result,
11309 gen_rtx_COMPARE (comp_mode,
11310 rs6000_compare_op0,
11311 rs6000_compare_op1)),
11312 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11313 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11314 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11315 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11316 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11317 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11318 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11319 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11320 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11321 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11322 {
11323 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11324 comp_mode = CCEQmode;
11325 compare_result = gen_reg_rtx (CCEQmode);
11326 if (TARGET_64BIT)
11327 emit_insn (gen_stack_protect_testdi (compare_result,
11328 rs6000_compare_op0, op1));
11329 else
11330 emit_insn (gen_stack_protect_testsi (compare_result,
11331 rs6000_compare_op0, op1));
11332 }
11333 else
11334 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11335 gen_rtx_COMPARE (comp_mode,
11336 rs6000_compare_op0,
11337 rs6000_compare_op1)));
11338 }
11339
11340 /* Some kinds of FP comparisons need an OR operation;
11341 under flag_finite_math_only we don't bother. */
11342 if (rs6000_compare_fp_p
11343 && !flag_finite_math_only
11344 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11345 && (code == LE || code == GE
11346 || code == UNEQ || code == LTGT
11347 || code == UNGT || code == UNLT))
11348 {
11349 enum rtx_code or1, or2;
11350 rtx or1_rtx, or2_rtx, compare2_rtx;
11351 rtx or_result = gen_reg_rtx (CCEQmode);
11352
11353 switch (code)
11354 {
11355 case LE: or1 = LT; or2 = EQ; break;
11356 case GE: or1 = GT; or2 = EQ; break;
11357 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11358 case LTGT: or1 = LT; or2 = GT; break;
11359 case UNGT: or1 = UNORDERED; or2 = GT; break;
11360 case UNLT: or1 = UNORDERED; or2 = LT; break;
11361 default: gcc_unreachable ();
11362 }
11363 validate_condition_mode (or1, comp_mode);
11364 validate_condition_mode (or2, comp_mode);
11365 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11366 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11367 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11368 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11369 const_true_rtx);
11370 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11371
11372 compare_result = or_result;
11373 code = EQ;
11374 }
11375
11376 validate_condition_mode (code, GET_MODE (compare_result));
11377
11378 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11379 }
11380
11381
11382 /* Emit the RTL for an sCOND pattern. */
11383
11384 void
rs6000_emit_sCOND(enum rtx_code code,rtx result)11385 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11386 {
11387 rtx condition_rtx;
11388 enum machine_mode op_mode;
11389 enum rtx_code cond_code;
11390
11391 condition_rtx = rs6000_generate_compare (code);
11392 cond_code = GET_CODE (condition_rtx);
11393
11394 if (TARGET_E500 && rs6000_compare_fp_p
11395 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11396 {
11397 rtx t;
11398
11399 PUT_MODE (condition_rtx, SImode);
11400 t = XEXP (condition_rtx, 0);
11401
11402 gcc_assert (cond_code == NE || cond_code == EQ);
11403
11404 if (cond_code == NE)
11405 emit_insn (gen_e500_flip_gt_bit (t, t));
11406
11407 emit_insn (gen_move_from_CR_gt_bit (result, t));
11408 return;
11409 }
11410
11411 if (cond_code == NE
11412 || cond_code == GE || cond_code == LE
11413 || cond_code == GEU || cond_code == LEU
11414 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11415 {
11416 rtx not_result = gen_reg_rtx (CCEQmode);
11417 rtx not_op, rev_cond_rtx;
11418 enum machine_mode cc_mode;
11419
11420 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11421
11422 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11423 SImode, XEXP (condition_rtx, 0), const0_rtx);
11424 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11425 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11426 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11427 }
11428
11429 op_mode = GET_MODE (rs6000_compare_op0);
11430 if (op_mode == VOIDmode)
11431 op_mode = GET_MODE (rs6000_compare_op1);
11432
11433 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11434 {
11435 PUT_MODE (condition_rtx, DImode);
11436 convert_move (result, condition_rtx, 0);
11437 }
11438 else
11439 {
11440 PUT_MODE (condition_rtx, SImode);
11441 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11442 }
11443 }
11444
11445 /* Emit a branch of kind CODE to location LOC. */
11446
11447 void
rs6000_emit_cbranch(enum rtx_code code,rtx loc)11448 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11449 {
11450 rtx condition_rtx, loc_ref;
11451
11452 condition_rtx = rs6000_generate_compare (code);
11453 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11454 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11455 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11456 loc_ref, pc_rtx)));
11457 }
11458
11459 /* Return the string to output a conditional branch to LABEL, which is
11460 the operand number of the label, or -1 if the branch is really a
11461 conditional return.
11462
11463 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11464 condition code register and its mode specifies what kind of
11465 comparison we made.
11466
11467 REVERSED is nonzero if we should reverse the sense of the comparison.
11468
11469 INSN is the insn. */
11470
11471 char *
output_cbranch(rtx op,const char * label,int reversed,rtx insn)11472 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11473 {
11474 static char string[64];
11475 enum rtx_code code = GET_CODE (op);
11476 rtx cc_reg = XEXP (op, 0);
11477 enum machine_mode mode = GET_MODE (cc_reg);
11478 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11479 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11480 int really_reversed = reversed ^ need_longbranch;
11481 char *s = string;
11482 const char *ccode;
11483 const char *pred;
11484 rtx note;
11485
11486 validate_condition_mode (code, mode);
11487
11488 /* Work out which way this really branches. We could use
11489 reverse_condition_maybe_unordered here always but this
11490 makes the resulting assembler clearer. */
11491 if (really_reversed)
11492 {
11493 /* Reversal of FP compares takes care -- an ordered compare
11494 becomes an unordered compare and vice versa. */
11495 if (mode == CCFPmode)
11496 code = reverse_condition_maybe_unordered (code);
11497 else
11498 code = reverse_condition (code);
11499 }
11500
11501 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11502 {
11503 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11504 to the GT bit. */
11505 switch (code)
11506 {
11507 case EQ:
11508 /* Opposite of GT. */
11509 code = GT;
11510 break;
11511
11512 case NE:
11513 code = UNLE;
11514 break;
11515
11516 default:
11517 gcc_unreachable ();
11518 }
11519 }
11520
11521 switch (code)
11522 {
11523 /* Not all of these are actually distinct opcodes, but
11524 we distinguish them for clarity of the resulting assembler. */
11525 case NE: case LTGT:
11526 ccode = "ne"; break;
11527 case EQ: case UNEQ:
11528 ccode = "eq"; break;
11529 case GE: case GEU:
11530 ccode = "ge"; break;
11531 case GT: case GTU: case UNGT:
11532 ccode = "gt"; break;
11533 case LE: case LEU:
11534 ccode = "le"; break;
11535 case LT: case LTU: case UNLT:
11536 ccode = "lt"; break;
11537 case UNORDERED: ccode = "un"; break;
11538 case ORDERED: ccode = "nu"; break;
11539 case UNGE: ccode = "nl"; break;
11540 case UNLE: ccode = "ng"; break;
11541 default:
11542 gcc_unreachable ();
11543 }
11544
11545 /* Maybe we have a guess as to how likely the branch is.
11546 The old mnemonics don't have a way to specify this information. */
11547 pred = "";
11548 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11549 if (note != NULL_RTX)
11550 {
11551 /* PROB is the difference from 50%. */
11552 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11553
11554 /* Only hint for highly probable/improbable branches on newer
11555 cpus as static prediction overrides processor dynamic
11556 prediction. For older cpus we may as well always hint, but
11557 assume not taken for branches that are very close to 50% as a
11558 mispredicted taken branch is more expensive than a
11559 mispredicted not-taken branch. */
11560 if (rs6000_always_hint
11561 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
11562 && br_prob_note_reliable_p (note)))
11563 {
11564 if (abs (prob) > REG_BR_PROB_BASE / 20
11565 && ((prob > 0) ^ need_longbranch))
11566 pred = "+";
11567 else
11568 pred = "-";
11569 }
11570 }
11571
11572 if (label == NULL)
11573 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11574 else
11575 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11576
11577 /* We need to escape any '%' characters in the reg_names string.
11578 Assume they'd only be the first character.... */
11579 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11580 *s++ = '%';
11581 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11582
11583 if (label != NULL)
11584 {
11585 /* If the branch distance was too far, we may have to use an
11586 unconditional branch to go the distance. */
11587 if (need_longbranch)
11588 s += sprintf (s, ",$+8\n\tb %s", label);
11589 else
11590 s += sprintf (s, ",%s", label);
11591 }
11592
11593 return string;
11594 }
11595
11596 /* Return the string to flip the GT bit on a CR. */
11597 char *
output_e500_flip_gt_bit(rtx dst,rtx src)11598 output_e500_flip_gt_bit (rtx dst, rtx src)
11599 {
11600 static char string[64];
11601 int a, b;
11602
11603 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11604 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11605
11606 /* GT bit. */
11607 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11608 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11609
11610 sprintf (string, "crnot %d,%d", a, b);
11611 return string;
11612 }
11613
11614 /* Return insn index for the vector compare instruction for given CODE,
11615 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11616 not available. */
11617
11618 static int
get_vec_cmp_insn(enum rtx_code code,enum machine_mode dest_mode,enum machine_mode op_mode)11619 get_vec_cmp_insn (enum rtx_code code,
11620 enum machine_mode dest_mode,
11621 enum machine_mode op_mode)
11622 {
11623 if (!TARGET_ALTIVEC)
11624 return INSN_NOT_AVAILABLE;
11625
11626 switch (code)
11627 {
11628 case EQ:
11629 if (dest_mode == V16QImode && op_mode == V16QImode)
11630 return UNSPEC_VCMPEQUB;
11631 if (dest_mode == V8HImode && op_mode == V8HImode)
11632 return UNSPEC_VCMPEQUH;
11633 if (dest_mode == V4SImode && op_mode == V4SImode)
11634 return UNSPEC_VCMPEQUW;
11635 if (dest_mode == V4SImode && op_mode == V4SFmode)
11636 return UNSPEC_VCMPEQFP;
11637 break;
11638 case GE:
11639 if (dest_mode == V4SImode && op_mode == V4SFmode)
11640 return UNSPEC_VCMPGEFP;
11641 case GT:
11642 if (dest_mode == V16QImode && op_mode == V16QImode)
11643 return UNSPEC_VCMPGTSB;
11644 if (dest_mode == V8HImode && op_mode == V8HImode)
11645 return UNSPEC_VCMPGTSH;
11646 if (dest_mode == V4SImode && op_mode == V4SImode)
11647 return UNSPEC_VCMPGTSW;
11648 if (dest_mode == V4SImode && op_mode == V4SFmode)
11649 return UNSPEC_VCMPGTFP;
11650 break;
11651 case GTU:
11652 if (dest_mode == V16QImode && op_mode == V16QImode)
11653 return UNSPEC_VCMPGTUB;
11654 if (dest_mode == V8HImode && op_mode == V8HImode)
11655 return UNSPEC_VCMPGTUH;
11656 if (dest_mode == V4SImode && op_mode == V4SImode)
11657 return UNSPEC_VCMPGTUW;
11658 break;
11659 default:
11660 break;
11661 }
11662 return INSN_NOT_AVAILABLE;
11663 }
11664
11665 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11666 DMODE is expected destination mode. This is a recursive function. */
11667
11668 static rtx
rs6000_emit_vector_compare(enum rtx_code rcode,rtx op0,rtx op1,enum machine_mode dmode)11669 rs6000_emit_vector_compare (enum rtx_code rcode,
11670 rtx op0, rtx op1,
11671 enum machine_mode dmode)
11672 {
11673 int vec_cmp_insn;
11674 rtx mask;
11675 enum machine_mode dest_mode;
11676 enum machine_mode op_mode = GET_MODE (op1);
11677
11678 gcc_assert (TARGET_ALTIVEC);
11679 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11680
11681 /* Floating point vector compare instructions uses destination V4SImode.
11682 Move destination to appropriate mode later. */
11683 if (dmode == V4SFmode)
11684 dest_mode = V4SImode;
11685 else
11686 dest_mode = dmode;
11687
11688 mask = gen_reg_rtx (dest_mode);
11689 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11690
11691 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11692 {
11693 bool swap_operands = false;
11694 bool try_again = false;
11695 switch (rcode)
11696 {
11697 case LT:
11698 rcode = GT;
11699 swap_operands = true;
11700 try_again = true;
11701 break;
11702 case LTU:
11703 rcode = GTU;
11704 swap_operands = true;
11705 try_again = true;
11706 break;
11707 case NE:
11708 /* Treat A != B as ~(A==B). */
11709 {
11710 enum insn_code nor_code;
11711 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11712 dest_mode);
11713
11714 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11715 gcc_assert (nor_code != CODE_FOR_nothing);
11716 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11717
11718 if (dmode != dest_mode)
11719 {
11720 rtx temp = gen_reg_rtx (dest_mode);
11721 convert_move (temp, mask, 0);
11722 return temp;
11723 }
11724 return mask;
11725 }
11726 break;
11727 case GE:
11728 case GEU:
11729 case LE:
11730 case LEU:
11731 /* Try GT/GTU/LT/LTU OR EQ */
11732 {
11733 rtx c_rtx, eq_rtx;
11734 enum insn_code ior_code;
11735 enum rtx_code new_code;
11736
11737 switch (rcode)
11738 {
11739 case GE:
11740 new_code = GT;
11741 break;
11742
11743 case GEU:
11744 new_code = GTU;
11745 break;
11746
11747 case LE:
11748 new_code = LT;
11749 break;
11750
11751 case LEU:
11752 new_code = LTU;
11753 break;
11754
11755 default:
11756 gcc_unreachable ();
11757 }
11758
11759 c_rtx = rs6000_emit_vector_compare (new_code,
11760 op0, op1, dest_mode);
11761 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11762 dest_mode);
11763
11764 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11765 gcc_assert (ior_code != CODE_FOR_nothing);
11766 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11767 if (dmode != dest_mode)
11768 {
11769 rtx temp = gen_reg_rtx (dest_mode);
11770 convert_move (temp, mask, 0);
11771 return temp;
11772 }
11773 return mask;
11774 }
11775 break;
11776 default:
11777 gcc_unreachable ();
11778 }
11779
11780 if (try_again)
11781 {
11782 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11783 /* You only get two chances. */
11784 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11785 }
11786
11787 if (swap_operands)
11788 {
11789 rtx tmp;
11790 tmp = op0;
11791 op0 = op1;
11792 op1 = tmp;
11793 }
11794 }
11795
11796 emit_insn (gen_rtx_SET (VOIDmode, mask,
11797 gen_rtx_UNSPEC (dest_mode,
11798 gen_rtvec (2, op0, op1),
11799 vec_cmp_insn)));
11800 if (dmode != dest_mode)
11801 {
11802 rtx temp = gen_reg_rtx (dest_mode);
11803 convert_move (temp, mask, 0);
11804 return temp;
11805 }
11806 return mask;
11807 }
11808
11809 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11810 valid insn doesn exist for given mode. */
11811
11812 static int
get_vsel_insn(enum machine_mode mode)11813 get_vsel_insn (enum machine_mode mode)
11814 {
11815 switch (mode)
11816 {
11817 case V4SImode:
11818 return UNSPEC_VSEL4SI;
11819 break;
11820 case V4SFmode:
11821 return UNSPEC_VSEL4SF;
11822 break;
11823 case V8HImode:
11824 return UNSPEC_VSEL8HI;
11825 break;
11826 case V16QImode:
11827 return UNSPEC_VSEL16QI;
11828 break;
11829 default:
11830 return INSN_NOT_AVAILABLE;
11831 break;
11832 }
11833 return INSN_NOT_AVAILABLE;
11834 }
11835
11836 /* Emit vector select insn where DEST is destination using
11837 operands OP1, OP2 and MASK. */
11838
11839 static void
rs6000_emit_vector_select(rtx dest,rtx op1,rtx op2,rtx mask)11840 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11841 {
11842 rtx t, temp;
11843 enum machine_mode dest_mode = GET_MODE (dest);
11844 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11845
11846 temp = gen_reg_rtx (dest_mode);
11847
11848 /* For each vector element, select op1 when mask is 1 otherwise
11849 select op2. */
11850 t = gen_rtx_SET (VOIDmode, temp,
11851 gen_rtx_UNSPEC (dest_mode,
11852 gen_rtvec (3, op2, op1, mask),
11853 vsel_insn_index));
11854 emit_insn (t);
11855 emit_move_insn (dest, temp);
11856 return;
11857 }
11858
11859 /* Emit vector conditional expression.
11860 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11861 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11862
11863 int
rs6000_emit_vector_cond_expr(rtx dest,rtx op1,rtx op2,rtx cond,rtx cc_op0,rtx cc_op1)11864 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11865 rtx cond, rtx cc_op0, rtx cc_op1)
11866 {
11867 enum machine_mode dest_mode = GET_MODE (dest);
11868 enum rtx_code rcode = GET_CODE (cond);
11869 rtx mask;
11870
11871 if (!TARGET_ALTIVEC)
11872 return 0;
11873
11874 /* Get the vector mask for the given relational operations. */
11875 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11876
11877 rs6000_emit_vector_select (dest, op1, op2, mask);
11878
11879 return 1;
11880 }
11881
11882 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11883 operands of the last comparison is nonzero/true, FALSE_COND if it
11884 is zero/false. Return 0 if the hardware has no such operation. */
11885
11886 int
rs6000_emit_cmove(rtx dest,rtx op,rtx true_cond,rtx false_cond)11887 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11888 {
11889 enum rtx_code code = GET_CODE (op);
11890 rtx op0 = rs6000_compare_op0;
11891 rtx op1 = rs6000_compare_op1;
11892 REAL_VALUE_TYPE c1;
11893 enum machine_mode compare_mode = GET_MODE (op0);
11894 enum machine_mode result_mode = GET_MODE (dest);
11895 rtx temp;
11896 bool is_against_zero;
11897
11898 /* These modes should always match. */
11899 if (GET_MODE (op1) != compare_mode
11900 /* In the isel case however, we can use a compare immediate, so
11901 op1 may be a small constant. */
11902 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11903 return 0;
11904 if (GET_MODE (true_cond) != result_mode)
11905 return 0;
11906 if (GET_MODE (false_cond) != result_mode)
11907 return 0;
11908
11909 /* First, work out if the hardware can do this at all, or
11910 if it's too slow.... */
11911 if (! rs6000_compare_fp_p)
11912 {
11913 if (TARGET_ISEL)
11914 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11915 return 0;
11916 }
11917 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11918 && SCALAR_FLOAT_MODE_P (compare_mode))
11919 return 0;
11920
11921 is_against_zero = op1 == CONST0_RTX (compare_mode);
11922
11923 /* A floating-point subtract might overflow, underflow, or produce
11924 an inexact result, thus changing the floating-point flags, so it
11925 can't be generated if we care about that. It's safe if one side
11926 of the construct is zero, since then no subtract will be
11927 generated. */
11928 if (SCALAR_FLOAT_MODE_P (compare_mode)
11929 && flag_trapping_math && ! is_against_zero)
11930 return 0;
11931
11932 /* Eliminate half of the comparisons by switching operands, this
11933 makes the remaining code simpler. */
11934 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11935 || code == LTGT || code == LT || code == UNLE)
11936 {
11937 code = reverse_condition_maybe_unordered (code);
11938 temp = true_cond;
11939 true_cond = false_cond;
11940 false_cond = temp;
11941 }
11942
11943 /* UNEQ and LTGT take four instructions for a comparison with zero,
11944 it'll probably be faster to use a branch here too. */
11945 if (code == UNEQ && HONOR_NANS (compare_mode))
11946 return 0;
11947
11948 if (GET_CODE (op1) == CONST_DOUBLE)
11949 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11950
11951 /* We're going to try to implement comparisons by performing
11952 a subtract, then comparing against zero. Unfortunately,
11953 Inf - Inf is NaN which is not zero, and so if we don't
11954 know that the operand is finite and the comparison
11955 would treat EQ different to UNORDERED, we can't do it. */
11956 if (HONOR_INFINITIES (compare_mode)
11957 && code != GT && code != UNGE
11958 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11959 /* Constructs of the form (a OP b ? a : b) are safe. */
11960 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11961 || (! rtx_equal_p (op0, true_cond)
11962 && ! rtx_equal_p (op1, true_cond))))
11963 return 0;
11964
11965 /* At this point we know we can use fsel. */
11966
11967 /* Reduce the comparison to a comparison against zero. */
11968 if (! is_against_zero)
11969 {
11970 temp = gen_reg_rtx (compare_mode);
11971 emit_insn (gen_rtx_SET (VOIDmode, temp,
11972 gen_rtx_MINUS (compare_mode, op0, op1)));
11973 op0 = temp;
11974 op1 = CONST0_RTX (compare_mode);
11975 }
11976
11977 /* If we don't care about NaNs we can reduce some of the comparisons
11978 down to faster ones. */
11979 if (! HONOR_NANS (compare_mode))
11980 switch (code)
11981 {
11982 case GT:
11983 code = LE;
11984 temp = true_cond;
11985 true_cond = false_cond;
11986 false_cond = temp;
11987 break;
11988 case UNGE:
11989 code = GE;
11990 break;
11991 case UNEQ:
11992 code = EQ;
11993 break;
11994 default:
11995 break;
11996 }
11997
11998 /* Now, reduce everything down to a GE. */
11999 switch (code)
12000 {
12001 case GE:
12002 break;
12003
12004 case LE:
12005 temp = gen_reg_rtx (compare_mode);
12006 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12007 op0 = temp;
12008 break;
12009
12010 case ORDERED:
12011 temp = gen_reg_rtx (compare_mode);
12012 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12013 op0 = temp;
12014 break;
12015
12016 case EQ:
12017 temp = gen_reg_rtx (compare_mode);
12018 emit_insn (gen_rtx_SET (VOIDmode, temp,
12019 gen_rtx_NEG (compare_mode,
12020 gen_rtx_ABS (compare_mode, op0))));
12021 op0 = temp;
12022 break;
12023
12024 case UNGE:
12025 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12026 temp = gen_reg_rtx (result_mode);
12027 emit_insn (gen_rtx_SET (VOIDmode, temp,
12028 gen_rtx_IF_THEN_ELSE (result_mode,
12029 gen_rtx_GE (VOIDmode,
12030 op0, op1),
12031 true_cond, false_cond)));
12032 false_cond = true_cond;
12033 true_cond = temp;
12034
12035 temp = gen_reg_rtx (compare_mode);
12036 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12037 op0 = temp;
12038 break;
12039
12040 case GT:
12041 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12042 temp = gen_reg_rtx (result_mode);
12043 emit_insn (gen_rtx_SET (VOIDmode, temp,
12044 gen_rtx_IF_THEN_ELSE (result_mode,
12045 gen_rtx_GE (VOIDmode,
12046 op0, op1),
12047 true_cond, false_cond)));
12048 true_cond = false_cond;
12049 false_cond = temp;
12050
12051 temp = gen_reg_rtx (compare_mode);
12052 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12053 op0 = temp;
12054 break;
12055
12056 default:
12057 gcc_unreachable ();
12058 }
12059
12060 emit_insn (gen_rtx_SET (VOIDmode, dest,
12061 gen_rtx_IF_THEN_ELSE (result_mode,
12062 gen_rtx_GE (VOIDmode,
12063 op0, op1),
12064 true_cond, false_cond)));
12065 return 1;
12066 }
12067
12068 /* Same as above, but for ints (isel). */
12069
12070 static int
rs6000_emit_int_cmove(rtx dest,rtx op,rtx true_cond,rtx false_cond)12071 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12072 {
12073 rtx condition_rtx, cr;
12074
12075 /* All isel implementations thus far are 32-bits. */
12076 if (GET_MODE (rs6000_compare_op0) != SImode)
12077 return 0;
12078
12079 /* We still have to do the compare, because isel doesn't do a
12080 compare, it just looks at the CRx bits set by a previous compare
12081 instruction. */
12082 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12083 cr = XEXP (condition_rtx, 0);
12084
12085 if (GET_MODE (cr) == CCmode)
12086 emit_insn (gen_isel_signed (dest, condition_rtx,
12087 true_cond, false_cond, cr));
12088 else
12089 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12090 true_cond, false_cond, cr));
12091
12092 return 1;
12093 }
12094
12095 const char *
output_isel(rtx * operands)12096 output_isel (rtx *operands)
12097 {
12098 enum rtx_code code;
12099
12100 code = GET_CODE (operands[1]);
12101 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12102 {
12103 PUT_CODE (operands[1], reverse_condition (code));
12104 return "isel %0,%3,%2,%j1";
12105 }
12106 else
12107 return "isel %0,%2,%3,%j1";
12108 }
12109
12110 void
rs6000_emit_minmax(rtx dest,enum rtx_code code,rtx op0,rtx op1)12111 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12112 {
12113 enum machine_mode mode = GET_MODE (op0);
12114 enum rtx_code c;
12115 rtx target;
12116
12117 if (code == SMAX || code == SMIN)
12118 c = GE;
12119 else
12120 c = GEU;
12121
12122 if (code == SMAX || code == UMAX)
12123 target = emit_conditional_move (dest, c, op0, op1, mode,
12124 op0, op1, mode, 0);
12125 else
12126 target = emit_conditional_move (dest, c, op0, op1, mode,
12127 op1, op0, mode, 0);
12128 gcc_assert (target);
12129 if (target != dest)
12130 emit_move_insn (dest, target);
12131 }
12132
12133 /* Emit instructions to perform a load-reserved/store-conditional operation.
12134 The operation performed is an atomic
12135 (set M (CODE:MODE M OP))
12136 If not NULL, BEFORE is atomically set to M before the operation, and
12137 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12138 If SYNC_P then a memory barrier is emitted before the operation.
12139 Either OP or M may be wrapped in a NOT operation. */
12140
12141 void
rs6000_emit_sync(enum rtx_code code,enum machine_mode mode,rtx m,rtx op,rtx before_param,rtx after_param,bool sync_p)12142 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12143 rtx m, rtx op, rtx before_param, rtx after_param,
12144 bool sync_p)
12145 {
12146 enum machine_mode used_mode;
12147 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12148 rtx used_m;
12149 rtvec vec;
12150 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12151 rtx shift = NULL_RTX;
12152
12153 if (sync_p)
12154 emit_insn (gen_memory_barrier ());
12155
12156 if (GET_CODE (m) == NOT)
12157 used_m = XEXP (m, 0);
12158 else
12159 used_m = m;
12160
12161 /* If this is smaller than SImode, we'll have to use SImode with
12162 adjustments. */
12163 if (mode == QImode || mode == HImode)
12164 {
12165 rtx newop, oldop;
12166
12167 if (MEM_ALIGN (used_m) >= 32)
12168 {
12169 int ishift = 0;
12170 if (BYTES_BIG_ENDIAN)
12171 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12172
12173 shift = GEN_INT (ishift);
12174 }
12175 else
12176 {
12177 rtx addrSI, aligned_addr;
12178 int shift_mask = mode == QImode ? 0x18 : 0x10;
12179
12180 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12181 XEXP (used_m, 0)));
12182 shift = gen_reg_rtx (SImode);
12183
12184 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12185 GEN_INT (shift_mask)));
12186 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12187
12188 aligned_addr = expand_binop (Pmode, and_optab,
12189 XEXP (used_m, 0),
12190 GEN_INT (-4), NULL_RTX,
12191 1, OPTAB_LIB_WIDEN);
12192 used_m = change_address (used_m, SImode, aligned_addr);
12193 set_mem_align (used_m, 32);
12194 /* It's safe to keep the old alias set of USED_M, because
12195 the operation is atomic and only affects the original
12196 USED_M. */
12197 if (GET_CODE (m) == NOT)
12198 m = gen_rtx_NOT (SImode, used_m);
12199 else
12200 m = used_m;
12201 }
12202
12203 if (GET_CODE (op) == NOT)
12204 {
12205 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12206 oldop = gen_rtx_NOT (SImode, oldop);
12207 }
12208 else
12209 oldop = lowpart_subreg (SImode, op, mode);
12210
12211 switch (code)
12212 {
12213 case IOR:
12214 case XOR:
12215 newop = expand_binop (SImode, and_optab,
12216 oldop, GEN_INT (imask), NULL_RTX,
12217 1, OPTAB_LIB_WIDEN);
12218 emit_insn (gen_ashlsi3 (newop, newop, shift));
12219 break;
12220
12221 case AND:
12222 newop = expand_binop (SImode, ior_optab,
12223 oldop, GEN_INT (~imask), NULL_RTX,
12224 1, OPTAB_LIB_WIDEN);
12225 emit_insn (gen_rotlsi3 (newop, newop, shift));
12226 break;
12227
12228 case PLUS:
12229 case MINUS:
12230 {
12231 rtx mask;
12232
12233 newop = expand_binop (SImode, and_optab,
12234 oldop, GEN_INT (imask), NULL_RTX,
12235 1, OPTAB_LIB_WIDEN);
12236 emit_insn (gen_ashlsi3 (newop, newop, shift));
12237
12238 mask = gen_reg_rtx (SImode);
12239 emit_move_insn (mask, GEN_INT (imask));
12240 emit_insn (gen_ashlsi3 (mask, mask, shift));
12241
12242 if (code == PLUS)
12243 newop = gen_rtx_PLUS (SImode, m, newop);
12244 else
12245 newop = gen_rtx_MINUS (SImode, m, newop);
12246 newop = gen_rtx_AND (SImode, newop, mask);
12247 newop = gen_rtx_IOR (SImode, newop,
12248 gen_rtx_AND (SImode,
12249 gen_rtx_NOT (SImode, mask),
12250 m));
12251 break;
12252 }
12253
12254 default:
12255 gcc_unreachable ();
12256 }
12257
12258 if (GET_CODE (m) == NOT)
12259 {
12260 rtx mask, xorm;
12261
12262 mask = gen_reg_rtx (SImode);
12263 emit_move_insn (mask, GEN_INT (imask));
12264 emit_insn (gen_ashlsi3 (mask, mask, shift));
12265
12266 xorm = gen_rtx_XOR (SImode, used_m, mask);
12267 /* Depending on the value of 'op', the XOR or the operation might
12268 be able to be simplified away. */
12269 newop = simplify_gen_binary (code, SImode, xorm, newop);
12270 }
12271 op = newop;
12272 used_mode = SImode;
12273 before = gen_reg_rtx (used_mode);
12274 after = gen_reg_rtx (used_mode);
12275 }
12276 else
12277 {
12278 used_mode = mode;
12279 before = before_param;
12280 after = after_param;
12281
12282 if (before == NULL_RTX)
12283 before = gen_reg_rtx (used_mode);
12284 if (after == NULL_RTX)
12285 after = gen_reg_rtx (used_mode);
12286 }
12287
12288 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12289 && used_mode != mode)
12290 the_op = op; /* Computed above. */
12291 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12292 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12293 else
12294 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12295
12296 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12297 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12298 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12299 gen_rtx_UNSPEC (used_mode,
12300 gen_rtvec (1, the_op),
12301 UNSPEC_SYNC_OP));
12302 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12303
12304 if ((code == PLUS || code == MINUS) && used_mode != mode)
12305 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12306 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12307 else
12308 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12309 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12310
12311 /* Shift and mask the return values properly. */
12312 if (used_mode != mode && before_param)
12313 {
12314 emit_insn (gen_lshrsi3 (before, before, shift));
12315 convert_move (before_param, before, 1);
12316 }
12317
12318 if (used_mode != mode && after_param)
12319 {
12320 emit_insn (gen_lshrsi3 (after, after, shift));
12321 convert_move (after_param, after, 1);
12322 }
12323
12324 /* The previous sequence will end with a branch that's dependent on
12325 the conditional store, so placing an isync will ensure that no
12326 other instructions (especially, no load or store instructions)
12327 can start before the atomic operation completes. */
12328 if (sync_p)
12329 emit_insn (gen_isync ());
12330 }
12331
12332 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12333 COND is true. Mark the jump as unlikely to be taken. */
12334
12335 static void
emit_unlikely_jump(rtx cond,rtx label)12336 emit_unlikely_jump (rtx cond, rtx label)
12337 {
12338 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12339 rtx x;
12340
12341 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12342 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12343 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12344 }
12345
12346 /* A subroutine of the atomic operation splitters. Emit a load-locked
12347 instruction in MODE. */
12348
12349 static void
emit_load_locked(enum machine_mode mode,rtx reg,rtx mem)12350 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12351 {
12352 rtx (*fn) (rtx, rtx) = NULL;
12353 if (mode == SImode)
12354 fn = gen_load_locked_si;
12355 else if (mode == DImode)
12356 fn = gen_load_locked_di;
12357 emit_insn (fn (reg, mem));
12358 }
12359
12360 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12361 instruction in MODE. */
12362
12363 static void
emit_store_conditional(enum machine_mode mode,rtx res,rtx mem,rtx val)12364 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12365 {
12366 rtx (*fn) (rtx, rtx, rtx) = NULL;
12367 if (mode == SImode)
12368 fn = gen_store_conditional_si;
12369 else if (mode == DImode)
12370 fn = gen_store_conditional_di;
12371
12372 /* Emit sync before stwcx. to address PPC405 Erratum. */
12373 if (PPC405_ERRATUM77)
12374 emit_insn (gen_memory_barrier ());
12375
12376 emit_insn (fn (res, mem, val));
12377 }
12378
12379 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12380 to perform. MEM is the memory on which to operate. VAL is the second
12381 operand of the binary operator. BEFORE and AFTER are optional locations to
12382 return the value of MEM either before of after the operation. SCRATCH is
12383 a scratch register. */
12384
12385 void
rs6000_split_atomic_op(enum rtx_code code,rtx mem,rtx val,rtx before,rtx after,rtx scratch)12386 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12387 rtx before, rtx after, rtx scratch)
12388 {
12389 enum machine_mode mode = GET_MODE (mem);
12390 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12391
12392 emit_insn (gen_memory_barrier ());
12393
12394 label = gen_label_rtx ();
12395 emit_label (label);
12396 label = gen_rtx_LABEL_REF (VOIDmode, label);
12397
12398 if (before == NULL_RTX)
12399 before = scratch;
12400 emit_load_locked (mode, before, mem);
12401
12402 if (code == NOT)
12403 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12404 else if (code == AND)
12405 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12406 else
12407 x = gen_rtx_fmt_ee (code, mode, before, val);
12408
12409 if (after != NULL_RTX)
12410 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12411 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12412
12413 emit_store_conditional (mode, cond, mem, scratch);
12414
12415 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12416 emit_unlikely_jump (x, label);
12417
12418 emit_insn (gen_isync ());
12419 }
12420
12421 /* Expand an atomic compare and swap operation. MEM is the memory on which
12422 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12423 value to be stored. SCRATCH is a scratch GPR. */
12424
12425 void
rs6000_split_compare_and_swap(rtx retval,rtx mem,rtx oldval,rtx newval,rtx scratch)12426 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12427 rtx scratch)
12428 {
12429 enum machine_mode mode = GET_MODE (mem);
12430 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12431
12432 emit_insn (gen_memory_barrier ());
12433
12434 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12435 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12436 emit_label (XEXP (label1, 0));
12437
12438 emit_load_locked (mode, retval, mem);
12439
12440 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12441 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12442
12443 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12444 emit_unlikely_jump (x, label2);
12445
12446 emit_move_insn (scratch, newval);
12447 emit_store_conditional (mode, cond, mem, scratch);
12448
12449 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12450 emit_unlikely_jump (x, label1);
12451
12452 emit_insn (gen_isync ());
12453 emit_label (XEXP (label2, 0));
12454 }
12455
12456 /* Expand an atomic test and set operation. MEM is the memory on which
12457 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12458
12459 void
rs6000_split_lock_test_and_set(rtx retval,rtx mem,rtx val,rtx scratch)12460 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12461 {
12462 enum machine_mode mode = GET_MODE (mem);
12463 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12464
12465 emit_insn (gen_memory_barrier ());
12466
12467 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12468 emit_label (XEXP (label, 0));
12469
12470 emit_load_locked (mode, retval, mem);
12471 emit_move_insn (scratch, val);
12472 emit_store_conditional (mode, cond, mem, scratch);
12473
12474 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12475 emit_unlikely_jump (x, label);
12476
12477 emit_insn (gen_isync ());
12478 }
12479
12480 void
rs6000_expand_compare_and_swapqhi(rtx dst,rtx mem,rtx oldval,rtx newval)12481 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12482 {
12483 enum machine_mode mode = GET_MODE (mem);
12484 rtx addrSI, align, wdst, shift, mask;
12485 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12486 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12487
12488 /* Shift amount for subword relative to aligned word. */
12489 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12490 shift = gen_reg_rtx (SImode);
12491 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12492 GEN_INT (shift_mask)));
12493 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12494
12495 /* Shift and mask old value into position within word. */
12496 oldval = convert_modes (SImode, mode, oldval, 1);
12497 oldval = expand_binop (SImode, and_optab,
12498 oldval, GEN_INT (imask), NULL_RTX,
12499 1, OPTAB_LIB_WIDEN);
12500 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12501
12502 /* Shift and mask new value into position within word. */
12503 newval = convert_modes (SImode, mode, newval, 1);
12504 newval = expand_binop (SImode, and_optab,
12505 newval, GEN_INT (imask), NULL_RTX,
12506 1, OPTAB_LIB_WIDEN);
12507 emit_insn (gen_ashlsi3 (newval, newval, shift));
12508
12509 /* Mask for insertion. */
12510 mask = gen_reg_rtx (SImode);
12511 emit_move_insn (mask, GEN_INT (imask));
12512 emit_insn (gen_ashlsi3 (mask, mask, shift));
12513
12514 /* Address of aligned word containing subword. */
12515 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12516 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12517 mem = change_address (mem, SImode, align);
12518 set_mem_align (mem, 32);
12519 MEM_VOLATILE_P (mem) = 1;
12520
12521 wdst = gen_reg_rtx (SImode);
12522 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12523 oldval, newval, mem));
12524
12525 emit_move_insn (dst, gen_lowpart (mode, wdst));
12526 }
12527
12528 void
rs6000_split_compare_and_swapqhi(rtx dest,rtx mask,rtx oldval,rtx newval,rtx mem,rtx scratch)12529 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12530 rtx oldval, rtx newval, rtx mem,
12531 rtx scratch)
12532 {
12533 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12534
12535 emit_insn (gen_memory_barrier ());
12536 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12537 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12538 emit_label (XEXP (label1, 0));
12539
12540 emit_load_locked (SImode, scratch, mem);
12541
12542 /* Mask subword within loaded value for comparison with oldval.
12543 Use UNSPEC_AND to avoid clobber.*/
12544 emit_insn (gen_rtx_SET (SImode, dest,
12545 gen_rtx_UNSPEC (SImode,
12546 gen_rtvec (2, scratch, mask),
12547 UNSPEC_AND)));
12548
12549 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12550 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12551
12552 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12553 emit_unlikely_jump (x, label2);
12554
12555 /* Clear subword within loaded value for insertion of new value. */
12556 emit_insn (gen_rtx_SET (SImode, scratch,
12557 gen_rtx_AND (SImode,
12558 gen_rtx_NOT (SImode, mask), scratch)));
12559 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12560 emit_store_conditional (SImode, cond, mem, scratch);
12561
12562 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12563 emit_unlikely_jump (x, label1);
12564
12565 emit_insn (gen_isync ());
12566 emit_label (XEXP (label2, 0));
12567 }
12568
12569
12570 /* Emit instructions to move SRC to DST. Called by splitters for
12571 multi-register moves. It will emit at most one instruction for
12572 each register that is accessed; that is, it won't emit li/lis pairs
12573 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12574 register. */
12575
12576 void
rs6000_split_multireg_move(rtx dst,rtx src)12577 rs6000_split_multireg_move (rtx dst, rtx src)
12578 {
12579 /* The register number of the first register being moved. */
12580 int reg;
12581 /* The mode that is to be moved. */
12582 enum machine_mode mode;
12583 /* The mode that the move is being done in, and its size. */
12584 enum machine_mode reg_mode;
12585 int reg_mode_size;
12586 /* The number of registers that will be moved. */
12587 int nregs;
12588
12589 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12590 mode = GET_MODE (dst);
12591 nregs = hard_regno_nregs[reg][mode];
12592 if (FP_REGNO_P (reg))
12593 reg_mode = DFmode;
12594 else if (ALTIVEC_REGNO_P (reg))
12595 reg_mode = V16QImode;
12596 else if (TARGET_E500_DOUBLE && mode == TFmode)
12597 reg_mode = DFmode;
12598 else
12599 reg_mode = word_mode;
12600 reg_mode_size = GET_MODE_SIZE (reg_mode);
12601
12602 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12603
12604 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12605 {
12606 /* Move register range backwards, if we might have destructive
12607 overlap. */
12608 int i;
12609 for (i = nregs - 1; i >= 0; i--)
12610 emit_insn (gen_rtx_SET (VOIDmode,
12611 simplify_gen_subreg (reg_mode, dst, mode,
12612 i * reg_mode_size),
12613 simplify_gen_subreg (reg_mode, src, mode,
12614 i * reg_mode_size)));
12615 }
12616 else
12617 {
12618 int i;
12619 int j = -1;
12620 bool used_update = false;
12621
12622 if (MEM_P (src) && INT_REGNO_P (reg))
12623 {
12624 rtx breg;
12625
12626 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12627 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12628 {
12629 rtx delta_rtx;
12630 breg = XEXP (XEXP (src, 0), 0);
12631 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12632 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12633 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12634 emit_insn (TARGET_32BIT
12635 ? gen_addsi3 (breg, breg, delta_rtx)
12636 : gen_adddi3 (breg, breg, delta_rtx));
12637 src = replace_equiv_address (src, breg);
12638 }
12639 else if (! rs6000_offsettable_memref_p (src))
12640 {
12641 rtx basereg;
12642 basereg = gen_rtx_REG (Pmode, reg);
12643 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12644 src = replace_equiv_address (src, basereg);
12645 }
12646
12647 breg = XEXP (src, 0);
12648 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12649 breg = XEXP (breg, 0);
12650
12651 /* If the base register we are using to address memory is
12652 also a destination reg, then change that register last. */
12653 if (REG_P (breg)
12654 && REGNO (breg) >= REGNO (dst)
12655 && REGNO (breg) < REGNO (dst) + nregs)
12656 j = REGNO (breg) - REGNO (dst);
12657 }
12658
12659 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12660 {
12661 rtx breg;
12662
12663 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12664 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12665 {
12666 rtx delta_rtx;
12667 breg = XEXP (XEXP (dst, 0), 0);
12668 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12669 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12670 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12671
12672 /* We have to update the breg before doing the store.
12673 Use store with update, if available. */
12674
12675 if (TARGET_UPDATE)
12676 {
12677 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12678 emit_insn (TARGET_32BIT
12679 ? (TARGET_POWERPC64
12680 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12681 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12682 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12683 used_update = true;
12684 }
12685 else
12686 emit_insn (TARGET_32BIT
12687 ? gen_addsi3 (breg, breg, delta_rtx)
12688 : gen_adddi3 (breg, breg, delta_rtx));
12689 dst = replace_equiv_address (dst, breg);
12690 }
12691 else
12692 gcc_assert (rs6000_offsettable_memref_p (dst));
12693 }
12694
12695 for (i = 0; i < nregs; i++)
12696 {
12697 /* Calculate index to next subword. */
12698 ++j;
12699 if (j == nregs)
12700 j = 0;
12701
12702 /* If compiler already emitted move of first word by
12703 store with update, no need to do anything. */
12704 if (j == 0 && used_update)
12705 continue;
12706
12707 emit_insn (gen_rtx_SET (VOIDmode,
12708 simplify_gen_subreg (reg_mode, dst, mode,
12709 j * reg_mode_size),
12710 simplify_gen_subreg (reg_mode, src, mode,
12711 j * reg_mode_size)));
12712 }
12713 }
12714 }
12715
12716
12717 /* This page contains routines that are used to determine what the
12718 function prologue and epilogue code will do and write them out. */
12719
12720 /* Return the first fixed-point register that is required to be
12721 saved. 32 if none. */
12722
12723 int
first_reg_to_save(void)12724 first_reg_to_save (void)
12725 {
12726 int first_reg;
12727
12728 /* Find lowest numbered live register. */
12729 for (first_reg = 13; first_reg <= 31; first_reg++)
12730 if (regs_ever_live[first_reg]
12731 && (! call_used_regs[first_reg]
12732 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12733 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12734 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12735 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12736 break;
12737
12738 #if TARGET_MACHO
12739 if (flag_pic
12740 && current_function_uses_pic_offset_table
12741 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12742 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12743 #endif
12744
12745 return first_reg;
12746 }
12747
12748 /* Similar, for FP regs. */
12749
12750 int
first_fp_reg_to_save(void)12751 first_fp_reg_to_save (void)
12752 {
12753 int first_reg;
12754
12755 /* Find lowest numbered live register. */
12756 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12757 if (regs_ever_live[first_reg])
12758 break;
12759
12760 return first_reg;
12761 }
12762
12763 /* Similar, for AltiVec regs. */
12764
12765 static int
first_altivec_reg_to_save(void)12766 first_altivec_reg_to_save (void)
12767 {
12768 int i;
12769
12770 /* Stack frame remains as is unless we are in AltiVec ABI. */
12771 if (! TARGET_ALTIVEC_ABI)
12772 return LAST_ALTIVEC_REGNO + 1;
12773
12774 /* On Darwin, the unwind routines are compiled without
12775 TARGET_ALTIVEC, and use save_world to save/restore the
12776 altivec registers when necessary. */
12777 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
12778 && ! TARGET_ALTIVEC)
12779 return FIRST_ALTIVEC_REGNO + 20;
12780
12781 /* Find lowest numbered live register. */
12782 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12783 if (regs_ever_live[i])
12784 break;
12785
12786 return i;
12787 }
12788
12789 /* Return a 32-bit mask of the AltiVec registers we need to set in
12790 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12791 the 32-bit word is 0. */
12792
12793 static unsigned int
compute_vrsave_mask(void)12794 compute_vrsave_mask (void)
12795 {
12796 unsigned int i, mask = 0;
12797
12798 /* On Darwin, the unwind routines are compiled without
12799 TARGET_ALTIVEC, and use save_world to save/restore the
12800 call-saved altivec registers when necessary. */
12801 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
12802 && ! TARGET_ALTIVEC)
12803 mask |= 0xFFF;
12804
12805 /* First, find out if we use _any_ altivec registers. */
12806 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12807 if (regs_ever_live[i])
12808 mask |= ALTIVEC_REG_BIT (i);
12809
12810 if (mask == 0)
12811 return mask;
12812
12813 /* Next, remove the argument registers from the set. These must
12814 be in the VRSAVE mask set by the caller, so we don't need to add
12815 them in again. More importantly, the mask we compute here is
12816 used to generate CLOBBERs in the set_vrsave insn, and we do not
12817 wish the argument registers to die. */
12818 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12819 mask &= ~ALTIVEC_REG_BIT (i);
12820
12821 /* Similarly, remove the return value from the set. */
12822 {
12823 bool yes = false;
12824 diddle_return_value (is_altivec_return_reg, &yes);
12825 if (yes)
12826 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12827 }
12828
12829 return mask;
12830 }
12831
12832 /* For a very restricted set of circumstances, we can cut down the
12833 size of prologues/epilogues by calling our own save/restore-the-world
12834 routines. */
12835
12836 static void
compute_save_world_info(rs6000_stack_t * info_ptr)12837 compute_save_world_info (rs6000_stack_t *info_ptr)
12838 {
12839 info_ptr->world_save_p = 1;
12840 info_ptr->world_save_p
12841 = (WORLD_SAVE_P (info_ptr)
12842 && DEFAULT_ABI == ABI_DARWIN
12843 && ! (current_function_calls_setjmp && flag_exceptions)
12844 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12845 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12846 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12847 && info_ptr->cr_save_p);
12848
12849 /* This will not work in conjunction with sibcalls. Make sure there
12850 are none. (This check is expensive, but seldom executed.) */
12851 if (WORLD_SAVE_P (info_ptr))
12852 {
12853 rtx insn;
12854 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12855 if ( GET_CODE (insn) == CALL_INSN
12856 && SIBLING_CALL_P (insn))
12857 {
12858 info_ptr->world_save_p = 0;
12859 break;
12860 }
12861 }
12862
12863 if (WORLD_SAVE_P (info_ptr))
12864 {
12865 /* Even if we're not touching VRsave, make sure there's room on the
12866 stack for it, if it looks like we're calling SAVE_WORLD, which
12867 will attempt to save it. */
12868 info_ptr->vrsave_size = 4;
12869
12870 /* "Save" the VRsave register too if we're saving the world. */
12871 if (info_ptr->vrsave_mask == 0)
12872 info_ptr->vrsave_mask = compute_vrsave_mask ();
12873
12874 /* Because the Darwin register save/restore routines only handle
12875 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12876 check. */
12877 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12878 && (info_ptr->first_altivec_reg_save
12879 >= FIRST_SAVED_ALTIVEC_REGNO));
12880 }
12881 return;
12882 }
12883
12884
12885 static void
is_altivec_return_reg(rtx reg,void * xyes)12886 is_altivec_return_reg (rtx reg, void *xyes)
12887 {
12888 bool *yes = (bool *) xyes;
12889 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12890 *yes = true;
12891 }
12892
12893
12894 /* Calculate the stack information for the current function. This is
12895 complicated by having two separate calling sequences, the AIX calling
12896 sequence and the V.4 calling sequence.
12897
12898 AIX (and Darwin/Mac OS X) stack frames look like:
12899 32-bit 64-bit
12900 SP----> +---------------------------------------+
12901 | back chain to caller | 0 0
12902 +---------------------------------------+
12903 | saved CR | 4 8 (8-11)
12904 +---------------------------------------+
12905 | saved LR | 8 16
12906 +---------------------------------------+
12907 | reserved for compilers | 12 24
12908 +---------------------------------------+
12909 | reserved for binders | 16 32
12910 +---------------------------------------+
12911 | saved TOC pointer | 20 40
12912 +---------------------------------------+
12913 | Parameter save area (P) | 24 48
12914 +---------------------------------------+
12915 | Alloca space (A) | 24+P etc.
12916 +---------------------------------------+
12917 | Local variable space (L) | 24+P+A
12918 +---------------------------------------+
12919 | Float/int conversion temporary (X) | 24+P+A+L
12920 +---------------------------------------+
12921 | Save area for AltiVec registers (W) | 24+P+A+L+X
12922 +---------------------------------------+
12923 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12924 +---------------------------------------+
12925 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12926 +---------------------------------------+
12927 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12928 +---------------------------------------+
12929 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12930 +---------------------------------------+
12931 old SP->| back chain to caller's caller |
12932 +---------------------------------------+
12933
12934 The required alignment for AIX configurations is two words (i.e., 8
12935 or 16 bytes).
12936
12937
12938 V.4 stack frames look like:
12939
12940 SP----> +---------------------------------------+
12941 | back chain to caller | 0
12942 +---------------------------------------+
12943 | caller's saved LR | 4
12944 +---------------------------------------+
12945 | Parameter save area (P) | 8
12946 +---------------------------------------+
12947 | Alloca space (A) | 8+P
12948 +---------------------------------------+
12949 | Varargs save area (V) | 8+P+A
12950 +---------------------------------------+
12951 | Local variable space (L) | 8+P+A+V
12952 +---------------------------------------+
12953 | Float/int conversion temporary (X) | 8+P+A+V+L
12954 +---------------------------------------+
12955 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12956 +---------------------------------------+
12957 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12958 +---------------------------------------+
12959 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12960 +---------------------------------------+
12961 | SPE: area for 64-bit GP registers |
12962 +---------------------------------------+
12963 | SPE alignment padding |
12964 +---------------------------------------+
12965 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12966 +---------------------------------------+
12967 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12968 +---------------------------------------+
12969 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12970 +---------------------------------------+
12971 old SP->| back chain to caller's caller |
12972 +---------------------------------------+
12973
12974 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12975 given. (But note below and in sysv4.h that we require only 8 and
12976 may round up the size of our stack frame anyways. The historical
12977 reason is early versions of powerpc-linux which didn't properly
12978 align the stack at program startup. A happy side-effect is that
12979 -mno-eabi libraries can be used with -meabi programs.)
12980
12981 The EABI configuration defaults to the V.4 layout. However,
12982 the stack alignment requirements may differ. If -mno-eabi is not
12983 given, the required stack alignment is 8 bytes; if -mno-eabi is
12984 given, the required alignment is 16 bytes. (But see V.4 comment
12985 above.) */
12986
12987 #ifndef ABI_STACK_BOUNDARY
12988 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12989 #endif
12990
12991 static rs6000_stack_t *
rs6000_stack_info(void)12992 rs6000_stack_info (void)
12993 {
12994 static rs6000_stack_t info;
12995 rs6000_stack_t *info_ptr = &info;
12996 int reg_size = TARGET_32BIT ? 4 : 8;
12997 int ehrd_size;
12998 int save_align;
12999 HOST_WIDE_INT non_fixed_size;
13000
13001 memset (&info, 0, sizeof (info));
13002
13003 if (TARGET_SPE)
13004 {
13005 /* Cache value so we don't rescan instruction chain over and over. */
13006 if (cfun->machine->insn_chain_scanned_p == 0)
13007 cfun->machine->insn_chain_scanned_p
13008 = spe_func_has_64bit_regs_p () + 1;
13009 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13010 }
13011
13012 /* Select which calling sequence. */
13013 info_ptr->abi = DEFAULT_ABI;
13014
13015 /* Calculate which registers need to be saved & save area size. */
13016 info_ptr->first_gp_reg_save = first_reg_to_save ();
13017 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13018 even if it currently looks like we won't. */
13019 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13020 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13021 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13022 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13023 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13024 else
13025 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13026
13027 /* For the SPE, we have an additional upper 32-bits on each GPR.
13028 Ideally we should save the entire 64-bits only when the upper
13029 half is used in SIMD instructions. Since we only record
13030 registers live (not the size they are used in), this proves
13031 difficult because we'd have to traverse the instruction chain at
13032 the right time, taking reload into account. This is a real pain,
13033 so we opt to save the GPRs in 64-bits always if but one register
13034 gets used in 64-bits. Otherwise, all the registers in the frame
13035 get saved in 32-bits.
13036
13037 So... since when we save all GPRs (except the SP) in 64-bits, the
13038 traditional GP save area will be empty. */
13039 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13040 info_ptr->gp_size = 0;
13041
13042 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13043 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13044
13045 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13046 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13047 - info_ptr->first_altivec_reg_save);
13048
13049 /* Does this function call anything? */
13050 info_ptr->calls_p = (! current_function_is_leaf
13051 || cfun->machine->ra_needs_full_frame);
13052
13053 /* Determine if we need to save the link register. */
13054 if ((DEFAULT_ABI == ABI_AIX
13055 && current_function_profile
13056 && !TARGET_PROFILE_KERNEL)
13057 #ifdef TARGET_RELOCATABLE
13058 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13059 #endif
13060 || (info_ptr->first_fp_reg_save != 64
13061 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13062 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13063 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13064 || info_ptr->calls_p
13065 || rs6000_ra_ever_killed ())
13066 {
13067 info_ptr->lr_save_p = 1;
13068 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
13069 }
13070
13071 /* Determine if we need to save the condition code registers. */
13072 if (regs_ever_live[CR2_REGNO]
13073 || regs_ever_live[CR3_REGNO]
13074 || regs_ever_live[CR4_REGNO])
13075 {
13076 info_ptr->cr_save_p = 1;
13077 if (DEFAULT_ABI == ABI_V4)
13078 info_ptr->cr_size = reg_size;
13079 }
13080
13081 /* If the current function calls __builtin_eh_return, then we need
13082 to allocate stack space for registers that will hold data for
13083 the exception handler. */
13084 if (current_function_calls_eh_return)
13085 {
13086 unsigned int i;
13087 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13088 continue;
13089
13090 /* SPE saves EH registers in 64-bits. */
13091 ehrd_size = i * (TARGET_SPE_ABI
13092 && info_ptr->spe_64bit_regs_used != 0
13093 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13094 }
13095 else
13096 ehrd_size = 0;
13097
13098 /* Determine various sizes. */
13099 info_ptr->reg_size = reg_size;
13100 info_ptr->fixed_size = RS6000_SAVE_AREA;
13101 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13102 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13103 TARGET_ALTIVEC ? 16 : 8);
13104 if (FRAME_GROWS_DOWNWARD)
13105 info_ptr->vars_size
13106 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13107 + info_ptr->parm_size,
13108 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13109 - (info_ptr->fixed_size + info_ptr->vars_size
13110 + info_ptr->parm_size);
13111
13112 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13113 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13114 else
13115 info_ptr->spe_gp_size = 0;
13116
13117 if (TARGET_ALTIVEC_ABI)
13118 info_ptr->vrsave_mask = compute_vrsave_mask ();
13119 else
13120 info_ptr->vrsave_mask = 0;
13121
13122 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13123 info_ptr->vrsave_size = 4;
13124 else
13125 info_ptr->vrsave_size = 0;
13126
13127 compute_save_world_info (info_ptr);
13128
13129 /* Calculate the offsets. */
13130 switch (DEFAULT_ABI)
13131 {
13132 case ABI_NONE:
13133 default:
13134 gcc_unreachable ();
13135
13136 case ABI_AIX:
13137 case ABI_DARWIN:
13138 info_ptr->fp_save_offset = - info_ptr->fp_size;
13139 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13140
13141 if (TARGET_ALTIVEC_ABI)
13142 {
13143 info_ptr->vrsave_save_offset
13144 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13145
13146 /* Align stack so vector save area is on a quadword boundary.
13147 The padding goes above the vectors. */
13148 if (info_ptr->altivec_size != 0)
13149 info_ptr->altivec_padding_size
13150 = info_ptr->vrsave_save_offset & 0xF;
13151 else
13152 info_ptr->altivec_padding_size = 0;
13153
13154 info_ptr->altivec_save_offset
13155 = info_ptr->vrsave_save_offset
13156 - info_ptr->altivec_padding_size
13157 - info_ptr->altivec_size;
13158 gcc_assert (info_ptr->altivec_size == 0
13159 || info_ptr->altivec_save_offset % 16 == 0);
13160
13161 /* Adjust for AltiVec case. */
13162 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13163 }
13164 else
13165 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13166 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13167 info_ptr->lr_save_offset = 2*reg_size;
13168 break;
13169
13170 case ABI_V4:
13171 info_ptr->fp_save_offset = - info_ptr->fp_size;
13172 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13173 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13174
13175 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13176 {
13177 /* Align stack so SPE GPR save area is aligned on a
13178 double-word boundary. */
13179 if (info_ptr->spe_gp_size != 0)
13180 info_ptr->spe_padding_size
13181 = 8 - (-info_ptr->cr_save_offset % 8);
13182 else
13183 info_ptr->spe_padding_size = 0;
13184
13185 info_ptr->spe_gp_save_offset
13186 = info_ptr->cr_save_offset
13187 - info_ptr->spe_padding_size
13188 - info_ptr->spe_gp_size;
13189
13190 /* Adjust for SPE case. */
13191 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13192 }
13193 else if (TARGET_ALTIVEC_ABI)
13194 {
13195 info_ptr->vrsave_save_offset
13196 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13197
13198 /* Align stack so vector save area is on a quadword boundary. */
13199 if (info_ptr->altivec_size != 0)
13200 info_ptr->altivec_padding_size
13201 = 16 - (-info_ptr->vrsave_save_offset % 16);
13202 else
13203 info_ptr->altivec_padding_size = 0;
13204
13205 info_ptr->altivec_save_offset
13206 = info_ptr->vrsave_save_offset
13207 - info_ptr->altivec_padding_size
13208 - info_ptr->altivec_size;
13209
13210 /* Adjust for AltiVec case. */
13211 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13212 }
13213 else
13214 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13215 info_ptr->ehrd_offset -= ehrd_size;
13216 info_ptr->lr_save_offset = reg_size;
13217 break;
13218 }
13219
13220 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13221 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13222 + info_ptr->gp_size
13223 + info_ptr->altivec_size
13224 + info_ptr->altivec_padding_size
13225 + info_ptr->spe_gp_size
13226 + info_ptr->spe_padding_size
13227 + ehrd_size
13228 + info_ptr->cr_size
13229 + info_ptr->vrsave_size,
13230 save_align);
13231
13232 non_fixed_size = (info_ptr->vars_size
13233 + info_ptr->parm_size
13234 + info_ptr->save_size);
13235
13236 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13237 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13238
13239 /* Determine if we need to allocate any stack frame:
13240
13241 For AIX we need to push the stack if a frame pointer is needed
13242 (because the stack might be dynamically adjusted), if we are
13243 debugging, if we make calls, or if the sum of fp_save, gp_save,
13244 and local variables are more than the space needed to save all
13245 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13246 + 18*8 = 288 (GPR13 reserved).
13247
13248 For V.4 we don't have the stack cushion that AIX uses, but assume
13249 that the debugger can handle stackless frames. */
13250
13251 if (info_ptr->calls_p)
13252 info_ptr->push_p = 1;
13253
13254 else if (DEFAULT_ABI == ABI_V4)
13255 info_ptr->push_p = non_fixed_size != 0;
13256
13257 else if (frame_pointer_needed)
13258 info_ptr->push_p = 1;
13259
13260 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13261 info_ptr->push_p = 1;
13262
13263 else
13264 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13265
13266 /* Zero offsets if we're not saving those registers. */
13267 if (info_ptr->fp_size == 0)
13268 info_ptr->fp_save_offset = 0;
13269
13270 if (info_ptr->gp_size == 0)
13271 info_ptr->gp_save_offset = 0;
13272
13273 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13274 info_ptr->altivec_save_offset = 0;
13275
13276 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13277 info_ptr->vrsave_save_offset = 0;
13278
13279 if (! TARGET_SPE_ABI
13280 || info_ptr->spe_64bit_regs_used == 0
13281 || info_ptr->spe_gp_size == 0)
13282 info_ptr->spe_gp_save_offset = 0;
13283
13284 if (! info_ptr->lr_save_p)
13285 info_ptr->lr_save_offset = 0;
13286
13287 if (! info_ptr->cr_save_p)
13288 info_ptr->cr_save_offset = 0;
13289
13290 return info_ptr;
13291 }
13292
13293 /* Return true if the current function uses any GPRs in 64-bit SIMD
13294 mode. */
13295
13296 static bool
spe_func_has_64bit_regs_p(void)13297 spe_func_has_64bit_regs_p (void)
13298 {
13299 rtx insns, insn;
13300
13301 /* Functions that save and restore all the call-saved registers will
13302 need to save/restore the registers in 64-bits. */
13303 if (current_function_calls_eh_return
13304 || current_function_calls_setjmp
13305 || current_function_has_nonlocal_goto)
13306 return true;
13307
13308 insns = get_insns ();
13309
13310 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13311 {
13312 if (INSN_P (insn))
13313 {
13314 rtx i;
13315
13316 /* FIXME: This should be implemented with attributes...
13317
13318 (set_attr "spe64" "true")....then,
13319 if (get_spe64(insn)) return true;
13320
13321 It's the only reliable way to do the stuff below. */
13322
13323 i = PATTERN (insn);
13324 if (GET_CODE (i) == SET)
13325 {
13326 enum machine_mode mode = GET_MODE (SET_SRC (i));
13327
13328 if (SPE_VECTOR_MODE (mode))
13329 return true;
13330 if (TARGET_E500_DOUBLE && mode == DFmode)
13331 return true;
13332 }
13333 }
13334 }
13335
13336 return false;
13337 }
13338
13339 static void
debug_stack_info(rs6000_stack_t * info)13340 debug_stack_info (rs6000_stack_t *info)
13341 {
13342 const char *abi_string;
13343
13344 if (! info)
13345 info = rs6000_stack_info ();
13346
13347 fprintf (stderr, "\nStack information for function %s:\n",
13348 ((current_function_decl && DECL_NAME (current_function_decl))
13349 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13350 : "<unknown>"));
13351
13352 switch (info->abi)
13353 {
13354 default: abi_string = "Unknown"; break;
13355 case ABI_NONE: abi_string = "NONE"; break;
13356 case ABI_AIX: abi_string = "AIX"; break;
13357 case ABI_DARWIN: abi_string = "Darwin"; break;
13358 case ABI_V4: abi_string = "V.4"; break;
13359 }
13360
13361 fprintf (stderr, "\tABI = %5s\n", abi_string);
13362
13363 if (TARGET_ALTIVEC_ABI)
13364 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13365
13366 if (TARGET_SPE_ABI)
13367 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13368
13369 if (info->first_gp_reg_save != 32)
13370 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13371
13372 if (info->first_fp_reg_save != 64)
13373 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13374
13375 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13376 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13377 info->first_altivec_reg_save);
13378
13379 if (info->lr_save_p)
13380 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13381
13382 if (info->cr_save_p)
13383 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13384
13385 if (info->vrsave_mask)
13386 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13387
13388 if (info->push_p)
13389 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13390
13391 if (info->calls_p)
13392 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13393
13394 if (info->gp_save_offset)
13395 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13396
13397 if (info->fp_save_offset)
13398 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13399
13400 if (info->altivec_save_offset)
13401 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13402 info->altivec_save_offset);
13403
13404 if (info->spe_gp_save_offset)
13405 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13406 info->spe_gp_save_offset);
13407
13408 if (info->vrsave_save_offset)
13409 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13410 info->vrsave_save_offset);
13411
13412 if (info->lr_save_offset)
13413 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13414
13415 if (info->cr_save_offset)
13416 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13417
13418 if (info->varargs_save_offset)
13419 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13420
13421 if (info->total_size)
13422 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13423 info->total_size);
13424
13425 if (info->vars_size)
13426 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13427 info->vars_size);
13428
13429 if (info->parm_size)
13430 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13431
13432 if (info->fixed_size)
13433 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13434
13435 if (info->gp_size)
13436 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13437
13438 if (info->spe_gp_size)
13439 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13440
13441 if (info->fp_size)
13442 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13443
13444 if (info->altivec_size)
13445 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13446
13447 if (info->vrsave_size)
13448 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13449
13450 if (info->altivec_padding_size)
13451 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13452 info->altivec_padding_size);
13453
13454 if (info->spe_padding_size)
13455 fprintf (stderr, "\tspe_padding_size = %5d\n",
13456 info->spe_padding_size);
13457
13458 if (info->cr_size)
13459 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13460
13461 if (info->save_size)
13462 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13463
13464 if (info->reg_size != 4)
13465 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13466
13467 fprintf (stderr, "\n");
13468 }
13469
13470 rtx
rs6000_return_addr(int count,rtx frame)13471 rs6000_return_addr (int count, rtx frame)
13472 {
13473 /* Currently we don't optimize very well between prolog and body
13474 code and for PIC code the code can be actually quite bad, so
13475 don't try to be too clever here. */
13476 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13477 {
13478 rtx x;
13479 cfun->machine->ra_needs_full_frame = 1;
13480
13481 if (count == 0)
13482 {
13483 gcc_assert (frame == frame_pointer_rtx);
13484 x = arg_pointer_rtx;
13485 }
13486 else
13487 {
13488 x = memory_address (Pmode, frame);
13489 x = copy_to_reg (gen_rtx_MEM (Pmode, x));
13490 }
13491
13492 x = plus_constant (x, RETURN_ADDRESS_OFFSET);
13493 return gen_rtx_MEM (Pmode, memory_address (Pmode, x));
13494 }
13495
13496 cfun->machine->ra_need_lr = 1;
13497 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13498 }
13499
13500 /* Say whether a function is a candidate for sibcall handling or not.
13501 We do not allow indirect calls to be optimized into sibling calls.
13502 Also, we can't do it if there are any vector parameters; there's
13503 nowhere to put the VRsave code so it works; note that functions with
13504 vector parameters are required to have a prototype, so the argument
13505 type info must be available here. (The tail recursion case can work
13506 with vector parameters, but there's no way to distinguish here.) */
13507 static bool
rs6000_function_ok_for_sibcall(tree decl,tree exp ATTRIBUTE_UNUSED)13508 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13509 {
13510 tree type;
13511 if (decl)
13512 {
13513 if (TARGET_ALTIVEC_VRSAVE)
13514 {
13515 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13516 type; type = TREE_CHAIN (type))
13517 {
13518 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13519 return false;
13520 }
13521 }
13522 if (DEFAULT_ABI == ABI_DARWIN
13523 || ((*targetm.binds_local_p) (decl)
13524 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
13525 {
13526 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13527
13528 if (!lookup_attribute ("longcall", attr_list)
13529 || lookup_attribute ("shortcall", attr_list))
13530 return true;
13531 }
13532 }
13533 return false;
13534 }
13535
13536 /* NULL if INSN insn is valid within a low-overhead loop.
13537 Otherwise return why doloop cannot be applied.
13538 PowerPC uses the COUNT register for branch on table instructions. */
13539
13540 static const char *
rs6000_invalid_within_doloop(rtx insn)13541 rs6000_invalid_within_doloop (rtx insn)
13542 {
13543 if (CALL_P (insn))
13544 return "Function call in the loop.";
13545
13546 if (JUMP_P (insn)
13547 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13548 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13549 return "Computed branch in the loop.";
13550
13551 return NULL;
13552 }
13553
13554 static int
rs6000_ra_ever_killed(void)13555 rs6000_ra_ever_killed (void)
13556 {
13557 rtx top;
13558 rtx reg;
13559 rtx insn;
13560
13561 if (current_function_is_thunk)
13562 return 0;
13563
13564 /* regs_ever_live has LR marked as used if any sibcalls are present,
13565 but this should not force saving and restoring in the
13566 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13567 clobbers LR, so that is inappropriate. */
13568
13569 /* Also, the prologue can generate a store into LR that
13570 doesn't really count, like this:
13571
13572 move LR->R0
13573 bcl to set PIC register
13574 move LR->R31
13575 move R0->LR
13576
13577 When we're called from the epilogue, we need to avoid counting
13578 this as a store. */
13579
13580 push_topmost_sequence ();
13581 top = get_insns ();
13582 pop_topmost_sequence ();
13583 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13584
13585 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13586 {
13587 if (INSN_P (insn))
13588 {
13589 if (CALL_P (insn))
13590 {
13591 if (!SIBLING_CALL_P (insn))
13592 return 1;
13593 }
13594 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13595 return 1;
13596 else if (set_of (reg, insn) != NULL_RTX
13597 && !prologue_epilogue_contains (insn))
13598 return 1;
13599 }
13600 }
13601 return 0;
13602 }
13603
13604 /* Add a REG_MAYBE_DEAD note to the insn. */
13605 static void
rs6000_maybe_dead(rtx insn)13606 rs6000_maybe_dead (rtx insn)
13607 {
13608 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13609 const0_rtx,
13610 REG_NOTES (insn));
13611 }
13612
13613 /* Emit instructions needed to load the TOC register.
13614 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13615 a constant pool; or for SVR4 -fpic. */
13616
13617 void
rs6000_emit_load_toc_table(int fromprolog)13618 rs6000_emit_load_toc_table (int fromprolog)
13619 {
13620 rtx dest, insn;
13621 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13622
13623 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13624 {
13625 char buf[30];
13626 rtx lab, tmp1, tmp2, got, tempLR;
13627
13628 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13629 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13630 if (flag_pic == 2)
13631 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13632 else
13633 got = rs6000_got_sym ();
13634 tmp1 = tmp2 = dest;
13635 if (!fromprolog)
13636 {
13637 tmp1 = gen_reg_rtx (Pmode);
13638 tmp2 = gen_reg_rtx (Pmode);
13639 }
13640 tempLR = (fromprolog
13641 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13642 : gen_reg_rtx (Pmode));
13643 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13644 if (fromprolog)
13645 rs6000_maybe_dead (insn);
13646 insn = emit_move_insn (tmp1, tempLR);
13647 if (fromprolog)
13648 rs6000_maybe_dead (insn);
13649 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13650 if (fromprolog)
13651 rs6000_maybe_dead (insn);
13652 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13653 if (fromprolog)
13654 rs6000_maybe_dead (insn);
13655 }
13656 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13657 {
13658 rtx tempLR = (fromprolog
13659 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13660 : gen_reg_rtx (Pmode));
13661
13662 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13663 if (fromprolog)
13664 rs6000_maybe_dead (insn);
13665 insn = emit_move_insn (dest, tempLR);
13666 if (fromprolog)
13667 rs6000_maybe_dead (insn);
13668 }
13669 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13670 {
13671 char buf[30];
13672 rtx tempLR = (fromprolog
13673 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13674 : gen_reg_rtx (Pmode));
13675 rtx temp0 = (fromprolog
13676 ? gen_rtx_REG (Pmode, 0)
13677 : gen_reg_rtx (Pmode));
13678
13679 if (fromprolog)
13680 {
13681 rtx symF, symL;
13682
13683 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13684 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13685
13686 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13687 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13688
13689 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13690 symF)));
13691 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13692 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13693 symL,
13694 symF)));
13695 }
13696 else
13697 {
13698 rtx tocsym;
13699
13700 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13701 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13702 emit_move_insn (dest, tempLR);
13703 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13704 }
13705 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13706 if (fromprolog)
13707 rs6000_maybe_dead (insn);
13708 }
13709 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13710 {
13711 /* This is for AIX code running in non-PIC ELF32. */
13712 char buf[30];
13713 rtx realsym;
13714 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13715 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13716
13717 insn = emit_insn (gen_elf_high (dest, realsym));
13718 if (fromprolog)
13719 rs6000_maybe_dead (insn);
13720 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13721 if (fromprolog)
13722 rs6000_maybe_dead (insn);
13723 }
13724 else
13725 {
13726 gcc_assert (DEFAULT_ABI == ABI_AIX);
13727
13728 if (TARGET_32BIT)
13729 insn = emit_insn (gen_load_toc_aix_si (dest));
13730 else
13731 insn = emit_insn (gen_load_toc_aix_di (dest));
13732 if (fromprolog)
13733 rs6000_maybe_dead (insn);
13734 }
13735 }
13736
13737 /* Emit instructions to restore the link register after determining where
13738 its value has been stored. */
13739
13740 void
rs6000_emit_eh_reg_restore(rtx source,rtx scratch)13741 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13742 {
13743 rs6000_stack_t *info = rs6000_stack_info ();
13744 rtx operands[2];
13745
13746 operands[0] = source;
13747 operands[1] = scratch;
13748
13749 if (info->lr_save_p)
13750 {
13751 rtx frame_rtx = stack_pointer_rtx;
13752 HOST_WIDE_INT sp_offset = 0;
13753 rtx tmp;
13754
13755 if (frame_pointer_needed
13756 || current_function_calls_alloca
13757 || info->total_size > 32767)
13758 {
13759 tmp = gen_frame_mem (Pmode, frame_rtx);
13760 emit_move_insn (operands[1], tmp);
13761 frame_rtx = operands[1];
13762 }
13763 else if (info->push_p)
13764 sp_offset = info->total_size;
13765
13766 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13767 tmp = gen_frame_mem (Pmode, tmp);
13768 emit_move_insn (tmp, operands[0]);
13769 }
13770 else
13771 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13772 }
13773
13774 static GTY(()) int set = -1;
13775
13776 int
get_TOC_alias_set(void)13777 get_TOC_alias_set (void)
13778 {
13779 if (set == -1)
13780 set = new_alias_set ();
13781 return set;
13782 }
13783
13784 /* This returns nonzero if the current function uses the TOC. This is
13785 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13786 is generated by the ABI_V4 load_toc_* patterns. */
13787 #if TARGET_ELF
13788 static int
uses_TOC(void)13789 uses_TOC (void)
13790 {
13791 rtx insn;
13792
13793 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13794 if (INSN_P (insn))
13795 {
13796 rtx pat = PATTERN (insn);
13797 int i;
13798
13799 if (GET_CODE (pat) == PARALLEL)
13800 for (i = 0; i < XVECLEN (pat, 0); i++)
13801 {
13802 rtx sub = XVECEXP (pat, 0, i);
13803 if (GET_CODE (sub) == USE)
13804 {
13805 sub = XEXP (sub, 0);
13806 if (GET_CODE (sub) == UNSPEC
13807 && XINT (sub, 1) == UNSPEC_TOC)
13808 return 1;
13809 }
13810 }
13811 }
13812 return 0;
13813 }
13814 #endif
13815
13816 rtx
create_TOC_reference(rtx symbol)13817 create_TOC_reference (rtx symbol)
13818 {
13819 if (no_new_pseudos)
13820 regs_ever_live[TOC_REGISTER] = 1;
13821 return gen_rtx_PLUS (Pmode,
13822 gen_rtx_REG (Pmode, TOC_REGISTER),
13823 gen_rtx_CONST (Pmode,
13824 gen_rtx_MINUS (Pmode, symbol,
13825 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13826 }
13827
13828 /* If _Unwind_* has been called from within the same module,
13829 toc register is not guaranteed to be saved to 40(1) on function
13830 entry. Save it there in that case. */
13831
13832 void
rs6000_aix_emit_builtin_unwind_init(void)13833 rs6000_aix_emit_builtin_unwind_init (void)
13834 {
13835 rtx mem;
13836 rtx stack_top = gen_reg_rtx (Pmode);
13837 rtx opcode_addr = gen_reg_rtx (Pmode);
13838 rtx opcode = gen_reg_rtx (SImode);
13839 rtx tocompare = gen_reg_rtx (SImode);
13840 rtx no_toc_save_needed = gen_label_rtx ();
13841
13842 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13843 emit_move_insn (stack_top, mem);
13844
13845 mem = gen_frame_mem (Pmode,
13846 gen_rtx_PLUS (Pmode, stack_top,
13847 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13848 emit_move_insn (opcode_addr, mem);
13849 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13850 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13851 : 0xE8410028, SImode));
13852
13853 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13854 SImode, NULL_RTX, NULL_RTX,
13855 no_toc_save_needed);
13856
13857 mem = gen_frame_mem (Pmode,
13858 gen_rtx_PLUS (Pmode, stack_top,
13859 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13860 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13861 emit_label (no_toc_save_needed);
13862 }
13863
13864 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13865 and the change to the stack pointer. */
13866
13867 static void
rs6000_emit_stack_tie(void)13868 rs6000_emit_stack_tie (void)
13869 {
13870 rtx mem = gen_frame_mem (BLKmode,
13871 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13872
13873 emit_insn (gen_stack_tie (mem));
13874 }
13875
13876 /* Emit the correct code for allocating stack space, as insns.
13877 If COPY_R12, make sure a copy of the old frame is left in r12.
13878 The generated code may use hard register 0 as a temporary. */
13879
13880 static void
rs6000_emit_allocate_stack(HOST_WIDE_INT size,int copy_r12)13881 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13882 {
13883 rtx insn;
13884 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13885 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13886 rtx todec = gen_int_mode (-size, Pmode);
13887
13888 if (INTVAL (todec) != -size)
13889 {
13890 warning (0, "stack frame too large");
13891 emit_insn (gen_trap ());
13892 return;
13893 }
13894
13895 if (current_function_limit_stack)
13896 {
13897 if (REG_P (stack_limit_rtx)
13898 && REGNO (stack_limit_rtx) > 1
13899 && REGNO (stack_limit_rtx) <= 31)
13900 {
13901 emit_insn (TARGET_32BIT
13902 ? gen_addsi3 (tmp_reg,
13903 stack_limit_rtx,
13904 GEN_INT (size))
13905 : gen_adddi3 (tmp_reg,
13906 stack_limit_rtx,
13907 GEN_INT (size)));
13908
13909 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13910 const0_rtx));
13911 }
13912 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13913 && TARGET_32BIT
13914 && DEFAULT_ABI == ABI_V4)
13915 {
13916 rtx toload = gen_rtx_CONST (VOIDmode,
13917 gen_rtx_PLUS (Pmode,
13918 stack_limit_rtx,
13919 GEN_INT (size)));
13920
13921 emit_insn (gen_elf_high (tmp_reg, toload));
13922 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13923 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13924 const0_rtx));
13925 }
13926 else
13927 warning (0, "stack limit expression is not supported");
13928 }
13929
13930 if (copy_r12 || ! TARGET_UPDATE)
13931 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13932
13933 if (TARGET_UPDATE)
13934 {
13935 if (size > 32767)
13936 {
13937 /* Need a note here so that try_split doesn't get confused. */
13938 if (get_last_insn () == NULL_RTX)
13939 emit_note (NOTE_INSN_DELETED);
13940 insn = emit_move_insn (tmp_reg, todec);
13941 try_split (PATTERN (insn), insn, 0);
13942 todec = tmp_reg;
13943 }
13944
13945 insn = emit_insn (TARGET_32BIT
13946 ? gen_movsi_update (stack_reg, stack_reg,
13947 todec, stack_reg)
13948 : gen_movdi_di_update (stack_reg, stack_reg,
13949 todec, stack_reg));
13950 }
13951 else
13952 {
13953 insn = emit_insn (TARGET_32BIT
13954 ? gen_addsi3 (stack_reg, stack_reg, todec)
13955 : gen_adddi3 (stack_reg, stack_reg, todec));
13956 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13957 gen_rtx_REG (Pmode, 12));
13958 }
13959
13960 RTX_FRAME_RELATED_P (insn) = 1;
13961 REG_NOTES (insn) =
13962 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13963 gen_rtx_SET (VOIDmode, stack_reg,
13964 gen_rtx_PLUS (Pmode, stack_reg,
13965 GEN_INT (-size))),
13966 REG_NOTES (insn));
13967 }
13968
13969 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13970 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13971 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13972 deduce these equivalences by itself so it wasn't necessary to hold
13973 its hand so much. */
13974
13975 static void
rs6000_frame_related(rtx insn,rtx reg,HOST_WIDE_INT val,rtx reg2,rtx rreg)13976 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13977 rtx reg2, rtx rreg)
13978 {
13979 rtx real, temp;
13980
13981 /* copy_rtx will not make unique copies of registers, so we need to
13982 ensure we don't have unwanted sharing here. */
13983 if (reg == reg2)
13984 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13985
13986 if (reg == rreg)
13987 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13988
13989 real = copy_rtx (PATTERN (insn));
13990
13991 if (reg2 != NULL_RTX)
13992 real = replace_rtx (real, reg2, rreg);
13993
13994 real = replace_rtx (real, reg,
13995 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13996 STACK_POINTER_REGNUM),
13997 GEN_INT (val)));
13998
13999 /* We expect that 'real' is either a SET or a PARALLEL containing
14000 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14001 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14002
14003 if (GET_CODE (real) == SET)
14004 {
14005 rtx set = real;
14006
14007 temp = simplify_rtx (SET_SRC (set));
14008 if (temp)
14009 SET_SRC (set) = temp;
14010 temp = simplify_rtx (SET_DEST (set));
14011 if (temp)
14012 SET_DEST (set) = temp;
14013 if (GET_CODE (SET_DEST (set)) == MEM)
14014 {
14015 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14016 if (temp)
14017 XEXP (SET_DEST (set), 0) = temp;
14018 }
14019 }
14020 else
14021 {
14022 int i;
14023
14024 gcc_assert (GET_CODE (real) == PARALLEL);
14025 for (i = 0; i < XVECLEN (real, 0); i++)
14026 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14027 {
14028 rtx set = XVECEXP (real, 0, i);
14029
14030 temp = simplify_rtx (SET_SRC (set));
14031 if (temp)
14032 SET_SRC (set) = temp;
14033 temp = simplify_rtx (SET_DEST (set));
14034 if (temp)
14035 SET_DEST (set) = temp;
14036 if (GET_CODE (SET_DEST (set)) == MEM)
14037 {
14038 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14039 if (temp)
14040 XEXP (SET_DEST (set), 0) = temp;
14041 }
14042 RTX_FRAME_RELATED_P (set) = 1;
14043 }
14044 }
14045
14046 if (TARGET_SPE)
14047 real = spe_synthesize_frame_save (real);
14048
14049 RTX_FRAME_RELATED_P (insn) = 1;
14050 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14051 real,
14052 REG_NOTES (insn));
14053 }
14054
14055 /* Given an SPE frame note, return a PARALLEL of SETs with the
14056 original note, plus a synthetic register save. */
14057
14058 static rtx
spe_synthesize_frame_save(rtx real)14059 spe_synthesize_frame_save (rtx real)
14060 {
14061 rtx synth, offset, reg, real2;
14062
14063 if (GET_CODE (real) != SET
14064 || GET_MODE (SET_SRC (real)) != V2SImode)
14065 return real;
14066
14067 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14068 frame related note. The parallel contains a set of the register
14069 being saved, and another set to a synthetic register (n+1200).
14070 This is so we can differentiate between 64-bit and 32-bit saves.
14071 Words cannot describe this nastiness. */
14072
14073 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14074 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14075 && GET_CODE (SET_SRC (real)) == REG);
14076
14077 /* Transform:
14078 (set (mem (plus (reg x) (const y)))
14079 (reg z))
14080 into:
14081 (set (mem (plus (reg x) (const y+4)))
14082 (reg z+1200))
14083 */
14084
14085 real2 = copy_rtx (real);
14086 PUT_MODE (SET_DEST (real2), SImode);
14087 reg = SET_SRC (real2);
14088 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14089 synth = copy_rtx (real2);
14090
14091 if (BYTES_BIG_ENDIAN)
14092 {
14093 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14094 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14095 }
14096
14097 reg = SET_SRC (synth);
14098
14099 synth = replace_rtx (synth, reg,
14100 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14101
14102 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14103 synth = replace_rtx (synth, offset,
14104 GEN_INT (INTVAL (offset)
14105 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14106
14107 RTX_FRAME_RELATED_P (synth) = 1;
14108 RTX_FRAME_RELATED_P (real2) = 1;
14109 if (BYTES_BIG_ENDIAN)
14110 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14111 else
14112 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14113
14114 return real;
14115 }
14116
14117 /* Returns an insn that has a vrsave set operation with the
14118 appropriate CLOBBERs. */
14119
14120 static rtx
generate_set_vrsave(rtx reg,rs6000_stack_t * info,int epiloguep)14121 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14122 {
14123 int nclobs, i;
14124 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14125 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14126
14127 clobs[0]
14128 = gen_rtx_SET (VOIDmode,
14129 vrsave,
14130 gen_rtx_UNSPEC_VOLATILE (SImode,
14131 gen_rtvec (2, reg, vrsave),
14132 UNSPECV_SET_VRSAVE));
14133
14134 nclobs = 1;
14135
14136 /* We need to clobber the registers in the mask so the scheduler
14137 does not move sets to VRSAVE before sets of AltiVec registers.
14138
14139 However, if the function receives nonlocal gotos, reload will set
14140 all call saved registers live. We will end up with:
14141
14142 (set (reg 999) (mem))
14143 (parallel [ (set (reg vrsave) (unspec blah))
14144 (clobber (reg 999))])
14145
14146 The clobber will cause the store into reg 999 to be dead, and
14147 flow will attempt to delete an epilogue insn. In this case, we
14148 need an unspec use/set of the register. */
14149
14150 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14151 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14152 {
14153 if (!epiloguep || call_used_regs [i])
14154 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14155 gen_rtx_REG (V4SImode, i));
14156 else
14157 {
14158 rtx reg = gen_rtx_REG (V4SImode, i);
14159
14160 clobs[nclobs++]
14161 = gen_rtx_SET (VOIDmode,
14162 reg,
14163 gen_rtx_UNSPEC (V4SImode,
14164 gen_rtvec (1, reg), 27));
14165 }
14166 }
14167
14168 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14169
14170 for (i = 0; i < nclobs; ++i)
14171 XVECEXP (insn, 0, i) = clobs[i];
14172
14173 return insn;
14174 }
14175
14176 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14177 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14178
14179 static void
emit_frame_save(rtx frame_reg,rtx frame_ptr,enum machine_mode mode,unsigned int regno,int offset,HOST_WIDE_INT total_size)14180 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14181 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14182 {
14183 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14184 rtx replacea, replaceb;
14185
14186 int_rtx = GEN_INT (offset);
14187
14188 /* Some cases that need register indexed addressing. */
14189 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14190 || (TARGET_E500_DOUBLE && mode == DFmode)
14191 || (TARGET_SPE_ABI
14192 && SPE_VECTOR_MODE (mode)
14193 && !SPE_CONST_OFFSET_OK (offset)))
14194 {
14195 /* Whomever calls us must make sure r11 is available in the
14196 flow path of instructions in the prologue. */
14197 offset_rtx = gen_rtx_REG (Pmode, 11);
14198 emit_move_insn (offset_rtx, int_rtx);
14199
14200 replacea = offset_rtx;
14201 replaceb = int_rtx;
14202 }
14203 else
14204 {
14205 offset_rtx = int_rtx;
14206 replacea = NULL_RTX;
14207 replaceb = NULL_RTX;
14208 }
14209
14210 reg = gen_rtx_REG (mode, regno);
14211 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14212 mem = gen_frame_mem (mode, addr);
14213
14214 insn = emit_move_insn (mem, reg);
14215
14216 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14217 }
14218
14219 /* Emit an offset memory reference suitable for a frame store, while
14220 converting to a valid addressing mode. */
14221
14222 static rtx
gen_frame_mem_offset(enum machine_mode mode,rtx reg,int offset)14223 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14224 {
14225 rtx int_rtx, offset_rtx;
14226
14227 int_rtx = GEN_INT (offset);
14228
14229 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14230 || (TARGET_E500_DOUBLE && mode == DFmode))
14231 {
14232 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14233 emit_move_insn (offset_rtx, int_rtx);
14234 }
14235 else
14236 offset_rtx = int_rtx;
14237
14238 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14239 }
14240
14241 /* Look for user-defined global regs. We should not save and restore these,
14242 and cannot use stmw/lmw if there are any in its range. */
14243
14244 static bool
no_global_regs_above(int first_greg)14245 no_global_regs_above (int first_greg)
14246 {
14247 int i;
14248 for (i = 0; i < 32 - first_greg; i++)
14249 if (global_regs[first_greg + i])
14250 return false;
14251 return true;
14252 }
14253
14254 #ifndef TARGET_FIX_AND_CONTINUE
14255 #define TARGET_FIX_AND_CONTINUE 0
14256 #endif
14257
14258 /* Emit function prologue as insns. */
14259
14260 void
rs6000_emit_prologue(void)14261 rs6000_emit_prologue (void)
14262 {
14263 rs6000_stack_t *info = rs6000_stack_info ();
14264 enum machine_mode reg_mode = Pmode;
14265 int reg_size = TARGET_32BIT ? 4 : 8;
14266 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14267 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14268 rtx frame_reg_rtx = sp_reg_rtx;
14269 rtx cr_save_rtx = NULL_RTX;
14270 rtx insn;
14271 int saving_FPRs_inline;
14272 int using_store_multiple;
14273 HOST_WIDE_INT sp_offset = 0;
14274
14275 if (TARGET_FIX_AND_CONTINUE)
14276 {
14277 /* gdb on darwin arranges to forward a function from the old
14278 address by modifying the first 5 instructions of the function
14279 to branch to the overriding function. This is necessary to
14280 permit function pointers that point to the old function to
14281 actually forward to the new function. */
14282 emit_insn (gen_nop ());
14283 emit_insn (gen_nop ());
14284 emit_insn (gen_nop ());
14285 emit_insn (gen_nop ());
14286 emit_insn (gen_nop ());
14287 }
14288
14289 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14290 {
14291 reg_mode = V2SImode;
14292 reg_size = 8;
14293 }
14294
14295 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14296 && (!TARGET_SPE_ABI
14297 || info->spe_64bit_regs_used == 0)
14298 && info->first_gp_reg_save < 31
14299 && no_global_regs_above (info->first_gp_reg_save));
14300 saving_FPRs_inline = (info->first_fp_reg_save == 64
14301 || FP_SAVE_INLINE (info->first_fp_reg_save)
14302 || current_function_calls_eh_return
14303 || cfun->machine->ra_need_lr);
14304
14305 /* For V.4, update stack before we do any saving and set back pointer. */
14306 if (! WORLD_SAVE_P (info)
14307 && info->push_p
14308 && (DEFAULT_ABI == ABI_V4
14309 || current_function_calls_eh_return))
14310 {
14311 if (info->total_size < 32767)
14312 sp_offset = info->total_size;
14313 else
14314 frame_reg_rtx = frame_ptr_rtx;
14315 rs6000_emit_allocate_stack (info->total_size,
14316 (frame_reg_rtx != sp_reg_rtx
14317 && (info->cr_save_p
14318 || info->lr_save_p
14319 || info->first_fp_reg_save < 64
14320 || info->first_gp_reg_save < 32
14321 )));
14322 if (frame_reg_rtx != sp_reg_rtx)
14323 rs6000_emit_stack_tie ();
14324 }
14325
14326 /* Handle world saves specially here. */
14327 if (WORLD_SAVE_P (info))
14328 {
14329 int i, j, sz;
14330 rtx treg;
14331 rtvec p;
14332 rtx reg0;
14333
14334 /* save_world expects lr in r0. */
14335 reg0 = gen_rtx_REG (Pmode, 0);
14336 if (info->lr_save_p)
14337 {
14338 insn = emit_move_insn (reg0,
14339 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14340 RTX_FRAME_RELATED_P (insn) = 1;
14341 }
14342
14343 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14344 assumptions about the offsets of various bits of the stack
14345 frame. */
14346 gcc_assert (info->gp_save_offset == -220
14347 && info->fp_save_offset == -144
14348 && info->lr_save_offset == 8
14349 && info->cr_save_offset == 4
14350 && info->push_p
14351 && info->lr_save_p
14352 && (!current_function_calls_eh_return
14353 || info->ehrd_offset == -432)
14354 && info->vrsave_save_offset == -224
14355 && info->altivec_save_offset == -416);
14356
14357 treg = gen_rtx_REG (SImode, 11);
14358 emit_move_insn (treg, GEN_INT (-info->total_size));
14359
14360 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14361 in R11. It also clobbers R12, so beware! */
14362
14363 /* Preserve CR2 for save_world prologues */
14364 sz = 5;
14365 sz += 32 - info->first_gp_reg_save;
14366 sz += 64 - info->first_fp_reg_save;
14367 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14368 p = rtvec_alloc (sz);
14369 j = 0;
14370 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14371 gen_rtx_REG (Pmode,
14372 LINK_REGISTER_REGNUM));
14373 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14374 gen_rtx_SYMBOL_REF (Pmode,
14375 "*save_world"));
14376 /* We do floats first so that the instruction pattern matches
14377 properly. */
14378 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14379 {
14380 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14381 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14382 GEN_INT (info->fp_save_offset
14383 + sp_offset + 8 * i));
14384 rtx mem = gen_frame_mem (DFmode, addr);
14385
14386 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14387 }
14388 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14389 {
14390 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14391 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14392 GEN_INT (info->altivec_save_offset
14393 + sp_offset + 16 * i));
14394 rtx mem = gen_frame_mem (V4SImode, addr);
14395
14396 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14397 }
14398 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14399 {
14400 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14401 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14402 GEN_INT (info->gp_save_offset
14403 + sp_offset + reg_size * i));
14404 rtx mem = gen_frame_mem (reg_mode, addr);
14405
14406 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14407 }
14408
14409 {
14410 /* CR register traditionally saved as CR2. */
14411 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14412 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14413 GEN_INT (info->cr_save_offset
14414 + sp_offset));
14415 rtx mem = gen_frame_mem (reg_mode, addr);
14416
14417 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14418 }
14419 /* Explain about use of R0. */
14420 if (info->lr_save_p)
14421 {
14422 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14423 GEN_INT (info->lr_save_offset
14424 + sp_offset));
14425 rtx mem = gen_frame_mem (reg_mode, addr);
14426
14427 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14428 }
14429 /* Explain what happens to the stack pointer. */
14430 {
14431 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14432 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14433 }
14434
14435 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14436 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14437 treg, GEN_INT (-info->total_size));
14438 sp_offset = info->total_size;
14439 }
14440
14441 /* Save AltiVec registers if needed. */
14442 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14443 {
14444 int i;
14445
14446 /* There should be a non inline version of this, for when we
14447 are saving lots of vector registers. */
14448 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14449 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14450 {
14451 rtx areg, savereg, mem;
14452 int offset;
14453
14454 offset = info->altivec_save_offset + sp_offset
14455 + 16 * (i - info->first_altivec_reg_save);
14456
14457 savereg = gen_rtx_REG (V4SImode, i);
14458
14459 areg = gen_rtx_REG (Pmode, 0);
14460 emit_move_insn (areg, GEN_INT (offset));
14461
14462 /* AltiVec addressing mode is [reg+reg]. */
14463 mem = gen_frame_mem (V4SImode,
14464 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14465
14466 insn = emit_move_insn (mem, savereg);
14467
14468 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14469 areg, GEN_INT (offset));
14470 }
14471 }
14472
14473 /* VRSAVE is a bit vector representing which AltiVec registers
14474 are used. The OS uses this to determine which vector
14475 registers to save on a context switch. We need to save
14476 VRSAVE on the stack frame, add whatever AltiVec registers we
14477 used in this function, and do the corresponding magic in the
14478 epilogue. */
14479
14480 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14481 && info->vrsave_mask != 0)
14482 {
14483 rtx reg, mem, vrsave;
14484 int offset;
14485
14486 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14487 as frame_reg_rtx and r11 as the static chain pointer for
14488 nested functions. */
14489 reg = gen_rtx_REG (SImode, 0);
14490 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14491 if (TARGET_MACHO)
14492 emit_insn (gen_get_vrsave_internal (reg));
14493 else
14494 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14495
14496 if (!WORLD_SAVE_P (info))
14497 {
14498 /* Save VRSAVE. */
14499 offset = info->vrsave_save_offset + sp_offset;
14500 mem = gen_frame_mem (SImode,
14501 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14502 GEN_INT (offset)));
14503 insn = emit_move_insn (mem, reg);
14504 }
14505
14506 /* Include the registers in the mask. */
14507 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14508
14509 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14510 }
14511
14512 /* If we use the link register, get it into r0. */
14513 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14514 {
14515 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14516 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14517 RTX_FRAME_RELATED_P (insn) = 1;
14518 }
14519
14520 /* If we need to save CR, put it into r12. */
14521 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14522 {
14523 rtx set;
14524
14525 cr_save_rtx = gen_rtx_REG (SImode, 12);
14526 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14527 RTX_FRAME_RELATED_P (insn) = 1;
14528 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14529 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14530 But that's OK. All we have to do is specify that _one_ condition
14531 code register is saved in this stack slot. The thrower's epilogue
14532 will then restore all the call-saved registers.
14533 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14534 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14535 gen_rtx_REG (SImode, CR2_REGNO));
14536 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14537 set,
14538 REG_NOTES (insn));
14539 }
14540
14541 /* Do any required saving of fpr's. If only one or two to save, do
14542 it ourselves. Otherwise, call function. */
14543 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14544 {
14545 int i;
14546 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14547 if ((regs_ever_live[info->first_fp_reg_save+i]
14548 && ! call_used_regs[info->first_fp_reg_save+i]))
14549 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14550 info->first_fp_reg_save + i,
14551 info->fp_save_offset + sp_offset + 8 * i,
14552 info->total_size);
14553 }
14554 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14555 {
14556 int i;
14557 char rname[30];
14558 const char *alloc_rname;
14559 rtvec p;
14560 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14561
14562 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14563 gen_rtx_REG (Pmode,
14564 LINK_REGISTER_REGNUM));
14565 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14566 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14567 alloc_rname = ggc_strdup (rname);
14568 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14569 gen_rtx_SYMBOL_REF (Pmode,
14570 alloc_rname));
14571 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14572 {
14573 rtx addr, reg, mem;
14574 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14575 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14576 GEN_INT (info->fp_save_offset
14577 + sp_offset + 8*i));
14578 mem = gen_frame_mem (DFmode, addr);
14579
14580 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14581 }
14582 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14583 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14584 NULL_RTX, NULL_RTX);
14585 }
14586
14587 /* Save GPRs. This is done as a PARALLEL if we are using
14588 the store-multiple instructions. */
14589 if (!WORLD_SAVE_P (info) && using_store_multiple)
14590 {
14591 rtvec p;
14592 int i;
14593 p = rtvec_alloc (32 - info->first_gp_reg_save);
14594 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14595 {
14596 rtx addr, reg, mem;
14597 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14598 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14599 GEN_INT (info->gp_save_offset
14600 + sp_offset
14601 + reg_size * i));
14602 mem = gen_frame_mem (reg_mode, addr);
14603
14604 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14605 }
14606 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14607 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14608 NULL_RTX, NULL_RTX);
14609 }
14610 else if (!WORLD_SAVE_P (info))
14611 {
14612 int i;
14613 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14614 if ((regs_ever_live[info->first_gp_reg_save + i]
14615 && (!call_used_regs[info->first_gp_reg_save + i]
14616 || (i + info->first_gp_reg_save
14617 == RS6000_PIC_OFFSET_TABLE_REGNUM
14618 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14619 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14620 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14621 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14622 {
14623 rtx addr, reg, mem;
14624 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14625
14626 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14627 {
14628 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14629 rtx b;
14630
14631 if (!SPE_CONST_OFFSET_OK (offset))
14632 {
14633 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14634 emit_move_insn (b, GEN_INT (offset));
14635 }
14636 else
14637 b = GEN_INT (offset);
14638
14639 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14640 mem = gen_frame_mem (V2SImode, addr);
14641 insn = emit_move_insn (mem, reg);
14642
14643 if (GET_CODE (b) == CONST_INT)
14644 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14645 NULL_RTX, NULL_RTX);
14646 else
14647 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14648 b, GEN_INT (offset));
14649 }
14650 else
14651 {
14652 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14653 GEN_INT (info->gp_save_offset
14654 + sp_offset
14655 + reg_size * i));
14656 mem = gen_frame_mem (reg_mode, addr);
14657
14658 insn = emit_move_insn (mem, reg);
14659 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14660 NULL_RTX, NULL_RTX);
14661 }
14662 }
14663 }
14664
14665 /* ??? There's no need to emit actual instructions here, but it's the
14666 easiest way to get the frame unwind information emitted. */
14667 if (current_function_calls_eh_return)
14668 {
14669 unsigned int i, regno;
14670
14671 /* In AIX ABI we need to pretend we save r2 here. */
14672 if (TARGET_AIX)
14673 {
14674 rtx addr, reg, mem;
14675
14676 reg = gen_rtx_REG (reg_mode, 2);
14677 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14678 GEN_INT (sp_offset + 5 * reg_size));
14679 mem = gen_frame_mem (reg_mode, addr);
14680
14681 insn = emit_move_insn (mem, reg);
14682 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14683 NULL_RTX, NULL_RTX);
14684 PATTERN (insn) = gen_blockage ();
14685 }
14686
14687 for (i = 0; ; ++i)
14688 {
14689 regno = EH_RETURN_DATA_REGNO (i);
14690 if (regno == INVALID_REGNUM)
14691 break;
14692
14693 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14694 info->ehrd_offset + sp_offset
14695 + reg_size * (int) i,
14696 info->total_size);
14697 }
14698 }
14699
14700 /* Save lr if we used it. */
14701 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14702 {
14703 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14704 GEN_INT (info->lr_save_offset + sp_offset));
14705 rtx reg = gen_rtx_REG (Pmode, 0);
14706 rtx mem = gen_rtx_MEM (Pmode, addr);
14707 /* This should not be of frame_alias_set, because of
14708 __builtin_return_address. */
14709
14710 insn = emit_move_insn (mem, reg);
14711 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14712 NULL_RTX, NULL_RTX);
14713 }
14714
14715 /* Save CR if we use any that must be preserved. */
14716 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14717 {
14718 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14719 GEN_INT (info->cr_save_offset + sp_offset));
14720 rtx mem = gen_frame_mem (SImode, addr);
14721 /* See the large comment above about why CR2_REGNO is used. */
14722 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14723
14724 /* If r12 was used to hold the original sp, copy cr into r0 now
14725 that it's free. */
14726 if (REGNO (frame_reg_rtx) == 12)
14727 {
14728 rtx set;
14729
14730 cr_save_rtx = gen_rtx_REG (SImode, 0);
14731 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14732 RTX_FRAME_RELATED_P (insn) = 1;
14733 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14734 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14735 set,
14736 REG_NOTES (insn));
14737
14738 }
14739 insn = emit_move_insn (mem, cr_save_rtx);
14740
14741 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14742 NULL_RTX, NULL_RTX);
14743 }
14744
14745 /* Update stack and set back pointer unless this is V.4,
14746 for which it was done previously. */
14747 if (!WORLD_SAVE_P (info) && info->push_p
14748 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14749 rs6000_emit_allocate_stack (info->total_size, FALSE);
14750
14751 /* Set frame pointer, if needed. */
14752 if (frame_pointer_needed)
14753 {
14754 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14755 sp_reg_rtx);
14756 RTX_FRAME_RELATED_P (insn) = 1;
14757 }
14758
14759 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14760 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14761 || (DEFAULT_ABI == ABI_V4
14762 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14763 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14764 {
14765 /* If emit_load_toc_table will use the link register, we need to save
14766 it. We use R12 for this purpose because emit_load_toc_table
14767 can use register 0. This allows us to use a plain 'blr' to return
14768 from the procedure more often. */
14769 int save_LR_around_toc_setup = (TARGET_ELF
14770 && DEFAULT_ABI != ABI_AIX
14771 && flag_pic
14772 && ! info->lr_save_p
14773 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14774 if (save_LR_around_toc_setup)
14775 {
14776 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14777
14778 insn = emit_move_insn (frame_ptr_rtx, lr);
14779 rs6000_maybe_dead (insn);
14780 RTX_FRAME_RELATED_P (insn) = 1;
14781
14782 rs6000_emit_load_toc_table (TRUE);
14783
14784 insn = emit_move_insn (lr, frame_ptr_rtx);
14785 rs6000_maybe_dead (insn);
14786 RTX_FRAME_RELATED_P (insn) = 1;
14787 }
14788 else
14789 rs6000_emit_load_toc_table (TRUE);
14790 }
14791
14792 #if TARGET_MACHO
14793 if (DEFAULT_ABI == ABI_DARWIN
14794 && flag_pic && current_function_uses_pic_offset_table)
14795 {
14796 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14797 rtx src = machopic_function_base_sym ();
14798
14799 /* Save and restore LR locally around this call (in R0). */
14800 if (!info->lr_save_p)
14801 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14802
14803 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14804
14805 insn = emit_move_insn (gen_rtx_REG (Pmode,
14806 RS6000_PIC_OFFSET_TABLE_REGNUM),
14807 lr);
14808 rs6000_maybe_dead (insn);
14809
14810 if (!info->lr_save_p)
14811 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14812 }
14813 #endif
14814 }
14815
14816 /* Write function prologue. */
14817
14818 static void
rs6000_output_function_prologue(FILE * file,HOST_WIDE_INT size ATTRIBUTE_UNUSED)14819 rs6000_output_function_prologue (FILE *file,
14820 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14821 {
14822 rs6000_stack_t *info = rs6000_stack_info ();
14823
14824 if (TARGET_DEBUG_STACK)
14825 debug_stack_info (info);
14826
14827 /* Write .extern for any function we will call to save and restore
14828 fp values. */
14829 if (info->first_fp_reg_save < 64
14830 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14831 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14832 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14833 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14834 RESTORE_FP_SUFFIX);
14835
14836 /* Write .extern for AIX common mode routines, if needed. */
14837 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14838 {
14839 fputs ("\t.extern __mulh\n", file);
14840 fputs ("\t.extern __mull\n", file);
14841 fputs ("\t.extern __divss\n", file);
14842 fputs ("\t.extern __divus\n", file);
14843 fputs ("\t.extern __quoss\n", file);
14844 fputs ("\t.extern __quous\n", file);
14845 common_mode_defined = 1;
14846 }
14847
14848 if (! HAVE_prologue)
14849 {
14850 start_sequence ();
14851
14852 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14853 the "toplevel" insn chain. */
14854 emit_note (NOTE_INSN_DELETED);
14855 rs6000_emit_prologue ();
14856 emit_note (NOTE_INSN_DELETED);
14857
14858 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14859 {
14860 rtx insn;
14861 unsigned addr = 0;
14862 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14863 {
14864 INSN_ADDRESSES_NEW (insn, addr);
14865 addr += 4;
14866 }
14867 }
14868
14869 if (TARGET_DEBUG_STACK)
14870 debug_rtx_list (get_insns (), 100);
14871 final (get_insns (), file, FALSE);
14872 end_sequence ();
14873 }
14874
14875 rs6000_pic_labelno++;
14876 }
14877
14878 /* Emit function epilogue as insns.
14879
14880 At present, dwarf2out_frame_debug_expr doesn't understand
14881 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14882 anywhere in the epilogue. Most of the insns below would in any case
14883 need special notes to explain where r11 is in relation to the stack. */
14884
14885 void
rs6000_emit_epilogue(int sibcall)14886 rs6000_emit_epilogue (int sibcall)
14887 {
14888 rs6000_stack_t *info;
14889 int restoring_FPRs_inline;
14890 int using_load_multiple;
14891 int using_mfcr_multiple;
14892 int use_backchain_to_restore_sp;
14893 int sp_offset = 0;
14894 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14895 rtx frame_reg_rtx = sp_reg_rtx;
14896 enum machine_mode reg_mode = Pmode;
14897 int reg_size = TARGET_32BIT ? 4 : 8;
14898 int i;
14899
14900 info = rs6000_stack_info ();
14901
14902 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14903 {
14904 reg_mode = V2SImode;
14905 reg_size = 8;
14906 }
14907
14908 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14909 && (!TARGET_SPE_ABI
14910 || info->spe_64bit_regs_used == 0)
14911 && info->first_gp_reg_save < 31
14912 && no_global_regs_above (info->first_gp_reg_save));
14913 restoring_FPRs_inline = (sibcall
14914 || current_function_calls_eh_return
14915 || info->first_fp_reg_save == 64
14916 || FP_SAVE_INLINE (info->first_fp_reg_save));
14917 use_backchain_to_restore_sp = (frame_pointer_needed
14918 || current_function_calls_alloca
14919 || info->total_size > 32767);
14920 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14921 || rs6000_cpu == PROCESSOR_PPC603
14922 || rs6000_cpu == PROCESSOR_PPC750
14923 || optimize_size);
14924
14925 if (WORLD_SAVE_P (info))
14926 {
14927 int i, j;
14928 char rname[30];
14929 const char *alloc_rname;
14930 rtvec p;
14931
14932 /* eh_rest_world_r10 will return to the location saved in the LR
14933 stack slot (which is not likely to be our caller.)
14934 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14935 rest_world is similar, except any R10 parameter is ignored.
14936 The exception-handling stuff that was here in 2.95 is no
14937 longer necessary. */
14938
14939 p = rtvec_alloc (9
14940 + 1
14941 + 32 - info->first_gp_reg_save
14942 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14943 + 63 + 1 - info->first_fp_reg_save);
14944
14945 strcpy (rname, ((current_function_calls_eh_return) ?
14946 "*eh_rest_world_r10" : "*rest_world"));
14947 alloc_rname = ggc_strdup (rname);
14948
14949 j = 0;
14950 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14951 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14952 gen_rtx_REG (Pmode,
14953 LINK_REGISTER_REGNUM));
14954 RTVEC_ELT (p, j++)
14955 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14956 /* The instruction pattern requires a clobber here;
14957 it is shared with the restVEC helper. */
14958 RTVEC_ELT (p, j++)
14959 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14960
14961 {
14962 /* CR register traditionally saved as CR2. */
14963 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14964 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14965 GEN_INT (info->cr_save_offset));
14966 rtx mem = gen_frame_mem (reg_mode, addr);
14967
14968 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14969 }
14970
14971 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14972 {
14973 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14974 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14975 GEN_INT (info->gp_save_offset
14976 + reg_size * i));
14977 rtx mem = gen_frame_mem (reg_mode, addr);
14978
14979 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14980 }
14981 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14982 {
14983 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14984 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14985 GEN_INT (info->altivec_save_offset
14986 + 16 * i));
14987 rtx mem = gen_frame_mem (V4SImode, addr);
14988
14989 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14990 }
14991 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14992 {
14993 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14994 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14995 GEN_INT (info->fp_save_offset
14996 + 8 * i));
14997 rtx mem = gen_frame_mem (DFmode, addr);
14998
14999 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15000 }
15001 RTVEC_ELT (p, j++)
15002 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15003 RTVEC_ELT (p, j++)
15004 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15005 RTVEC_ELT (p, j++)
15006 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15007 RTVEC_ELT (p, j++)
15008 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15009 RTVEC_ELT (p, j++)
15010 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15011 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15012
15013 return;
15014 }
15015
15016 /* If we have a frame pointer, a call to alloca, or a large stack
15017 frame, restore the old stack pointer using the backchain. Otherwise,
15018 we know what size to update it with. */
15019 if (use_backchain_to_restore_sp)
15020 {
15021 /* Under V.4, don't reset the stack pointer until after we're done
15022 loading the saved registers. */
15023 if (DEFAULT_ABI == ABI_V4)
15024 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15025
15026 emit_move_insn (frame_reg_rtx,
15027 gen_rtx_MEM (Pmode, sp_reg_rtx));
15028 }
15029 else if (info->push_p)
15030 {
15031 if (DEFAULT_ABI == ABI_V4
15032 || current_function_calls_eh_return)
15033 sp_offset = info->total_size;
15034 else
15035 {
15036 emit_insn (TARGET_32BIT
15037 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15038 GEN_INT (info->total_size))
15039 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15040 GEN_INT (info->total_size)));
15041 }
15042 }
15043
15044 /* Restore AltiVec registers if needed. */
15045 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15046 {
15047 int i;
15048
15049 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15050 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15051 {
15052 rtx addr, areg, mem;
15053
15054 areg = gen_rtx_REG (Pmode, 0);
15055 emit_move_insn
15056 (areg, GEN_INT (info->altivec_save_offset
15057 + sp_offset
15058 + 16 * (i - info->first_altivec_reg_save)));
15059
15060 /* AltiVec addressing mode is [reg+reg]. */
15061 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15062 mem = gen_frame_mem (V4SImode, addr);
15063
15064 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15065 }
15066 }
15067
15068 /* Restore VRSAVE if needed. */
15069 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15070 && info->vrsave_mask != 0)
15071 {
15072 rtx addr, mem, reg;
15073
15074 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15075 GEN_INT (info->vrsave_save_offset + sp_offset));
15076 mem = gen_frame_mem (SImode, addr);
15077 reg = gen_rtx_REG (SImode, 12);
15078 emit_move_insn (reg, mem);
15079
15080 emit_insn (generate_set_vrsave (reg, info, 1));
15081 }
15082
15083 /* Get the old lr if we saved it. */
15084 if (info->lr_save_p)
15085 {
15086 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15087 info->lr_save_offset + sp_offset);
15088
15089 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15090 }
15091
15092 /* Get the old cr if we saved it. */
15093 if (info->cr_save_p)
15094 {
15095 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15096 GEN_INT (info->cr_save_offset + sp_offset));
15097 rtx mem = gen_frame_mem (SImode, addr);
15098
15099 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15100 }
15101
15102 /* Set LR here to try to overlap restores below. */
15103 if (info->lr_save_p)
15104 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
15105 gen_rtx_REG (Pmode, 0));
15106
15107 /* Load exception handler data registers, if needed. */
15108 if (current_function_calls_eh_return)
15109 {
15110 unsigned int i, regno;
15111
15112 if (TARGET_AIX)
15113 {
15114 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15115 GEN_INT (sp_offset + 5 * reg_size));
15116 rtx mem = gen_frame_mem (reg_mode, addr);
15117
15118 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15119 }
15120
15121 for (i = 0; ; ++i)
15122 {
15123 rtx mem;
15124
15125 regno = EH_RETURN_DATA_REGNO (i);
15126 if (regno == INVALID_REGNUM)
15127 break;
15128
15129 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15130 info->ehrd_offset + sp_offset
15131 + reg_size * (int) i);
15132
15133 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15134 }
15135 }
15136
15137 /* Restore GPRs. This is done as a PARALLEL if we are using
15138 the load-multiple instructions. */
15139 if (using_load_multiple)
15140 {
15141 rtvec p;
15142 p = rtvec_alloc (32 - info->first_gp_reg_save);
15143 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15144 {
15145 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15146 GEN_INT (info->gp_save_offset
15147 + sp_offset
15148 + reg_size * i));
15149 rtx mem = gen_frame_mem (reg_mode, addr);
15150
15151 RTVEC_ELT (p, i) =
15152 gen_rtx_SET (VOIDmode,
15153 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15154 mem);
15155 }
15156 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15157 }
15158 else
15159 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15160 if ((regs_ever_live[info->first_gp_reg_save + i]
15161 && (!call_used_regs[info->first_gp_reg_save + i]
15162 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15163 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15164 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15165 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15166 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
15167 {
15168 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15169 GEN_INT (info->gp_save_offset
15170 + sp_offset
15171 + reg_size * i));
15172 rtx mem = gen_frame_mem (reg_mode, addr);
15173
15174 /* Restore 64-bit quantities for SPE. */
15175 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15176 {
15177 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15178 rtx b;
15179
15180 if (!SPE_CONST_OFFSET_OK (offset))
15181 {
15182 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15183 emit_move_insn (b, GEN_INT (offset));
15184 }
15185 else
15186 b = GEN_INT (offset);
15187
15188 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15189 mem = gen_frame_mem (V2SImode, addr);
15190 }
15191
15192 emit_move_insn (gen_rtx_REG (reg_mode,
15193 info->first_gp_reg_save + i), mem);
15194 }
15195
15196 /* Restore fpr's if we need to do it without calling a function. */
15197 if (restoring_FPRs_inline)
15198 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15199 if ((regs_ever_live[info->first_fp_reg_save+i]
15200 && ! call_used_regs[info->first_fp_reg_save+i]))
15201 {
15202 rtx addr, mem;
15203 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15204 GEN_INT (info->fp_save_offset
15205 + sp_offset
15206 + 8 * i));
15207 mem = gen_frame_mem (DFmode, addr);
15208
15209 emit_move_insn (gen_rtx_REG (DFmode,
15210 info->first_fp_reg_save + i),
15211 mem);
15212 }
15213
15214 /* If we saved cr, restore it here. Just those that were used. */
15215 if (info->cr_save_p)
15216 {
15217 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15218 int count = 0;
15219
15220 if (using_mfcr_multiple)
15221 {
15222 for (i = 0; i < 8; i++)
15223 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15224 count++;
15225 gcc_assert (count);
15226 }
15227
15228 if (using_mfcr_multiple && count > 1)
15229 {
15230 rtvec p;
15231 int ndx;
15232
15233 p = rtvec_alloc (count);
15234
15235 ndx = 0;
15236 for (i = 0; i < 8; i++)
15237 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15238 {
15239 rtvec r = rtvec_alloc (2);
15240 RTVEC_ELT (r, 0) = r12_rtx;
15241 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15242 RTVEC_ELT (p, ndx) =
15243 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15244 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15245 ndx++;
15246 }
15247 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15248 gcc_assert (ndx == count);
15249 }
15250 else
15251 for (i = 0; i < 8; i++)
15252 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15253 {
15254 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15255 CR0_REGNO+i),
15256 r12_rtx));
15257 }
15258 }
15259
15260 /* If this is V.4, unwind the stack pointer after all of the loads
15261 have been done. */
15262 if (frame_reg_rtx != sp_reg_rtx)
15263 {
15264 /* This blockage is needed so that sched doesn't decide to move
15265 the sp change before the register restores. */
15266 rs6000_emit_stack_tie ();
15267 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15268 }
15269 else if (sp_offset != 0)
15270 emit_insn (TARGET_32BIT
15271 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15272 GEN_INT (sp_offset))
15273 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15274 GEN_INT (sp_offset)));
15275
15276 if (current_function_calls_eh_return)
15277 {
15278 rtx sa = EH_RETURN_STACKADJ_RTX;
15279 emit_insn (TARGET_32BIT
15280 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15281 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15282 }
15283
15284 if (!sibcall)
15285 {
15286 rtvec p;
15287 if (! restoring_FPRs_inline)
15288 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15289 else
15290 p = rtvec_alloc (2);
15291
15292 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15293 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15294 gen_rtx_REG (Pmode,
15295 LINK_REGISTER_REGNUM));
15296
15297 /* If we have to restore more than two FP registers, branch to the
15298 restore function. It will return to our caller. */
15299 if (! restoring_FPRs_inline)
15300 {
15301 int i;
15302 char rname[30];
15303 const char *alloc_rname;
15304
15305 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15306 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15307 alloc_rname = ggc_strdup (rname);
15308 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15309 gen_rtx_SYMBOL_REF (Pmode,
15310 alloc_rname));
15311
15312 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15313 {
15314 rtx addr, mem;
15315 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15316 GEN_INT (info->fp_save_offset + 8*i));
15317 mem = gen_frame_mem (DFmode, addr);
15318
15319 RTVEC_ELT (p, i+3) =
15320 gen_rtx_SET (VOIDmode,
15321 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15322 mem);
15323 }
15324 }
15325
15326 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15327 }
15328 }
15329
15330 /* Write function epilogue. */
15331
15332 static void
rs6000_output_function_epilogue(FILE * file,HOST_WIDE_INT size ATTRIBUTE_UNUSED)15333 rs6000_output_function_epilogue (FILE *file,
15334 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15335 {
15336 if (! HAVE_epilogue)
15337 {
15338 rtx insn = get_last_insn ();
15339 /* If the last insn was a BARRIER, we don't have to write anything except
15340 the trace table. */
15341 if (GET_CODE (insn) == NOTE)
15342 insn = prev_nonnote_insn (insn);
15343 if (insn == 0 || GET_CODE (insn) != BARRIER)
15344 {
15345 /* This is slightly ugly, but at least we don't have two
15346 copies of the epilogue-emitting code. */
15347 start_sequence ();
15348
15349 /* A NOTE_INSN_DELETED is supposed to be at the start
15350 and end of the "toplevel" insn chain. */
15351 emit_note (NOTE_INSN_DELETED);
15352 rs6000_emit_epilogue (FALSE);
15353 emit_note (NOTE_INSN_DELETED);
15354
15355 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15356 {
15357 rtx insn;
15358 unsigned addr = 0;
15359 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15360 {
15361 INSN_ADDRESSES_NEW (insn, addr);
15362 addr += 4;
15363 }
15364 }
15365
15366 if (TARGET_DEBUG_STACK)
15367 debug_rtx_list (get_insns (), 100);
15368 final (get_insns (), file, FALSE);
15369 end_sequence ();
15370 }
15371 }
15372
15373 #if TARGET_MACHO
15374 macho_branch_islands ();
15375 /* Mach-O doesn't support labels at the end of objects, so if
15376 it looks like we might want one, insert a NOP. */
15377 {
15378 rtx insn = get_last_insn ();
15379 while (insn
15380 && NOTE_P (insn)
15381 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15382 insn = PREV_INSN (insn);
15383 if (insn
15384 && (LABEL_P (insn)
15385 || (NOTE_P (insn)
15386 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15387 fputs ("\tnop\n", file);
15388 }
15389 #endif
15390
15391 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15392 on its format.
15393
15394 We don't output a traceback table if -finhibit-size-directive was
15395 used. The documentation for -finhibit-size-directive reads
15396 ``don't output a @code{.size} assembler directive, or anything
15397 else that would cause trouble if the function is split in the
15398 middle, and the two halves are placed at locations far apart in
15399 memory.'' The traceback table has this property, since it
15400 includes the offset from the start of the function to the
15401 traceback table itself.
15402
15403 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15404 different traceback table. */
15405 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15406 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15407 {
15408 const char *fname = NULL;
15409 const char *language_string = lang_hooks.name;
15410 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15411 int i;
15412 int optional_tbtab;
15413 rs6000_stack_t *info = rs6000_stack_info ();
15414
15415 if (rs6000_traceback == traceback_full)
15416 optional_tbtab = 1;
15417 else if (rs6000_traceback == traceback_part)
15418 optional_tbtab = 0;
15419 else
15420 optional_tbtab = !optimize_size && !TARGET_ELF;
15421
15422 if (optional_tbtab)
15423 {
15424 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15425 while (*fname == '.') /* V.4 encodes . in the name */
15426 fname++;
15427
15428 /* Need label immediately before tbtab, so we can compute
15429 its offset from the function start. */
15430 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15431 ASM_OUTPUT_LABEL (file, fname);
15432 }
15433
15434 /* The .tbtab pseudo-op can only be used for the first eight
15435 expressions, since it can't handle the possibly variable
15436 length fields that follow. However, if you omit the optional
15437 fields, the assembler outputs zeros for all optional fields
15438 anyways, giving each variable length field is minimum length
15439 (as defined in sys/debug.h). Thus we can not use the .tbtab
15440 pseudo-op at all. */
15441
15442 /* An all-zero word flags the start of the tbtab, for debuggers
15443 that have to find it by searching forward from the entry
15444 point or from the current pc. */
15445 fputs ("\t.long 0\n", file);
15446
15447 /* Tbtab format type. Use format type 0. */
15448 fputs ("\t.byte 0,", file);
15449
15450 /* Language type. Unfortunately, there does not seem to be any
15451 official way to discover the language being compiled, so we
15452 use language_string.
15453 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15454 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15455 a number, so for now use 9. */
15456 if (! strcmp (language_string, "GNU C"))
15457 i = 0;
15458 else if (! strcmp (language_string, "GNU F77")
15459 || ! strcmp (language_string, "GNU F95"))
15460 i = 1;
15461 else if (! strcmp (language_string, "GNU Pascal"))
15462 i = 2;
15463 else if (! strcmp (language_string, "GNU Ada"))
15464 i = 3;
15465 else if (! strcmp (language_string, "GNU C++")
15466 || ! strcmp (language_string, "GNU Objective-C++"))
15467 i = 9;
15468 else if (! strcmp (language_string, "GNU Java"))
15469 i = 13;
15470 else if (! strcmp (language_string, "GNU Objective-C"))
15471 i = 14;
15472 else
15473 gcc_unreachable ();
15474 fprintf (file, "%d,", i);
15475
15476 /* 8 single bit fields: global linkage (not set for C extern linkage,
15477 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15478 from start of procedure stored in tbtab, internal function, function
15479 has controlled storage, function has no toc, function uses fp,
15480 function logs/aborts fp operations. */
15481 /* Assume that fp operations are used if any fp reg must be saved. */
15482 fprintf (file, "%d,",
15483 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15484
15485 /* 6 bitfields: function is interrupt handler, name present in
15486 proc table, function calls alloca, on condition directives
15487 (controls stack walks, 3 bits), saves condition reg, saves
15488 link reg. */
15489 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15490 set up as a frame pointer, even when there is no alloca call. */
15491 fprintf (file, "%d,",
15492 ((optional_tbtab << 6)
15493 | ((optional_tbtab & frame_pointer_needed) << 5)
15494 | (info->cr_save_p << 1)
15495 | (info->lr_save_p)));
15496
15497 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15498 (6 bits). */
15499 fprintf (file, "%d,",
15500 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15501
15502 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15503 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15504
15505 if (optional_tbtab)
15506 {
15507 /* Compute the parameter info from the function decl argument
15508 list. */
15509 tree decl;
15510 int next_parm_info_bit = 31;
15511
15512 for (decl = DECL_ARGUMENTS (current_function_decl);
15513 decl; decl = TREE_CHAIN (decl))
15514 {
15515 rtx parameter = DECL_INCOMING_RTL (decl);
15516 enum machine_mode mode = GET_MODE (parameter);
15517
15518 if (GET_CODE (parameter) == REG)
15519 {
15520 if (SCALAR_FLOAT_MODE_P (mode))
15521 {
15522 int bits;
15523
15524 float_parms++;
15525
15526 switch (mode)
15527 {
15528 case SFmode:
15529 bits = 0x2;
15530 break;
15531
15532 case DFmode:
15533 case TFmode:
15534 bits = 0x3;
15535 break;
15536
15537 default:
15538 gcc_unreachable ();
15539 }
15540
15541 /* If only one bit will fit, don't or in this entry. */
15542 if (next_parm_info_bit > 0)
15543 parm_info |= (bits << (next_parm_info_bit - 1));
15544 next_parm_info_bit -= 2;
15545 }
15546 else
15547 {
15548 fixed_parms += ((GET_MODE_SIZE (mode)
15549 + (UNITS_PER_WORD - 1))
15550 / UNITS_PER_WORD);
15551 next_parm_info_bit -= 1;
15552 }
15553 }
15554 }
15555 }
15556
15557 /* Number of fixed point parameters. */
15558 /* This is actually the number of words of fixed point parameters; thus
15559 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15560 fprintf (file, "%d,", fixed_parms);
15561
15562 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15563 all on stack. */
15564 /* This is actually the number of fp registers that hold parameters;
15565 and thus the maximum value is 13. */
15566 /* Set parameters on stack bit if parameters are not in their original
15567 registers, regardless of whether they are on the stack? Xlc
15568 seems to set the bit when not optimizing. */
15569 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15570
15571 if (! optional_tbtab)
15572 return;
15573
15574 /* Optional fields follow. Some are variable length. */
15575
15576 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15577 11 double float. */
15578 /* There is an entry for each parameter in a register, in the order that
15579 they occur in the parameter list. Any intervening arguments on the
15580 stack are ignored. If the list overflows a long (max possible length
15581 34 bits) then completely leave off all elements that don't fit. */
15582 /* Only emit this long if there was at least one parameter. */
15583 if (fixed_parms || float_parms)
15584 fprintf (file, "\t.long %d\n", parm_info);
15585
15586 /* Offset from start of code to tb table. */
15587 fputs ("\t.long ", file);
15588 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15589 if (TARGET_AIX)
15590 RS6000_OUTPUT_BASENAME (file, fname);
15591 else
15592 assemble_name (file, fname);
15593 putc ('-', file);
15594 rs6000_output_function_entry (file, fname);
15595 putc ('\n', file);
15596
15597 /* Interrupt handler mask. */
15598 /* Omit this long, since we never set the interrupt handler bit
15599 above. */
15600
15601 /* Number of CTL (controlled storage) anchors. */
15602 /* Omit this long, since the has_ctl bit is never set above. */
15603
15604 /* Displacement into stack of each CTL anchor. */
15605 /* Omit this list of longs, because there are no CTL anchors. */
15606
15607 /* Length of function name. */
15608 if (*fname == '*')
15609 ++fname;
15610 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15611
15612 /* Function name. */
15613 assemble_string (fname, strlen (fname));
15614
15615 /* Register for alloca automatic storage; this is always reg 31.
15616 Only emit this if the alloca bit was set above. */
15617 if (frame_pointer_needed)
15618 fputs ("\t.byte 31\n", file);
15619
15620 fputs ("\t.align 2\n", file);
15621 }
15622 }
15623
15624 /* A C compound statement that outputs the assembler code for a thunk
15625 function, used to implement C++ virtual function calls with
15626 multiple inheritance. The thunk acts as a wrapper around a virtual
15627 function, adjusting the implicit object parameter before handing
15628 control off to the real function.
15629
15630 First, emit code to add the integer DELTA to the location that
15631 contains the incoming first argument. Assume that this argument
15632 contains a pointer, and is the one used to pass the `this' pointer
15633 in C++. This is the incoming argument *before* the function
15634 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15635 values of all other incoming arguments.
15636
15637 After the addition, emit code to jump to FUNCTION, which is a
15638 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15639 not touch the return address. Hence returning from FUNCTION will
15640 return to whoever called the current `thunk'.
15641
15642 The effect must be as if FUNCTION had been called directly with the
15643 adjusted first argument. This macro is responsible for emitting
15644 all of the code for a thunk function; output_function_prologue()
15645 and output_function_epilogue() are not invoked.
15646
15647 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15648 been extracted from it.) It might possibly be useful on some
15649 targets, but probably not.
15650
15651 If you do not define this macro, the target-independent code in the
15652 C++ frontend will generate a less efficient heavyweight thunk that
15653 calls FUNCTION instead of jumping to it. The generic approach does
15654 not support varargs. */
15655
15656 static void
rs6000_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)15657 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15658 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15659 tree function)
15660 {
15661 rtx this, insn, funexp;
15662
15663 reload_completed = 1;
15664 epilogue_completed = 1;
15665 no_new_pseudos = 1;
15666 reset_block_changes ();
15667
15668 /* Mark the end of the (empty) prologue. */
15669 emit_note (NOTE_INSN_PROLOGUE_END);
15670
15671 /* Find the "this" pointer. If the function returns a structure,
15672 the structure return pointer is in r3. */
15673 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15674 this = gen_rtx_REG (Pmode, 4);
15675 else
15676 this = gen_rtx_REG (Pmode, 3);
15677
15678 /* Apply the constant offset, if required. */
15679 if (delta)
15680 {
15681 rtx delta_rtx = GEN_INT (delta);
15682 emit_insn (TARGET_32BIT
15683 ? gen_addsi3 (this, this, delta_rtx)
15684 : gen_adddi3 (this, this, delta_rtx));
15685 }
15686
15687 /* Apply the offset from the vtable, if required. */
15688 if (vcall_offset)
15689 {
15690 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15691 rtx tmp = gen_rtx_REG (Pmode, 12);
15692
15693 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15694 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15695 {
15696 emit_insn (TARGET_32BIT
15697 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15698 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15699 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15700 }
15701 else
15702 {
15703 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15704
15705 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15706 }
15707 emit_insn (TARGET_32BIT
15708 ? gen_addsi3 (this, this, tmp)
15709 : gen_adddi3 (this, this, tmp));
15710 }
15711
15712 /* Generate a tail call to the target function. */
15713 if (!TREE_USED (function))
15714 {
15715 assemble_external (function);
15716 TREE_USED (function) = 1;
15717 }
15718 funexp = XEXP (DECL_RTL (function), 0);
15719 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15720
15721 #if TARGET_MACHO
15722 if (MACHOPIC_INDIRECT)
15723 funexp = machopic_indirect_call_target (funexp);
15724 #endif
15725
15726 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15727 generate sibcall RTL explicitly. */
15728 insn = emit_call_insn (
15729 gen_rtx_PARALLEL (VOIDmode,
15730 gen_rtvec (4,
15731 gen_rtx_CALL (VOIDmode,
15732 funexp, const0_rtx),
15733 gen_rtx_USE (VOIDmode, const0_rtx),
15734 gen_rtx_USE (VOIDmode,
15735 gen_rtx_REG (SImode,
15736 LINK_REGISTER_REGNUM)),
15737 gen_rtx_RETURN (VOIDmode))));
15738 SIBLING_CALL_P (insn) = 1;
15739 emit_barrier ();
15740
15741 /* Run just enough of rest_of_compilation to get the insns emitted.
15742 There's not really enough bulk here to make other passes such as
15743 instruction scheduling worth while. Note that use_thunk calls
15744 assemble_start_function and assemble_end_function. */
15745 insn = get_insns ();
15746 insn_locators_initialize ();
15747 shorten_branches (insn);
15748 final_start_function (insn, file, 1);
15749 final (insn, file, 1);
15750 final_end_function ();
15751
15752 reload_completed = 0;
15753 epilogue_completed = 0;
15754 no_new_pseudos = 0;
15755 }
15756
15757 /* A quick summary of the various types of 'constant-pool tables'
15758 under PowerPC:
15759
15760 Target Flags Name One table per
15761 AIX (none) AIX TOC object file
15762 AIX -mfull-toc AIX TOC object file
15763 AIX -mminimal-toc AIX minimal TOC translation unit
15764 SVR4/EABI (none) SVR4 SDATA object file
15765 SVR4/EABI -fpic SVR4 pic object file
15766 SVR4/EABI -fPIC SVR4 PIC translation unit
15767 SVR4/EABI -mrelocatable EABI TOC function
15768 SVR4/EABI -maix AIX TOC object file
15769 SVR4/EABI -maix -mminimal-toc
15770 AIX minimal TOC translation unit
15771
15772 Name Reg. Set by entries contains:
15773 made by addrs? fp? sum?
15774
15775 AIX TOC 2 crt0 as Y option option
15776 AIX minimal TOC 30 prolog gcc Y Y option
15777 SVR4 SDATA 13 crt0 gcc N Y N
15778 SVR4 pic 30 prolog ld Y not yet N
15779 SVR4 PIC 30 prolog gcc Y option option
15780 EABI TOC 30 prolog gcc Y option option
15781
15782 */
15783
15784 /* Hash functions for the hash table. */
15785
15786 static unsigned
rs6000_hash_constant(rtx k)15787 rs6000_hash_constant (rtx k)
15788 {
15789 enum rtx_code code = GET_CODE (k);
15790 enum machine_mode mode = GET_MODE (k);
15791 unsigned result = (code << 3) ^ mode;
15792 const char *format;
15793 int flen, fidx;
15794
15795 format = GET_RTX_FORMAT (code);
15796 flen = strlen (format);
15797 fidx = 0;
15798
15799 switch (code)
15800 {
15801 case LABEL_REF:
15802 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15803
15804 case CONST_DOUBLE:
15805 if (mode != VOIDmode)
15806 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15807 flen = 2;
15808 break;
15809
15810 case CODE_LABEL:
15811 fidx = 3;
15812 break;
15813
15814 default:
15815 break;
15816 }
15817
15818 for (; fidx < flen; fidx++)
15819 switch (format[fidx])
15820 {
15821 case 's':
15822 {
15823 unsigned i, len;
15824 const char *str = XSTR (k, fidx);
15825 len = strlen (str);
15826 result = result * 613 + len;
15827 for (i = 0; i < len; i++)
15828 result = result * 613 + (unsigned) str[i];
15829 break;
15830 }
15831 case 'u':
15832 case 'e':
15833 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15834 break;
15835 case 'i':
15836 case 'n':
15837 result = result * 613 + (unsigned) XINT (k, fidx);
15838 break;
15839 case 'w':
15840 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15841 result = result * 613 + (unsigned) XWINT (k, fidx);
15842 else
15843 {
15844 size_t i;
15845 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15846 result = result * 613 + (unsigned) (XWINT (k, fidx)
15847 >> CHAR_BIT * i);
15848 }
15849 break;
15850 case '0':
15851 break;
15852 default:
15853 gcc_unreachable ();
15854 }
15855
15856 return result;
15857 }
15858
15859 static unsigned
toc_hash_function(const void * hash_entry)15860 toc_hash_function (const void *hash_entry)
15861 {
15862 const struct toc_hash_struct *thc =
15863 (const struct toc_hash_struct *) hash_entry;
15864 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15865 }
15866
15867 /* Compare H1 and H2 for equivalence. */
15868
15869 static int
toc_hash_eq(const void * h1,const void * h2)15870 toc_hash_eq (const void *h1, const void *h2)
15871 {
15872 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15873 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15874
15875 if (((const struct toc_hash_struct *) h1)->key_mode
15876 != ((const struct toc_hash_struct *) h2)->key_mode)
15877 return 0;
15878
15879 return rtx_equal_p (r1, r2);
15880 }
15881
15882 /* These are the names given by the C++ front-end to vtables, and
15883 vtable-like objects. Ideally, this logic should not be here;
15884 instead, there should be some programmatic way of inquiring as
15885 to whether or not an object is a vtable. */
15886
15887 #define VTABLE_NAME_P(NAME) \
15888 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15889 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15890 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15891 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15892 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15893
15894 void
rs6000_output_symbol_ref(FILE * file,rtx x)15895 rs6000_output_symbol_ref (FILE *file, rtx x)
15896 {
15897 /* Currently C++ toc references to vtables can be emitted before it
15898 is decided whether the vtable is public or private. If this is
15899 the case, then the linker will eventually complain that there is
15900 a reference to an unknown section. Thus, for vtables only,
15901 we emit the TOC reference to reference the symbol and not the
15902 section. */
15903 const char *name = XSTR (x, 0);
15904
15905 if (VTABLE_NAME_P (name))
15906 {
15907 RS6000_OUTPUT_BASENAME (file, name);
15908 }
15909 else
15910 assemble_name (file, name);
15911 }
15912
15913 /* Output a TOC entry. We derive the entry name from what is being
15914 written. */
15915
15916 void
output_toc(FILE * file,rtx x,int labelno,enum machine_mode mode)15917 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15918 {
15919 char buf[256];
15920 const char *name = buf;
15921 const char *real_name;
15922 rtx base = x;
15923 HOST_WIDE_INT offset = 0;
15924
15925 gcc_assert (!TARGET_NO_TOC);
15926
15927 /* When the linker won't eliminate them, don't output duplicate
15928 TOC entries (this happens on AIX if there is any kind of TOC,
15929 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15930 CODE_LABELs. */
15931 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15932 {
15933 struct toc_hash_struct *h;
15934 void * * found;
15935
15936 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15937 time because GGC is not initialized at that point. */
15938 if (toc_hash_table == NULL)
15939 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15940 toc_hash_eq, NULL);
15941
15942 h = ggc_alloc (sizeof (*h));
15943 h->key = x;
15944 h->key_mode = mode;
15945 h->labelno = labelno;
15946
15947 found = htab_find_slot (toc_hash_table, h, 1);
15948 if (*found == NULL)
15949 *found = h;
15950 else /* This is indeed a duplicate.
15951 Set this label equal to that label. */
15952 {
15953 fputs ("\t.set ", file);
15954 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15955 fprintf (file, "%d,", labelno);
15956 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15957 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15958 found)->labelno));
15959 return;
15960 }
15961 }
15962
15963 /* If we're going to put a double constant in the TOC, make sure it's
15964 aligned properly when strict alignment is on. */
15965 if (GET_CODE (x) == CONST_DOUBLE
15966 && STRICT_ALIGNMENT
15967 && GET_MODE_BITSIZE (mode) >= 64
15968 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15969 ASM_OUTPUT_ALIGN (file, 3);
15970 }
15971
15972 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15973
15974 /* Handle FP constants specially. Note that if we have a minimal
15975 TOC, things we put here aren't actually in the TOC, so we can allow
15976 FP constants. */
15977 if (GET_CODE (x) == CONST_DOUBLE &&
15978 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
15979 {
15980 REAL_VALUE_TYPE rv;
15981 long k[4];
15982
15983 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15984 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15985 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
15986 else
15987 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15988
15989 if (TARGET_64BIT)
15990 {
15991 if (TARGET_MINIMAL_TOC)
15992 fputs (DOUBLE_INT_ASM_OP, file);
15993 else
15994 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15995 k[0] & 0xffffffff, k[1] & 0xffffffff,
15996 k[2] & 0xffffffff, k[3] & 0xffffffff);
15997 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15998 k[0] & 0xffffffff, k[1] & 0xffffffff,
15999 k[2] & 0xffffffff, k[3] & 0xffffffff);
16000 return;
16001 }
16002 else
16003 {
16004 if (TARGET_MINIMAL_TOC)
16005 fputs ("\t.long ", file);
16006 else
16007 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16008 k[0] & 0xffffffff, k[1] & 0xffffffff,
16009 k[2] & 0xffffffff, k[3] & 0xffffffff);
16010 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16011 k[0] & 0xffffffff, k[1] & 0xffffffff,
16012 k[2] & 0xffffffff, k[3] & 0xffffffff);
16013 return;
16014 }
16015 }
16016 else if (GET_CODE (x) == CONST_DOUBLE &&
16017 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16018 {
16019 REAL_VALUE_TYPE rv;
16020 long k[2];
16021
16022 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16023
16024 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16025 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16026 else
16027 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16028
16029 if (TARGET_64BIT)
16030 {
16031 if (TARGET_MINIMAL_TOC)
16032 fputs (DOUBLE_INT_ASM_OP, file);
16033 else
16034 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16035 k[0] & 0xffffffff, k[1] & 0xffffffff);
16036 fprintf (file, "0x%lx%08lx\n",
16037 k[0] & 0xffffffff, k[1] & 0xffffffff);
16038 return;
16039 }
16040 else
16041 {
16042 if (TARGET_MINIMAL_TOC)
16043 fputs ("\t.long ", file);
16044 else
16045 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16046 k[0] & 0xffffffff, k[1] & 0xffffffff);
16047 fprintf (file, "0x%lx,0x%lx\n",
16048 k[0] & 0xffffffff, k[1] & 0xffffffff);
16049 return;
16050 }
16051 }
16052 else if (GET_CODE (x) == CONST_DOUBLE &&
16053 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16054 {
16055 REAL_VALUE_TYPE rv;
16056 long l;
16057
16058 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16059 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16060 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16061 else
16062 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16063
16064 if (TARGET_64BIT)
16065 {
16066 if (TARGET_MINIMAL_TOC)
16067 fputs (DOUBLE_INT_ASM_OP, file);
16068 else
16069 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16070 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16071 return;
16072 }
16073 else
16074 {
16075 if (TARGET_MINIMAL_TOC)
16076 fputs ("\t.long ", file);
16077 else
16078 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16079 fprintf (file, "0x%lx\n", l & 0xffffffff);
16080 return;
16081 }
16082 }
16083 else if (GET_MODE (x) == VOIDmode
16084 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16085 {
16086 unsigned HOST_WIDE_INT low;
16087 HOST_WIDE_INT high;
16088
16089 if (GET_CODE (x) == CONST_DOUBLE)
16090 {
16091 low = CONST_DOUBLE_LOW (x);
16092 high = CONST_DOUBLE_HIGH (x);
16093 }
16094 else
16095 #if HOST_BITS_PER_WIDE_INT == 32
16096 {
16097 low = INTVAL (x);
16098 high = (low & 0x80000000) ? ~0 : 0;
16099 }
16100 #else
16101 {
16102 low = INTVAL (x) & 0xffffffff;
16103 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16104 }
16105 #endif
16106
16107 /* TOC entries are always Pmode-sized, but since this
16108 is a bigendian machine then if we're putting smaller
16109 integer constants in the TOC we have to pad them.
16110 (This is still a win over putting the constants in
16111 a separate constant pool, because then we'd have
16112 to have both a TOC entry _and_ the actual constant.)
16113
16114 For a 32-bit target, CONST_INT values are loaded and shifted
16115 entirely within `low' and can be stored in one TOC entry. */
16116
16117 /* It would be easy to make this work, but it doesn't now. */
16118 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16119
16120 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16121 {
16122 #if HOST_BITS_PER_WIDE_INT == 32
16123 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16124 POINTER_SIZE, &low, &high, 0);
16125 #else
16126 low |= high << 32;
16127 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16128 high = (HOST_WIDE_INT) low >> 32;
16129 low &= 0xffffffff;
16130 #endif
16131 }
16132
16133 if (TARGET_64BIT)
16134 {
16135 if (TARGET_MINIMAL_TOC)
16136 fputs (DOUBLE_INT_ASM_OP, file);
16137 else
16138 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16139 (long) high & 0xffffffff, (long) low & 0xffffffff);
16140 fprintf (file, "0x%lx%08lx\n",
16141 (long) high & 0xffffffff, (long) low & 0xffffffff);
16142 return;
16143 }
16144 else
16145 {
16146 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16147 {
16148 if (TARGET_MINIMAL_TOC)
16149 fputs ("\t.long ", file);
16150 else
16151 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16152 (long) high & 0xffffffff, (long) low & 0xffffffff);
16153 fprintf (file, "0x%lx,0x%lx\n",
16154 (long) high & 0xffffffff, (long) low & 0xffffffff);
16155 }
16156 else
16157 {
16158 if (TARGET_MINIMAL_TOC)
16159 fputs ("\t.long ", file);
16160 else
16161 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16162 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16163 }
16164 return;
16165 }
16166 }
16167
16168 if (GET_CODE (x) == CONST)
16169 {
16170 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16171
16172 base = XEXP (XEXP (x, 0), 0);
16173 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16174 }
16175
16176 switch (GET_CODE (base))
16177 {
16178 case SYMBOL_REF:
16179 name = XSTR (base, 0);
16180 break;
16181
16182 case LABEL_REF:
16183 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16184 CODE_LABEL_NUMBER (XEXP (base, 0)));
16185 break;
16186
16187 case CODE_LABEL:
16188 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16189 break;
16190
16191 default:
16192 gcc_unreachable ();
16193 }
16194
16195 real_name = (*targetm.strip_name_encoding) (name);
16196 if (TARGET_MINIMAL_TOC)
16197 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16198 else
16199 {
16200 fprintf (file, "\t.tc %s", real_name);
16201
16202 if (offset < 0)
16203 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16204 else if (offset)
16205 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16206
16207 fputs ("[TC],", file);
16208 }
16209
16210 /* Currently C++ toc references to vtables can be emitted before it
16211 is decided whether the vtable is public or private. If this is
16212 the case, then the linker will eventually complain that there is
16213 a TOC reference to an unknown section. Thus, for vtables only,
16214 we emit the TOC reference to reference the symbol and not the
16215 section. */
16216 if (VTABLE_NAME_P (name))
16217 {
16218 RS6000_OUTPUT_BASENAME (file, name);
16219 if (offset < 0)
16220 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16221 else if (offset > 0)
16222 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16223 }
16224 else
16225 output_addr_const (file, x);
16226 putc ('\n', file);
16227 }
16228
16229 /* Output an assembler pseudo-op to write an ASCII string of N characters
16230 starting at P to FILE.
16231
16232 On the RS/6000, we have to do this using the .byte operation and
16233 write out special characters outside the quoted string.
16234 Also, the assembler is broken; very long strings are truncated,
16235 so we must artificially break them up early. */
16236
16237 void
output_ascii(FILE * file,const char * p,int n)16238 output_ascii (FILE *file, const char *p, int n)
16239 {
16240 char c;
16241 int i, count_string;
16242 const char *for_string = "\t.byte \"";
16243 const char *for_decimal = "\t.byte ";
16244 const char *to_close = NULL;
16245
16246 count_string = 0;
16247 for (i = 0; i < n; i++)
16248 {
16249 c = *p++;
16250 if (c >= ' ' && c < 0177)
16251 {
16252 if (for_string)
16253 fputs (for_string, file);
16254 putc (c, file);
16255
16256 /* Write two quotes to get one. */
16257 if (c == '"')
16258 {
16259 putc (c, file);
16260 ++count_string;
16261 }
16262
16263 for_string = NULL;
16264 for_decimal = "\"\n\t.byte ";
16265 to_close = "\"\n";
16266 ++count_string;
16267
16268 if (count_string >= 512)
16269 {
16270 fputs (to_close, file);
16271
16272 for_string = "\t.byte \"";
16273 for_decimal = "\t.byte ";
16274 to_close = NULL;
16275 count_string = 0;
16276 }
16277 }
16278 else
16279 {
16280 if (for_decimal)
16281 fputs (for_decimal, file);
16282 fprintf (file, "%d", c);
16283
16284 for_string = "\n\t.byte \"";
16285 for_decimal = ", ";
16286 to_close = "\n";
16287 count_string = 0;
16288 }
16289 }
16290
16291 /* Now close the string if we have written one. Then end the line. */
16292 if (to_close)
16293 fputs (to_close, file);
16294 }
16295
16296 /* Generate a unique section name for FILENAME for a section type
16297 represented by SECTION_DESC. Output goes into BUF.
16298
16299 SECTION_DESC can be any string, as long as it is different for each
16300 possible section type.
16301
16302 We name the section in the same manner as xlc. The name begins with an
16303 underscore followed by the filename (after stripping any leading directory
16304 names) with the last period replaced by the string SECTION_DESC. If
16305 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16306 the name. */
16307
16308 void
rs6000_gen_section_name(char ** buf,const char * filename,const char * section_desc)16309 rs6000_gen_section_name (char **buf, const char *filename,
16310 const char *section_desc)
16311 {
16312 const char *q, *after_last_slash, *last_period = 0;
16313 char *p;
16314 int len;
16315
16316 after_last_slash = filename;
16317 for (q = filename; *q; q++)
16318 {
16319 if (*q == '/')
16320 after_last_slash = q + 1;
16321 else if (*q == '.')
16322 last_period = q;
16323 }
16324
16325 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16326 *buf = (char *) xmalloc (len);
16327
16328 p = *buf;
16329 *p++ = '_';
16330
16331 for (q = after_last_slash; *q; q++)
16332 {
16333 if (q == last_period)
16334 {
16335 strcpy (p, section_desc);
16336 p += strlen (section_desc);
16337 break;
16338 }
16339
16340 else if (ISALNUM (*q))
16341 *p++ = *q;
16342 }
16343
16344 if (last_period == 0)
16345 strcpy (p, section_desc);
16346 else
16347 *p = '\0';
16348 }
16349
16350 /* Emit profile function. */
16351
16352 void
output_profile_hook(int labelno ATTRIBUTE_UNUSED)16353 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16354 {
16355 /* Non-standard profiling for kernels, which just saves LR then calls
16356 _mcount without worrying about arg saves. The idea is to change
16357 the function prologue as little as possible as it isn't easy to
16358 account for arg save/restore code added just for _mcount. */
16359 if (TARGET_PROFILE_KERNEL)
16360 return;
16361
16362 if (DEFAULT_ABI == ABI_AIX)
16363 {
16364 #ifndef NO_PROFILE_COUNTERS
16365 # define NO_PROFILE_COUNTERS 0
16366 #endif
16367 if (NO_PROFILE_COUNTERS)
16368 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16369 else
16370 {
16371 char buf[30];
16372 const char *label_name;
16373 rtx fun;
16374
16375 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16376 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16377 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16378
16379 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16380 fun, Pmode);
16381 }
16382 }
16383 else if (DEFAULT_ABI == ABI_DARWIN)
16384 {
16385 const char *mcount_name = RS6000_MCOUNT;
16386 int caller_addr_regno = LINK_REGISTER_REGNUM;
16387
16388 /* Be conservative and always set this, at least for now. */
16389 current_function_uses_pic_offset_table = 1;
16390
16391 #if TARGET_MACHO
16392 /* For PIC code, set up a stub and collect the caller's address
16393 from r0, which is where the prologue puts it. */
16394 if (MACHOPIC_INDIRECT
16395 && current_function_uses_pic_offset_table)
16396 caller_addr_regno = 0;
16397 #endif
16398 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16399 0, VOIDmode, 1,
16400 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16401 }
16402 }
16403
16404 /* Write function profiler code. */
16405
16406 void
output_function_profiler(FILE * file,int labelno)16407 output_function_profiler (FILE *file, int labelno)
16408 {
16409 char buf[100];
16410
16411 switch (DEFAULT_ABI)
16412 {
16413 default:
16414 gcc_unreachable ();
16415
16416 case ABI_V4:
16417 if (!TARGET_32BIT)
16418 {
16419 warning (0, "no profiling of 64-bit code for this ABI");
16420 return;
16421 }
16422 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16423 fprintf (file, "\tmflr %s\n", reg_names[0]);
16424 if (NO_PROFILE_COUNTERS)
16425 {
16426 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16427 reg_names[0], reg_names[1]);
16428 }
16429 else if (TARGET_SECURE_PLT && flag_pic)
16430 {
16431 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16432 reg_names[0], reg_names[1]);
16433 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16434 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16435 reg_names[12], reg_names[12]);
16436 assemble_name (file, buf);
16437 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16438 assemble_name (file, buf);
16439 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16440 }
16441 else if (flag_pic == 1)
16442 {
16443 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16444 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16445 reg_names[0], reg_names[1]);
16446 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16447 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16448 assemble_name (file, buf);
16449 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16450 }
16451 else if (flag_pic > 1)
16452 {
16453 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16454 reg_names[0], reg_names[1]);
16455 /* Now, we need to get the address of the label. */
16456 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16457 assemble_name (file, buf);
16458 fputs ("-.\n1:", file);
16459 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16460 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16461 reg_names[0], reg_names[11]);
16462 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16463 reg_names[0], reg_names[0], reg_names[11]);
16464 }
16465 else
16466 {
16467 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16468 assemble_name (file, buf);
16469 fputs ("@ha\n", file);
16470 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16471 reg_names[0], reg_names[1]);
16472 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16473 assemble_name (file, buf);
16474 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16475 }
16476
16477 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16478 fprintf (file, "\tbl %s%s\n",
16479 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16480 break;
16481
16482 case ABI_AIX:
16483 case ABI_DARWIN:
16484 if (!TARGET_PROFILE_KERNEL)
16485 {
16486 /* Don't do anything, done in output_profile_hook (). */
16487 }
16488 else
16489 {
16490 gcc_assert (!TARGET_32BIT);
16491
16492 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16493 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16494
16495 if (cfun->static_chain_decl != NULL)
16496 {
16497 asm_fprintf (file, "\tstd %s,24(%s)\n",
16498 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16499 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16500 asm_fprintf (file, "\tld %s,24(%s)\n",
16501 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16502 }
16503 else
16504 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16505 }
16506 break;
16507 }
16508 }
16509
16510
16511 /* Power4 load update and store update instructions are cracked into a
16512 load or store and an integer insn which are executed in the same cycle.
16513 Branches have their own dispatch slot which does not count against the
16514 GCC issue rate, but it changes the program flow so there are no other
16515 instructions to issue in this cycle. */
16516
16517 static int
rs6000_variable_issue(FILE * stream ATTRIBUTE_UNUSED,int verbose ATTRIBUTE_UNUSED,rtx insn,int more)16518 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16519 int verbose ATTRIBUTE_UNUSED,
16520 rtx insn, int more)
16521 {
16522 if (GET_CODE (PATTERN (insn)) == USE
16523 || GET_CODE (PATTERN (insn)) == CLOBBER)
16524 return more;
16525
16526 if (rs6000_sched_groups)
16527 {
16528 if (is_microcoded_insn (insn))
16529 return 0;
16530 else if (is_cracked_insn (insn))
16531 return more > 2 ? more - 2 : 0;
16532 }
16533
16534 return more - 1;
16535 }
16536
16537 /* Adjust the cost of a scheduling dependency. Return the new cost of
16538 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16539
16540 static int
rs6000_adjust_cost(rtx insn,rtx link,rtx dep_insn,int cost)16541 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16542 {
16543 if (! recog_memoized (insn))
16544 return 0;
16545
16546 if (REG_NOTE_KIND (link) != 0)
16547 return 0;
16548
16549 if (REG_NOTE_KIND (link) == 0)
16550 {
16551 /* Data dependency; DEP_INSN writes a register that INSN reads
16552 some cycles later. */
16553
16554 /* Separate a load from a narrower, dependent store. */
16555 if (rs6000_sched_groups
16556 && GET_CODE (PATTERN (insn)) == SET
16557 && GET_CODE (PATTERN (dep_insn)) == SET
16558 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16559 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16560 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16561 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16562 return cost + 14;
16563
16564 switch (get_attr_type (insn))
16565 {
16566 case TYPE_JMPREG:
16567 /* Tell the first scheduling pass about the latency between
16568 a mtctr and bctr (and mtlr and br/blr). The first
16569 scheduling pass will not know about this latency since
16570 the mtctr instruction, which has the latency associated
16571 to it, will be generated by reload. */
16572 return TARGET_POWER ? 5 : 4;
16573 case TYPE_BRANCH:
16574 /* Leave some extra cycles between a compare and its
16575 dependent branch, to inhibit expensive mispredicts. */
16576 if ((rs6000_cpu_attr == CPU_PPC603
16577 || rs6000_cpu_attr == CPU_PPC604
16578 || rs6000_cpu_attr == CPU_PPC604E
16579 || rs6000_cpu_attr == CPU_PPC620
16580 || rs6000_cpu_attr == CPU_PPC630
16581 || rs6000_cpu_attr == CPU_PPC750
16582 || rs6000_cpu_attr == CPU_PPC7400
16583 || rs6000_cpu_attr == CPU_PPC7450
16584 || rs6000_cpu_attr == CPU_POWER4
16585 || rs6000_cpu_attr == CPU_POWER5)
16586 && recog_memoized (dep_insn)
16587 && (INSN_CODE (dep_insn) >= 0)
16588 && (get_attr_type (dep_insn) == TYPE_CMP
16589 || get_attr_type (dep_insn) == TYPE_COMPARE
16590 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16591 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16592 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16593 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16594 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16595 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16596 return cost + 2;
16597 default:
16598 break;
16599 }
16600 /* Fall out to return default cost. */
16601 }
16602
16603 return cost;
16604 }
16605
16606 /* The function returns a true if INSN is microcoded.
16607 Return false otherwise. */
16608
16609 static bool
is_microcoded_insn(rtx insn)16610 is_microcoded_insn (rtx insn)
16611 {
16612 if (!insn || !INSN_P (insn)
16613 || GET_CODE (PATTERN (insn)) == USE
16614 || GET_CODE (PATTERN (insn)) == CLOBBER)
16615 return false;
16616
16617 if (rs6000_sched_groups)
16618 {
16619 enum attr_type type = get_attr_type (insn);
16620 if (type == TYPE_LOAD_EXT_U
16621 || type == TYPE_LOAD_EXT_UX
16622 || type == TYPE_LOAD_UX
16623 || type == TYPE_STORE_UX
16624 || type == TYPE_MFCR)
16625 return true;
16626 }
16627
16628 return false;
16629 }
16630
16631 /* The function returns a nonzero value if INSN can be scheduled only
16632 as the first insn in a dispatch group ("dispatch-slot restricted").
16633 In this case, the returned value indicates how many dispatch slots
16634 the insn occupies (at the beginning of the group).
16635 Return 0 otherwise. */
16636
16637 static int
is_dispatch_slot_restricted(rtx insn)16638 is_dispatch_slot_restricted (rtx insn)
16639 {
16640 enum attr_type type;
16641
16642 if (!rs6000_sched_groups)
16643 return 0;
16644
16645 if (!insn
16646 || insn == NULL_RTX
16647 || GET_CODE (insn) == NOTE
16648 || GET_CODE (PATTERN (insn)) == USE
16649 || GET_CODE (PATTERN (insn)) == CLOBBER)
16650 return 0;
16651
16652 type = get_attr_type (insn);
16653
16654 switch (type)
16655 {
16656 case TYPE_MFCR:
16657 case TYPE_MFCRF:
16658 case TYPE_MTCR:
16659 case TYPE_DELAYED_CR:
16660 case TYPE_CR_LOGICAL:
16661 case TYPE_MTJMPR:
16662 case TYPE_MFJMPR:
16663 return 1;
16664 case TYPE_IDIV:
16665 case TYPE_LDIV:
16666 return 2;
16667 case TYPE_LOAD_L:
16668 case TYPE_STORE_C:
16669 case TYPE_ISYNC:
16670 case TYPE_SYNC:
16671 return 4;
16672 default:
16673 if (rs6000_cpu == PROCESSOR_POWER5
16674 && is_cracked_insn (insn))
16675 return 2;
16676 return 0;
16677 }
16678 }
16679
16680 /* The function returns true if INSN is cracked into 2 instructions
16681 by the processor (and therefore occupies 2 issue slots). */
16682
16683 static bool
is_cracked_insn(rtx insn)16684 is_cracked_insn (rtx insn)
16685 {
16686 if (!insn || !INSN_P (insn)
16687 || GET_CODE (PATTERN (insn)) == USE
16688 || GET_CODE (PATTERN (insn)) == CLOBBER)
16689 return false;
16690
16691 if (rs6000_sched_groups)
16692 {
16693 enum attr_type type = get_attr_type (insn);
16694 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16695 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16696 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16697 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16698 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16699 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16700 || type == TYPE_IDIV || type == TYPE_LDIV
16701 || type == TYPE_INSERT_WORD)
16702 return true;
16703 }
16704
16705 return false;
16706 }
16707
16708 /* The function returns true if INSN can be issued only from
16709 the branch slot. */
16710
16711 static bool
is_branch_slot_insn(rtx insn)16712 is_branch_slot_insn (rtx insn)
16713 {
16714 if (!insn || !INSN_P (insn)
16715 || GET_CODE (PATTERN (insn)) == USE
16716 || GET_CODE (PATTERN (insn)) == CLOBBER)
16717 return false;
16718
16719 if (rs6000_sched_groups)
16720 {
16721 enum attr_type type = get_attr_type (insn);
16722 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16723 return true;
16724 return false;
16725 }
16726
16727 return false;
16728 }
16729
16730 /* A C statement (sans semicolon) to update the integer scheduling
16731 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16732 INSN earlier, reduce the priority to execute INSN later. Do not
16733 define this macro if you do not need to adjust the scheduling
16734 priorities of insns. */
16735
16736 static int
rs6000_adjust_priority(rtx insn ATTRIBUTE_UNUSED,int priority)16737 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16738 {
16739 /* On machines (like the 750) which have asymmetric integer units,
16740 where one integer unit can do multiply and divides and the other
16741 can't, reduce the priority of multiply/divide so it is scheduled
16742 before other integer operations. */
16743
16744 #if 0
16745 if (! INSN_P (insn))
16746 return priority;
16747
16748 if (GET_CODE (PATTERN (insn)) == USE)
16749 return priority;
16750
16751 switch (rs6000_cpu_attr) {
16752 case CPU_PPC750:
16753 switch (get_attr_type (insn))
16754 {
16755 default:
16756 break;
16757
16758 case TYPE_IMUL:
16759 case TYPE_IDIV:
16760 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16761 priority, priority);
16762 if (priority >= 0 && priority < 0x01000000)
16763 priority >>= 3;
16764 break;
16765 }
16766 }
16767 #endif
16768
16769 if (is_dispatch_slot_restricted (insn)
16770 && reload_completed
16771 && current_sched_info->sched_max_insns_priority
16772 && rs6000_sched_restricted_insns_priority)
16773 {
16774
16775 /* Prioritize insns that can be dispatched only in the first
16776 dispatch slot. */
16777 if (rs6000_sched_restricted_insns_priority == 1)
16778 /* Attach highest priority to insn. This means that in
16779 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16780 precede 'priority' (critical path) considerations. */
16781 return current_sched_info->sched_max_insns_priority;
16782 else if (rs6000_sched_restricted_insns_priority == 2)
16783 /* Increase priority of insn by a minimal amount. This means that in
16784 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16785 considerations precede dispatch-slot restriction considerations. */
16786 return (priority + 1);
16787 }
16788
16789 return priority;
16790 }
16791
16792 /* Return how many instructions the machine can issue per cycle. */
16793
16794 static int
rs6000_issue_rate(void)16795 rs6000_issue_rate (void)
16796 {
16797 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16798 if (!reload_completed)
16799 return 1;
16800
16801 switch (rs6000_cpu_attr) {
16802 case CPU_RIOS1: /* ? */
16803 case CPU_RS64A:
16804 case CPU_PPC601: /* ? */
16805 case CPU_PPC7450:
16806 return 3;
16807 case CPU_PPC440:
16808 case CPU_PPC603:
16809 case CPU_PPC750:
16810 case CPU_PPC7400:
16811 case CPU_PPC8540:
16812 return 2;
16813 case CPU_RIOS2:
16814 case CPU_PPC604:
16815 case CPU_PPC604E:
16816 case CPU_PPC620:
16817 case CPU_PPC630:
16818 return 4;
16819 case CPU_POWER4:
16820 case CPU_POWER5:
16821 return 5;
16822 default:
16823 return 1;
16824 }
16825 }
16826
16827 /* Return how many instructions to look ahead for better insn
16828 scheduling. */
16829
16830 static int
rs6000_use_sched_lookahead(void)16831 rs6000_use_sched_lookahead (void)
16832 {
16833 if (rs6000_cpu_attr == CPU_PPC8540)
16834 return 4;
16835 return 0;
16836 }
16837
16838 /* Determine is PAT refers to memory. */
16839
16840 static bool
is_mem_ref(rtx pat)16841 is_mem_ref (rtx pat)
16842 {
16843 const char * fmt;
16844 int i, j;
16845 bool ret = false;
16846
16847 if (GET_CODE (pat) == MEM)
16848 return true;
16849
16850 /* Recursively process the pattern. */
16851 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16852
16853 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16854 {
16855 if (fmt[i] == 'e')
16856 ret |= is_mem_ref (XEXP (pat, i));
16857 else if (fmt[i] == 'E')
16858 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16859 ret |= is_mem_ref (XVECEXP (pat, i, j));
16860 }
16861
16862 return ret;
16863 }
16864
16865 /* Determine if PAT is a PATTERN of a load insn. */
16866
16867 static bool
is_load_insn1(rtx pat)16868 is_load_insn1 (rtx pat)
16869 {
16870 if (!pat || pat == NULL_RTX)
16871 return false;
16872
16873 if (GET_CODE (pat) == SET)
16874 return is_mem_ref (SET_SRC (pat));
16875
16876 if (GET_CODE (pat) == PARALLEL)
16877 {
16878 int i;
16879
16880 for (i = 0; i < XVECLEN (pat, 0); i++)
16881 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16882 return true;
16883 }
16884
16885 return false;
16886 }
16887
16888 /* Determine if INSN loads from memory. */
16889
16890 static bool
is_load_insn(rtx insn)16891 is_load_insn (rtx insn)
16892 {
16893 if (!insn || !INSN_P (insn))
16894 return false;
16895
16896 if (GET_CODE (insn) == CALL_INSN)
16897 return false;
16898
16899 return is_load_insn1 (PATTERN (insn));
16900 }
16901
16902 /* Determine if PAT is a PATTERN of a store insn. */
16903
16904 static bool
is_store_insn1(rtx pat)16905 is_store_insn1 (rtx pat)
16906 {
16907 if (!pat || pat == NULL_RTX)
16908 return false;
16909
16910 if (GET_CODE (pat) == SET)
16911 return is_mem_ref (SET_DEST (pat));
16912
16913 if (GET_CODE (pat) == PARALLEL)
16914 {
16915 int i;
16916
16917 for (i = 0; i < XVECLEN (pat, 0); i++)
16918 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16919 return true;
16920 }
16921
16922 return false;
16923 }
16924
16925 /* Determine if INSN stores to memory. */
16926
16927 static bool
is_store_insn(rtx insn)16928 is_store_insn (rtx insn)
16929 {
16930 if (!insn || !INSN_P (insn))
16931 return false;
16932
16933 return is_store_insn1 (PATTERN (insn));
16934 }
16935
16936 /* Returns whether the dependence between INSN and NEXT is considered
16937 costly by the given target. */
16938
16939 static bool
rs6000_is_costly_dependence(rtx insn,rtx next,rtx link,int cost,int distance)16940 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16941 int distance)
16942 {
16943 /* If the flag is not enabled - no dependence is considered costly;
16944 allow all dependent insns in the same group.
16945 This is the most aggressive option. */
16946 if (rs6000_sched_costly_dep == no_dep_costly)
16947 return false;
16948
16949 /* If the flag is set to 1 - a dependence is always considered costly;
16950 do not allow dependent instructions in the same group.
16951 This is the most conservative option. */
16952 if (rs6000_sched_costly_dep == all_deps_costly)
16953 return true;
16954
16955 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16956 && is_load_insn (next)
16957 && is_store_insn (insn))
16958 /* Prevent load after store in the same group. */
16959 return true;
16960
16961 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16962 && is_load_insn (next)
16963 && is_store_insn (insn)
16964 && (!link || (int) REG_NOTE_KIND (link) == 0))
16965 /* Prevent load after store in the same group if it is a true
16966 dependence. */
16967 return true;
16968
16969 /* The flag is set to X; dependences with latency >= X are considered costly,
16970 and will not be scheduled in the same group. */
16971 if (rs6000_sched_costly_dep <= max_dep_latency
16972 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16973 return true;
16974
16975 return false;
16976 }
16977
16978 /* Return the next insn after INSN that is found before TAIL is reached,
16979 skipping any "non-active" insns - insns that will not actually occupy
16980 an issue slot. Return NULL_RTX if such an insn is not found. */
16981
16982 static rtx
get_next_active_insn(rtx insn,rtx tail)16983 get_next_active_insn (rtx insn, rtx tail)
16984 {
16985 if (insn == NULL_RTX || insn == tail)
16986 return NULL_RTX;
16987
16988 while (1)
16989 {
16990 insn = NEXT_INSN (insn);
16991 if (insn == NULL_RTX || insn == tail)
16992 return NULL_RTX;
16993
16994 if (CALL_P (insn)
16995 || JUMP_P (insn)
16996 || (NONJUMP_INSN_P (insn)
16997 && GET_CODE (PATTERN (insn)) != USE
16998 && GET_CODE (PATTERN (insn)) != CLOBBER
16999 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17000 break;
17001 }
17002 return insn;
17003 }
17004
17005 /* Return whether the presence of INSN causes a dispatch group termination
17006 of group WHICH_GROUP.
17007
17008 If WHICH_GROUP == current_group, this function will return true if INSN
17009 causes the termination of the current group (i.e, the dispatch group to
17010 which INSN belongs). This means that INSN will be the last insn in the
17011 group it belongs to.
17012
17013 If WHICH_GROUP == previous_group, this function will return true if INSN
17014 causes the termination of the previous group (i.e, the dispatch group that
17015 precedes the group to which INSN belongs). This means that INSN will be
17016 the first insn in the group it belongs to). */
17017
17018 static bool
insn_terminates_group_p(rtx insn,enum group_termination which_group)17019 insn_terminates_group_p (rtx insn, enum group_termination which_group)
17020 {
17021 enum attr_type type;
17022
17023 if (! insn)
17024 return false;
17025
17026 type = get_attr_type (insn);
17027
17028 if (is_microcoded_insn (insn))
17029 return true;
17030
17031 if (which_group == current_group)
17032 {
17033 if (is_branch_slot_insn (insn))
17034 return true;
17035 return false;
17036 }
17037 else if (which_group == previous_group)
17038 {
17039 if (is_dispatch_slot_restricted (insn))
17040 return true;
17041 return false;
17042 }
17043
17044 return false;
17045 }
17046
17047 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
17048 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
17049
17050 static bool
is_costly_group(rtx * group_insns,rtx next_insn)17051 is_costly_group (rtx *group_insns, rtx next_insn)
17052 {
17053 int i;
17054 rtx link;
17055 int cost;
17056 int issue_rate = rs6000_issue_rate ();
17057
17058 for (i = 0; i < issue_rate; i++)
17059 {
17060 rtx insn = group_insns[i];
17061 if (!insn)
17062 continue;
17063 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
17064 {
17065 rtx next = XEXP (link, 0);
17066 if (next == next_insn)
17067 {
17068 cost = insn_cost (insn, link, next_insn);
17069 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
17070 return true;
17071 }
17072 }
17073 }
17074
17075 return false;
17076 }
17077
17078 /* Utility of the function redefine_groups.
17079 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
17080 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
17081 to keep it "far" (in a separate group) from GROUP_INSNS, following
17082 one of the following schemes, depending on the value of the flag
17083 -minsert_sched_nops = X:
17084 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
17085 in order to force NEXT_INSN into a separate group.
17086 (2) X < sched_finish_regroup_exact: insert exactly X nops.
17087 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
17088 insertion (has a group just ended, how many vacant issue slots remain in the
17089 last group, and how many dispatch groups were encountered so far). */
17090
17091 static int
force_new_group(int sched_verbose,FILE * dump,rtx * group_insns,rtx next_insn,bool * group_end,int can_issue_more,int * group_count)17092 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
17093 rtx next_insn, bool *group_end, int can_issue_more,
17094 int *group_count)
17095 {
17096 rtx nop;
17097 bool force;
17098 int issue_rate = rs6000_issue_rate ();
17099 bool end = *group_end;
17100 int i;
17101
17102 if (next_insn == NULL_RTX)
17103 return can_issue_more;
17104
17105 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
17106 return can_issue_more;
17107
17108 force = is_costly_group (group_insns, next_insn);
17109 if (!force)
17110 return can_issue_more;
17111
17112 if (sched_verbose > 6)
17113 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
17114 *group_count ,can_issue_more);
17115
17116 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
17117 {
17118 if (*group_end)
17119 can_issue_more = 0;
17120
17121 /* Since only a branch can be issued in the last issue_slot, it is
17122 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
17123 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
17124 in this case the last nop will start a new group and the branch
17125 will be forced to the new group. */
17126 if (can_issue_more && !is_branch_slot_insn (next_insn))
17127 can_issue_more--;
17128
17129 while (can_issue_more > 0)
17130 {
17131 nop = gen_nop ();
17132 emit_insn_before (nop, next_insn);
17133 can_issue_more--;
17134 }
17135
17136 *group_end = true;
17137 return 0;
17138 }
17139
17140 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
17141 {
17142 int n_nops = rs6000_sched_insert_nops;
17143
17144 /* Nops can't be issued from the branch slot, so the effective
17145 issue_rate for nops is 'issue_rate - 1'. */
17146 if (can_issue_more == 0)
17147 can_issue_more = issue_rate;
17148 can_issue_more--;
17149 if (can_issue_more == 0)
17150 {
17151 can_issue_more = issue_rate - 1;
17152 (*group_count)++;
17153 end = true;
17154 for (i = 0; i < issue_rate; i++)
17155 {
17156 group_insns[i] = 0;
17157 }
17158 }
17159
17160 while (n_nops > 0)
17161 {
17162 nop = gen_nop ();
17163 emit_insn_before (nop, next_insn);
17164 if (can_issue_more == issue_rate - 1) /* new group begins */
17165 end = false;
17166 can_issue_more--;
17167 if (can_issue_more == 0)
17168 {
17169 can_issue_more = issue_rate - 1;
17170 (*group_count)++;
17171 end = true;
17172 for (i = 0; i < issue_rate; i++)
17173 {
17174 group_insns[i] = 0;
17175 }
17176 }
17177 n_nops--;
17178 }
17179
17180 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
17181 can_issue_more++;
17182
17183 /* Is next_insn going to start a new group? */
17184 *group_end
17185 = (end
17186 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17187 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17188 || (can_issue_more < issue_rate &&
17189 insn_terminates_group_p (next_insn, previous_group)));
17190 if (*group_end && end)
17191 (*group_count)--;
17192
17193 if (sched_verbose > 6)
17194 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
17195 *group_count, can_issue_more);
17196 return can_issue_more;
17197 }
17198
17199 return can_issue_more;
17200 }
17201
17202 /* This function tries to synch the dispatch groups that the compiler "sees"
17203 with the dispatch groups that the processor dispatcher is expected to
17204 form in practice. It tries to achieve this synchronization by forcing the
17205 estimated processor grouping on the compiler (as opposed to the function
17206 'pad_goups' which tries to force the scheduler's grouping on the processor).
17207
17208 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
17209 examines the (estimated) dispatch groups that will be formed by the processor
17210 dispatcher. It marks these group boundaries to reflect the estimated
17211 processor grouping, overriding the grouping that the scheduler had marked.
17212 Depending on the value of the flag '-minsert-sched-nops' this function can
17213 force certain insns into separate groups or force a certain distance between
17214 them by inserting nops, for example, if there exists a "costly dependence"
17215 between the insns.
17216
17217 The function estimates the group boundaries that the processor will form as
17218 follows: It keeps track of how many vacant issue slots are available after
17219 each insn. A subsequent insn will start a new group if one of the following
17220 4 cases applies:
17221 - no more vacant issue slots remain in the current dispatch group.
17222 - only the last issue slot, which is the branch slot, is vacant, but the next
17223 insn is not a branch.
17224 - only the last 2 or less issue slots, including the branch slot, are vacant,
17225 which means that a cracked insn (which occupies two issue slots) can't be
17226 issued in this group.
17227 - less than 'issue_rate' slots are vacant, and the next insn always needs to
17228 start a new group. */
17229
17230 static int
redefine_groups(FILE * dump,int sched_verbose,rtx prev_head_insn,rtx tail)17231 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17232 {
17233 rtx insn, next_insn;
17234 int issue_rate;
17235 int can_issue_more;
17236 int slot, i;
17237 bool group_end;
17238 int group_count = 0;
17239 rtx *group_insns;
17240
17241 /* Initialize. */
17242 issue_rate = rs6000_issue_rate ();
17243 group_insns = alloca (issue_rate * sizeof (rtx));
17244 for (i = 0; i < issue_rate; i++)
17245 {
17246 group_insns[i] = 0;
17247 }
17248 can_issue_more = issue_rate;
17249 slot = 0;
17250 insn = get_next_active_insn (prev_head_insn, tail);
17251 group_end = false;
17252
17253 while (insn != NULL_RTX)
17254 {
17255 slot = (issue_rate - can_issue_more);
17256 group_insns[slot] = insn;
17257 can_issue_more =
17258 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17259 if (insn_terminates_group_p (insn, current_group))
17260 can_issue_more = 0;
17261
17262 next_insn = get_next_active_insn (insn, tail);
17263 if (next_insn == NULL_RTX)
17264 return group_count + 1;
17265
17266 /* Is next_insn going to start a new group? */
17267 group_end
17268 = (can_issue_more == 0
17269 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17270 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17271 || (can_issue_more < issue_rate &&
17272 insn_terminates_group_p (next_insn, previous_group)));
17273
17274 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
17275 next_insn, &group_end, can_issue_more,
17276 &group_count);
17277
17278 if (group_end)
17279 {
17280 group_count++;
17281 can_issue_more = 0;
17282 for (i = 0; i < issue_rate; i++)
17283 {
17284 group_insns[i] = 0;
17285 }
17286 }
17287
17288 if (GET_MODE (next_insn) == TImode && can_issue_more)
17289 PUT_MODE (next_insn, VOIDmode);
17290 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
17291 PUT_MODE (next_insn, TImode);
17292
17293 insn = next_insn;
17294 if (can_issue_more == 0)
17295 can_issue_more = issue_rate;
17296 } /* while */
17297
17298 return group_count;
17299 }
17300
17301 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
17302 dispatch group boundaries that the scheduler had marked. Pad with nops
17303 any dispatch groups which have vacant issue slots, in order to force the
17304 scheduler's grouping on the processor dispatcher. The function
17305 returns the number of dispatch groups found. */
17306
17307 static int
pad_groups(FILE * dump,int sched_verbose,rtx prev_head_insn,rtx tail)17308 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17309 {
17310 rtx insn, next_insn;
17311 rtx nop;
17312 int issue_rate;
17313 int can_issue_more;
17314 int group_end;
17315 int group_count = 0;
17316
17317 /* Initialize issue_rate. */
17318 issue_rate = rs6000_issue_rate ();
17319 can_issue_more = issue_rate;
17320
17321 insn = get_next_active_insn (prev_head_insn, tail);
17322 next_insn = get_next_active_insn (insn, tail);
17323
17324 while (insn != NULL_RTX)
17325 {
17326 can_issue_more =
17327 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17328
17329 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17330
17331 if (next_insn == NULL_RTX)
17332 break;
17333
17334 if (group_end)
17335 {
17336 /* If the scheduler had marked group termination at this location
17337 (between insn and next_indn), and neither insn nor next_insn will
17338 force group termination, pad the group with nops to force group
17339 termination. */
17340 if (can_issue_more
17341 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17342 && !insn_terminates_group_p (insn, current_group)
17343 && !insn_terminates_group_p (next_insn, previous_group))
17344 {
17345 if (!is_branch_slot_insn (next_insn))
17346 can_issue_more--;
17347
17348 while (can_issue_more)
17349 {
17350 nop = gen_nop ();
17351 emit_insn_before (nop, next_insn);
17352 can_issue_more--;
17353 }
17354 }
17355
17356 can_issue_more = issue_rate;
17357 group_count++;
17358 }
17359
17360 insn = next_insn;
17361 next_insn = get_next_active_insn (insn, tail);
17362 }
17363
17364 return group_count;
17365 }
17366
17367 /* The following function is called at the end of scheduling BB.
17368 After reload, it inserts nops at insn group bundling. */
17369
17370 static void
rs6000_sched_finish(FILE * dump,int sched_verbose)17371 rs6000_sched_finish (FILE *dump, int sched_verbose)
17372 {
17373 int n_groups;
17374
17375 if (sched_verbose)
17376 fprintf (dump, "=== Finishing schedule.\n");
17377
17378 if (reload_completed && rs6000_sched_groups)
17379 {
17380 if (rs6000_sched_insert_nops == sched_finish_none)
17381 return;
17382
17383 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17384 n_groups = pad_groups (dump, sched_verbose,
17385 current_sched_info->prev_head,
17386 current_sched_info->next_tail);
17387 else
17388 n_groups = redefine_groups (dump, sched_verbose,
17389 current_sched_info->prev_head,
17390 current_sched_info->next_tail);
17391
17392 if (sched_verbose >= 6)
17393 {
17394 fprintf (dump, "ngroups = %d\n", n_groups);
17395 print_rtl (dump, current_sched_info->prev_head);
17396 fprintf (dump, "Done finish_sched\n");
17397 }
17398 }
17399 }
17400
17401 /* Length in units of the trampoline for entering a nested function. */
17402
17403 int
rs6000_trampoline_size(void)17404 rs6000_trampoline_size (void)
17405 {
17406 int ret = 0;
17407
17408 switch (DEFAULT_ABI)
17409 {
17410 default:
17411 gcc_unreachable ();
17412
17413 case ABI_AIX:
17414 ret = (TARGET_32BIT) ? 12 : 24;
17415 break;
17416
17417 case ABI_DARWIN:
17418 case ABI_V4:
17419 ret = (TARGET_32BIT) ? 40 : 48;
17420 break;
17421 }
17422
17423 return ret;
17424 }
17425
17426 /* Emit RTL insns to initialize the variable parts of a trampoline.
17427 FNADDR is an RTX for the address of the function's pure code.
17428 CXT is an RTX for the static chain value for the function. */
17429
17430 void
rs6000_initialize_trampoline(rtx addr,rtx fnaddr,rtx cxt)17431 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17432 {
17433 int regsize = (TARGET_32BIT) ? 4 : 8;
17434 rtx ctx_reg = force_reg (Pmode, cxt);
17435
17436 switch (DEFAULT_ABI)
17437 {
17438 default:
17439 gcc_unreachable ();
17440
17441 /* Macros to shorten the code expansions below. */
17442 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
17443 #define MEM_PLUS(addr,offset) \
17444 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
17445
17446 /* Under AIX, just build the 3 word function descriptor */
17447 case ABI_AIX:
17448 {
17449 rtx fn_reg = gen_reg_rtx (Pmode);
17450 rtx toc_reg = gen_reg_rtx (Pmode);
17451 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17452 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17453 emit_move_insn (MEM_DEREF (addr), fn_reg);
17454 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17455 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17456 }
17457 break;
17458
17459 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17460 case ABI_DARWIN:
17461 case ABI_V4:
17462 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
17463 FALSE, VOIDmode, 4,
17464 addr, Pmode,
17465 GEN_INT (rs6000_trampoline_size ()), SImode,
17466 fnaddr, Pmode,
17467 ctx_reg, Pmode);
17468 break;
17469 }
17470
17471 return;
17472 }
17473
17474
17475 /* Table of valid machine attributes. */
17476
17477 const struct attribute_spec rs6000_attribute_table[] =
17478 {
17479 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17480 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17481 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17482 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17483 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
17484 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
17485 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17486 SUBTARGET_ATTRIBUTE_TABLE,
17487 #endif
17488 { NULL, 0, 0, false, false, false, NULL }
17489 };
17490
17491 /* Handle the "altivec" attribute. The attribute may have
17492 arguments as follows:
17493
17494 __attribute__((altivec(vector__)))
17495 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17496 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17497
17498 and may appear more than once (e.g., 'vector bool char') in a
17499 given declaration. */
17500
17501 static tree
rs6000_handle_altivec_attribute(tree * node,tree name ATTRIBUTE_UNUSED,tree args,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)17502 rs6000_handle_altivec_attribute (tree *node,
17503 tree name ATTRIBUTE_UNUSED,
17504 tree args,
17505 int flags ATTRIBUTE_UNUSED,
17506 bool *no_add_attrs)
17507 {
17508 tree type = *node, result = NULL_TREE;
17509 enum machine_mode mode;
17510 int unsigned_p;
17511 char altivec_type
17512 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17513 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17514 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17515 : '?');
17516
17517 while (POINTER_TYPE_P (type)
17518 || TREE_CODE (type) == FUNCTION_TYPE
17519 || TREE_CODE (type) == METHOD_TYPE
17520 || TREE_CODE (type) == ARRAY_TYPE)
17521 type = TREE_TYPE (type);
17522
17523 mode = TYPE_MODE (type);
17524
17525 /* Check for invalid AltiVec type qualifiers. */
17526 if (type == long_unsigned_type_node || type == long_integer_type_node)
17527 {
17528 if (TARGET_64BIT)
17529 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17530 else if (rs6000_warn_altivec_long)
17531 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17532 }
17533 else if (type == long_long_unsigned_type_node
17534 || type == long_long_integer_type_node)
17535 error ("use of %<long long%> in AltiVec types is invalid");
17536 else if (type == double_type_node)
17537 error ("use of %<double%> in AltiVec types is invalid");
17538 else if (type == long_double_type_node)
17539 error ("use of %<long double%> in AltiVec types is invalid");
17540 else if (type == boolean_type_node)
17541 error ("use of boolean types in AltiVec types is invalid");
17542 else if (TREE_CODE (type) == COMPLEX_TYPE)
17543 error ("use of %<complex%> in AltiVec types is invalid");
17544 else if (DECIMAL_FLOAT_MODE_P (mode))
17545 error ("use of decimal floating point types in AltiVec types is invalid");
17546
17547 switch (altivec_type)
17548 {
17549 case 'v':
17550 unsigned_p = TYPE_UNSIGNED (type);
17551 switch (mode)
17552 {
17553 case SImode:
17554 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17555 break;
17556 case HImode:
17557 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17558 break;
17559 case QImode:
17560 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17561 break;
17562 case SFmode: result = V4SF_type_node; break;
17563 /* If the user says 'vector int bool', we may be handed the 'bool'
17564 attribute _before_ the 'vector' attribute, and so select the
17565 proper type in the 'b' case below. */
17566 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17567 result = type;
17568 default: break;
17569 }
17570 break;
17571 case 'b':
17572 switch (mode)
17573 {
17574 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17575 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17576 case QImode: case V16QImode: result = bool_V16QI_type_node;
17577 default: break;
17578 }
17579 break;
17580 case 'p':
17581 switch (mode)
17582 {
17583 case V8HImode: result = pixel_V8HI_type_node;
17584 default: break;
17585 }
17586 default: break;
17587 }
17588
17589 if (result && result != type && TYPE_READONLY (type))
17590 result = build_qualified_type (result, TYPE_QUAL_CONST);
17591
17592 *no_add_attrs = true; /* No need to hang on to the attribute. */
17593
17594 if (result)
17595 *node = reconstruct_complex_type (*node, result);
17596
17597 return NULL_TREE;
17598 }
17599
17600 /* AltiVec defines four built-in scalar types that serve as vector
17601 elements; we must teach the compiler how to mangle them. */
17602
17603 static const char *
rs6000_mangle_fundamental_type(tree type)17604 rs6000_mangle_fundamental_type (tree type)
17605 {
17606 if (type == bool_char_type_node) return "U6__boolc";
17607 if (type == bool_short_type_node) return "U6__bools";
17608 if (type == pixel_type_node) return "u7__pixel";
17609 if (type == bool_int_type_node) return "U6__booli";
17610
17611 /* Mangle IBM extended float long double as `g' (__float128) on
17612 powerpc*-linux where long-double-64 previously was the default. */
17613 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
17614 && TARGET_ELF
17615 && TARGET_LONG_DOUBLE_128
17616 && !TARGET_IEEEQUAD)
17617 return "g";
17618
17619 /* For all other types, use normal C++ mangling. */
17620 return NULL;
17621 }
17622
17623 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17624 struct attribute_spec.handler. */
17625
17626 static tree
rs6000_handle_longcall_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)17627 rs6000_handle_longcall_attribute (tree *node, tree name,
17628 tree args ATTRIBUTE_UNUSED,
17629 int flags ATTRIBUTE_UNUSED,
17630 bool *no_add_attrs)
17631 {
17632 if (TREE_CODE (*node) != FUNCTION_TYPE
17633 && TREE_CODE (*node) != FIELD_DECL
17634 && TREE_CODE (*node) != TYPE_DECL)
17635 {
17636 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17637 IDENTIFIER_POINTER (name));
17638 *no_add_attrs = true;
17639 }
17640
17641 return NULL_TREE;
17642 }
17643
17644 /* Set longcall attributes on all functions declared when
17645 rs6000_default_long_calls is true. */
17646 static void
rs6000_set_default_type_attributes(tree type)17647 rs6000_set_default_type_attributes (tree type)
17648 {
17649 if (rs6000_default_long_calls
17650 && (TREE_CODE (type) == FUNCTION_TYPE
17651 || TREE_CODE (type) == METHOD_TYPE))
17652 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17653 NULL_TREE,
17654 TYPE_ATTRIBUTES (type));
17655
17656 #if TARGET_MACHO
17657 darwin_set_default_type_attributes (type);
17658 #endif
17659 }
17660
17661 /* Return a reference suitable for calling a function with the
17662 longcall attribute. */
17663
17664 rtx
rs6000_longcall_ref(rtx call_ref)17665 rs6000_longcall_ref (rtx call_ref)
17666 {
17667 const char *call_name;
17668 tree node;
17669
17670 if (GET_CODE (call_ref) != SYMBOL_REF)
17671 return call_ref;
17672
17673 /* System V adds '.' to the internal name, so skip them. */
17674 call_name = XSTR (call_ref, 0);
17675 if (*call_name == '.')
17676 {
17677 while (*call_name == '.')
17678 call_name++;
17679
17680 node = get_identifier (call_name);
17681 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17682 }
17683
17684 return force_reg (Pmode, call_ref);
17685 }
17686
17687 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
17688 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
17689 #endif
17690
17691 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
17692 struct attribute_spec.handler. */
17693 static tree
rs6000_handle_struct_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)17694 rs6000_handle_struct_attribute (tree *node, tree name,
17695 tree args ATTRIBUTE_UNUSED,
17696 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
17697 {
17698 tree *type = NULL;
17699 if (DECL_P (*node))
17700 {
17701 if (TREE_CODE (*node) == TYPE_DECL)
17702 type = &TREE_TYPE (*node);
17703 }
17704 else
17705 type = node;
17706
17707 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
17708 || TREE_CODE (*type) == UNION_TYPE)))
17709 {
17710 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
17711 *no_add_attrs = true;
17712 }
17713
17714 else if ((is_attribute_p ("ms_struct", name)
17715 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
17716 || ((is_attribute_p ("gcc_struct", name)
17717 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
17718 {
17719 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
17720 IDENTIFIER_POINTER (name));
17721 *no_add_attrs = true;
17722 }
17723
17724 return NULL_TREE;
17725 }
17726
17727 static bool
rs6000_ms_bitfield_layout_p(tree record_type)17728 rs6000_ms_bitfield_layout_p (tree record_type)
17729 {
17730 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
17731 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
17732 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
17733 }
17734
17735 #ifdef USING_ELFOS_H
17736
17737 /* A get_unnamed_section callback, used for switching to toc_section. */
17738
17739 static void
rs6000_elf_output_toc_section_asm_op(const void * data ATTRIBUTE_UNUSED)17740 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17741 {
17742 if (DEFAULT_ABI == ABI_AIX
17743 && TARGET_MINIMAL_TOC
17744 && !TARGET_RELOCATABLE)
17745 {
17746 if (!toc_initialized)
17747 {
17748 toc_initialized = 1;
17749 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17750 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17751 fprintf (asm_out_file, "\t.tc ");
17752 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17753 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17754 fprintf (asm_out_file, "\n");
17755
17756 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17757 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17758 fprintf (asm_out_file, " = .+32768\n");
17759 }
17760 else
17761 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17762 }
17763 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17764 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17765 else
17766 {
17767 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17768 if (!toc_initialized)
17769 {
17770 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17771 fprintf (asm_out_file, " = .+32768\n");
17772 toc_initialized = 1;
17773 }
17774 }
17775 }
17776
17777 /* Implement TARGET_ASM_INIT_SECTIONS. */
17778
17779 static void
rs6000_elf_asm_init_sections(void)17780 rs6000_elf_asm_init_sections (void)
17781 {
17782 toc_section
17783 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17784
17785 sdata2_section
17786 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17787 SDATA2_SECTION_ASM_OP);
17788 }
17789
17790 /* Implement TARGET_SELECT_RTX_SECTION. */
17791
17792 static section *
rs6000_elf_select_rtx_section(enum machine_mode mode,rtx x,unsigned HOST_WIDE_INT align)17793 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17794 unsigned HOST_WIDE_INT align)
17795 {
17796 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17797 return toc_section;
17798 else
17799 return default_elf_select_rtx_section (mode, x, align);
17800 }
17801
17802 /* For a SYMBOL_REF, set generic flags and then perform some
17803 target-specific processing.
17804
17805 When the AIX ABI is requested on a non-AIX system, replace the
17806 function name with the real name (with a leading .) rather than the
17807 function descriptor name. This saves a lot of overriding code to
17808 read the prefixes. */
17809
17810 static void
rs6000_elf_encode_section_info(tree decl,rtx rtl,int first)17811 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17812 {
17813 default_encode_section_info (decl, rtl, first);
17814
17815 if (first
17816 && TREE_CODE (decl) == FUNCTION_DECL
17817 && !TARGET_AIX
17818 && DEFAULT_ABI == ABI_AIX)
17819 {
17820 rtx sym_ref = XEXP (rtl, 0);
17821 size_t len = strlen (XSTR (sym_ref, 0));
17822 char *str = alloca (len + 2);
17823 str[0] = '.';
17824 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17825 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17826 }
17827 }
17828
17829 bool
rs6000_elf_in_small_data_p(tree decl)17830 rs6000_elf_in_small_data_p (tree decl)
17831 {
17832 if (rs6000_sdata == SDATA_NONE)
17833 return false;
17834
17835 /* We want to merge strings, so we never consider them small data. */
17836 if (TREE_CODE (decl) == STRING_CST)
17837 return false;
17838
17839 /* Functions are never in the small data area. */
17840 if (TREE_CODE (decl) == FUNCTION_DECL)
17841 return false;
17842
17843 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17844 {
17845 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17846 if (strcmp (section, ".sdata") == 0
17847 || strcmp (section, ".sdata2") == 0
17848 || strcmp (section, ".sbss") == 0
17849 || strcmp (section, ".sbss2") == 0
17850 || strcmp (section, ".PPC.EMB.sdata0") == 0
17851 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17852 return true;
17853 }
17854 else
17855 {
17856 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17857
17858 if (size > 0
17859 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17860 /* If it's not public, and we're not going to reference it there,
17861 there's no need to put it in the small data section. */
17862 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17863 return true;
17864 }
17865
17866 return false;
17867 }
17868
17869 #endif /* USING_ELFOS_H */
17870
17871 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
17872
17873 static bool
rs6000_use_blocks_for_constant_p(enum machine_mode mode,rtx x)17874 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
17875 {
17876 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
17877 }
17878
17879 /* Return a REG that occurs in ADDR with coefficient 1.
17880 ADDR can be effectively incremented by incrementing REG.
17881
17882 r0 is special and we must not select it as an address
17883 register by this routine since our caller will try to
17884 increment the returned register via an "la" instruction. */
17885
17886 rtx
find_addr_reg(rtx addr)17887 find_addr_reg (rtx addr)
17888 {
17889 while (GET_CODE (addr) == PLUS)
17890 {
17891 if (GET_CODE (XEXP (addr, 0)) == REG
17892 && REGNO (XEXP (addr, 0)) != 0)
17893 addr = XEXP (addr, 0);
17894 else if (GET_CODE (XEXP (addr, 1)) == REG
17895 && REGNO (XEXP (addr, 1)) != 0)
17896 addr = XEXP (addr, 1);
17897 else if (CONSTANT_P (XEXP (addr, 0)))
17898 addr = XEXP (addr, 1);
17899 else if (CONSTANT_P (XEXP (addr, 1)))
17900 addr = XEXP (addr, 0);
17901 else
17902 gcc_unreachable ();
17903 }
17904 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17905 return addr;
17906 }
17907
17908 void
rs6000_fatal_bad_address(rtx op)17909 rs6000_fatal_bad_address (rtx op)
17910 {
17911 fatal_insn ("bad address", op);
17912 }
17913
17914 #if TARGET_MACHO
17915
17916 static tree branch_island_list = 0;
17917
17918 /* Remember to generate a branch island for far calls to the given
17919 function. */
17920
17921 static void
add_compiler_branch_island(tree label_name,tree function_name,int line_number)17922 add_compiler_branch_island (tree label_name, tree function_name,
17923 int line_number)
17924 {
17925 tree branch_island = build_tree_list (function_name, label_name);
17926 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17927 TREE_CHAIN (branch_island) = branch_island_list;
17928 branch_island_list = branch_island;
17929 }
17930
17931 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17932 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17933 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17934 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17935
17936 /* Generate far-jump branch islands for everything on the
17937 branch_island_list. Invoked immediately after the last instruction
17938 of the epilogue has been emitted; the branch-islands must be
17939 appended to, and contiguous with, the function body. Mach-O stubs
17940 are generated in machopic_output_stub(). */
17941
17942 static void
macho_branch_islands(void)17943 macho_branch_islands (void)
17944 {
17945 char tmp_buf[512];
17946 tree branch_island;
17947
17948 for (branch_island = branch_island_list;
17949 branch_island;
17950 branch_island = TREE_CHAIN (branch_island))
17951 {
17952 const char *label =
17953 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17954 const char *name =
17955 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17956 char name_buf[512];
17957 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17958 if (name[0] == '*' || name[0] == '&')
17959 strcpy (name_buf, name+1);
17960 else
17961 {
17962 name_buf[0] = '_';
17963 strcpy (name_buf+1, name);
17964 }
17965 strcpy (tmp_buf, "\n");
17966 strcat (tmp_buf, label);
17967 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17968 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17969 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17970 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17971 if (flag_pic)
17972 {
17973 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17974 strcat (tmp_buf, label);
17975 strcat (tmp_buf, "_pic\n");
17976 strcat (tmp_buf, label);
17977 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17978
17979 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17980 strcat (tmp_buf, name_buf);
17981 strcat (tmp_buf, " - ");
17982 strcat (tmp_buf, label);
17983 strcat (tmp_buf, "_pic)\n");
17984
17985 strcat (tmp_buf, "\tmtlr r0\n");
17986
17987 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17988 strcat (tmp_buf, name_buf);
17989 strcat (tmp_buf, " - ");
17990 strcat (tmp_buf, label);
17991 strcat (tmp_buf, "_pic)\n");
17992
17993 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17994 }
17995 else
17996 {
17997 strcat (tmp_buf, ":\nlis r12,hi16(");
17998 strcat (tmp_buf, name_buf);
17999 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
18000 strcat (tmp_buf, name_buf);
18001 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
18002 }
18003 output_asm_insn (tmp_buf, 0);
18004 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
18005 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
18006 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
18007 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
18008 }
18009
18010 branch_island_list = 0;
18011 }
18012
18013 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
18014 already there or not. */
18015
18016 static int
no_previous_def(tree function_name)18017 no_previous_def (tree function_name)
18018 {
18019 tree branch_island;
18020 for (branch_island = branch_island_list;
18021 branch_island;
18022 branch_island = TREE_CHAIN (branch_island))
18023 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
18024 return 0;
18025 return 1;
18026 }
18027
18028 /* GET_PREV_LABEL gets the label name from the previous definition of
18029 the function. */
18030
18031 static tree
get_prev_label(tree function_name)18032 get_prev_label (tree function_name)
18033 {
18034 tree branch_island;
18035 for (branch_island = branch_island_list;
18036 branch_island;
18037 branch_island = TREE_CHAIN (branch_island))
18038 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
18039 return BRANCH_ISLAND_LABEL_NAME (branch_island);
18040 return 0;
18041 }
18042
18043 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
18044 #define DARWIN_LINKER_GENERATES_ISLANDS 0
18045 #endif
18046
18047 /* KEXTs still need branch islands. */
18048 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
18049 || flag_mkernel || flag_apple_kext)
18050
18051 /* INSN is either a function call or a millicode call. It may have an
18052 unconditional jump in its delay slot.
18053
18054 CALL_DEST is the routine we are calling. */
18055
18056 char *
output_call(rtx insn,rtx * operands,int dest_operand_number,int cookie_operand_number)18057 output_call (rtx insn, rtx *operands, int dest_operand_number,
18058 int cookie_operand_number)
18059 {
18060 static char buf[256];
18061 if (DARWIN_GENERATE_ISLANDS
18062 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
18063 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
18064 {
18065 tree labelname;
18066 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
18067
18068 if (no_previous_def (funname))
18069 {
18070 int line_number = 0;
18071 rtx label_rtx = gen_label_rtx ();
18072 char *label_buf, temp_buf[256];
18073 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
18074 CODE_LABEL_NUMBER (label_rtx));
18075 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
18076 labelname = get_identifier (label_buf);
18077 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
18078 if (insn)
18079 line_number = NOTE_LINE_NUMBER (insn);
18080 add_compiler_branch_island (labelname, funname, line_number);
18081 }
18082 else
18083 labelname = get_prev_label (funname);
18084
18085 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
18086 instruction will reach 'foo', otherwise link as 'bl L42'".
18087 "L42" should be a 'branch island', that will do a far jump to
18088 'foo'. Branch islands are generated in
18089 macho_branch_islands(). */
18090 sprintf (buf, "jbsr %%z%d,%.246s",
18091 dest_operand_number, IDENTIFIER_POINTER (labelname));
18092 }
18093 else
18094 sprintf (buf, "bl %%z%d", dest_operand_number);
18095 return buf;
18096 }
18097
18098 /* Generate PIC and indirect symbol stubs. */
18099
18100 void
machopic_output_stub(FILE * file,const char * symb,const char * stub)18101 machopic_output_stub (FILE *file, const char *symb, const char *stub)
18102 {
18103 unsigned int length;
18104 char *symbol_name, *lazy_ptr_name;
18105 char *local_label_0;
18106 static int label = 0;
18107
18108 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
18109 symb = (*targetm.strip_name_encoding) (symb);
18110
18111
18112 length = strlen (symb);
18113 symbol_name = alloca (length + 32);
18114 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
18115
18116 lazy_ptr_name = alloca (length + 32);
18117 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
18118
18119 if (flag_pic == 2)
18120 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
18121 else
18122 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
18123
18124 if (flag_pic == 2)
18125 {
18126 fprintf (file, "\t.align 5\n");
18127
18128 fprintf (file, "%s:\n", stub);
18129 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18130
18131 label++;
18132 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
18133 sprintf (local_label_0, "\"L%011d$spb\"", label);
18134
18135 fprintf (file, "\tmflr r0\n");
18136 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
18137 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
18138 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
18139 lazy_ptr_name, local_label_0);
18140 fprintf (file, "\tmtlr r0\n");
18141 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
18142 (TARGET_64BIT ? "ldu" : "lwzu"),
18143 lazy_ptr_name, local_label_0);
18144 fprintf (file, "\tmtctr r12\n");
18145 fprintf (file, "\tbctr\n");
18146 }
18147 else
18148 {
18149 fprintf (file, "\t.align 4\n");
18150
18151 fprintf (file, "%s:\n", stub);
18152 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18153
18154 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
18155 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
18156 (TARGET_64BIT ? "ldu" : "lwzu"),
18157 lazy_ptr_name);
18158 fprintf (file, "\tmtctr r12\n");
18159 fprintf (file, "\tbctr\n");
18160 }
18161
18162 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
18163 fprintf (file, "%s:\n", lazy_ptr_name);
18164 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18165 fprintf (file, "%sdyld_stub_binding_helper\n",
18166 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
18167 }
18168
18169 /* Legitimize PIC addresses. If the address is already
18170 position-independent, we return ORIG. Newly generated
18171 position-independent addresses go into a reg. This is REG if non
18172 zero, otherwise we allocate register(s) as necessary. */
18173
18174 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
18175
18176 rtx
rs6000_machopic_legitimize_pic_address(rtx orig,enum machine_mode mode,rtx reg)18177 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
18178 rtx reg)
18179 {
18180 rtx base, offset;
18181
18182 if (reg == NULL && ! reload_in_progress && ! reload_completed)
18183 reg = gen_reg_rtx (Pmode);
18184
18185 if (GET_CODE (orig) == CONST)
18186 {
18187 rtx reg_temp;
18188
18189 if (GET_CODE (XEXP (orig, 0)) == PLUS
18190 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
18191 return orig;
18192
18193 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
18194
18195 /* Use a different reg for the intermediate value, as
18196 it will be marked UNCHANGING. */
18197 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
18198 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
18199 Pmode, reg_temp);
18200 offset =
18201 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
18202 Pmode, reg);
18203
18204 if (GET_CODE (offset) == CONST_INT)
18205 {
18206 if (SMALL_INT (offset))
18207 return plus_constant (base, INTVAL (offset));
18208 else if (! reload_in_progress && ! reload_completed)
18209 offset = force_reg (Pmode, offset);
18210 else
18211 {
18212 rtx mem = force_const_mem (Pmode, orig);
18213 return machopic_legitimize_pic_address (mem, Pmode, reg);
18214 }
18215 }
18216 return gen_rtx_PLUS (Pmode, base, offset);
18217 }
18218
18219 /* Fall back on generic machopic code. */
18220 return machopic_legitimize_pic_address (orig, mode, reg);
18221 }
18222
18223 /* Output a .machine directive for the Darwin assembler, and call
18224 the generic start_file routine. */
18225
18226 static void
rs6000_darwin_file_start(void)18227 rs6000_darwin_file_start (void)
18228 {
18229 static const struct
18230 {
18231 const char *arg;
18232 const char *name;
18233 int if_set;
18234 } mapping[] = {
18235 { "ppc64", "ppc64", MASK_64BIT },
18236 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
18237 { "power4", "ppc970", 0 },
18238 { "G5", "ppc970", 0 },
18239 { "7450", "ppc7450", 0 },
18240 { "7400", "ppc7400", MASK_ALTIVEC },
18241 { "G4", "ppc7400", 0 },
18242 { "750", "ppc750", 0 },
18243 { "740", "ppc750", 0 },
18244 { "G3", "ppc750", 0 },
18245 { "604e", "ppc604e", 0 },
18246 { "604", "ppc604", 0 },
18247 { "603e", "ppc603", 0 },
18248 { "603", "ppc603", 0 },
18249 { "601", "ppc601", 0 },
18250 { NULL, "ppc", 0 } };
18251 const char *cpu_id = "";
18252 size_t i;
18253
18254 rs6000_file_start ();
18255 darwin_file_start ();
18256
18257 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
18258 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
18259 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
18260 && rs6000_select[i].string[0] != '\0')
18261 cpu_id = rs6000_select[i].string;
18262
18263 /* Look through the mapping array. Pick the first name that either
18264 matches the argument, has a bit set in IF_SET that is also set
18265 in the target flags, or has a NULL name. */
18266
18267 i = 0;
18268 while (mapping[i].arg != NULL
18269 && strcmp (mapping[i].arg, cpu_id) != 0
18270 && (mapping[i].if_set & target_flags) == 0)
18271 i++;
18272
18273 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
18274 }
18275
18276 #endif /* TARGET_MACHO */
18277
18278 #if TARGET_ELF
18279 static int
rs6000_elf_reloc_rw_mask(void)18280 rs6000_elf_reloc_rw_mask (void)
18281 {
18282 if (flag_pic)
18283 return 3;
18284 else if (DEFAULT_ABI == ABI_AIX)
18285 return 2;
18286 else
18287 return 0;
18288 }
18289
18290 /* Record an element in the table of global constructors. SYMBOL is
18291 a SYMBOL_REF of the function to be called; PRIORITY is a number
18292 between 0 and MAX_INIT_PRIORITY.
18293
18294 This differs from default_named_section_asm_out_constructor in
18295 that we have special handling for -mrelocatable. */
18296
18297 static void
rs6000_elf_asm_out_constructor(rtx symbol,int priority)18298 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
18299 {
18300 const char *section = ".ctors";
18301 char buf[16];
18302
18303 if (priority != DEFAULT_INIT_PRIORITY)
18304 {
18305 sprintf (buf, ".ctors.%.5u",
18306 /* Invert the numbering so the linker puts us in the proper
18307 order; constructors are run from right to left, and the
18308 linker sorts in increasing order. */
18309 MAX_INIT_PRIORITY - priority);
18310 section = buf;
18311 }
18312
18313 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18314 assemble_align (POINTER_SIZE);
18315
18316 if (TARGET_RELOCATABLE)
18317 {
18318 fputs ("\t.long (", asm_out_file);
18319 output_addr_const (asm_out_file, symbol);
18320 fputs (")@fixup\n", asm_out_file);
18321 }
18322 else
18323 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18324 }
18325
18326 static void
rs6000_elf_asm_out_destructor(rtx symbol,int priority)18327 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
18328 {
18329 const char *section = ".dtors";
18330 char buf[16];
18331
18332 if (priority != DEFAULT_INIT_PRIORITY)
18333 {
18334 sprintf (buf, ".dtors.%.5u",
18335 /* Invert the numbering so the linker puts us in the proper
18336 order; constructors are run from right to left, and the
18337 linker sorts in increasing order. */
18338 MAX_INIT_PRIORITY - priority);
18339 section = buf;
18340 }
18341
18342 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18343 assemble_align (POINTER_SIZE);
18344
18345 if (TARGET_RELOCATABLE)
18346 {
18347 fputs ("\t.long (", asm_out_file);
18348 output_addr_const (asm_out_file, symbol);
18349 fputs (")@fixup\n", asm_out_file);
18350 }
18351 else
18352 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18353 }
18354
18355 void
rs6000_elf_declare_function_name(FILE * file,const char * name,tree decl)18356 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
18357 {
18358 if (TARGET_64BIT)
18359 {
18360 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
18361 ASM_OUTPUT_LABEL (file, name);
18362 fputs (DOUBLE_INT_ASM_OP, file);
18363 rs6000_output_function_entry (file, name);
18364 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
18365 if (DOT_SYMBOLS)
18366 {
18367 fputs ("\t.size\t", file);
18368 assemble_name (file, name);
18369 fputs (",24\n\t.type\t.", file);
18370 assemble_name (file, name);
18371 fputs (",@function\n", file);
18372 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
18373 {
18374 fputs ("\t.globl\t.", file);
18375 assemble_name (file, name);
18376 putc ('\n', file);
18377 }
18378 }
18379 else
18380 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18381 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18382 rs6000_output_function_entry (file, name);
18383 fputs (":\n", file);
18384 return;
18385 }
18386
18387 if (TARGET_RELOCATABLE
18388 && !TARGET_SECURE_PLT
18389 && (get_pool_size () != 0 || current_function_profile)
18390 && uses_TOC ())
18391 {
18392 char buf[256];
18393
18394 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18395
18396 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18397 fprintf (file, "\t.long ");
18398 assemble_name (file, buf);
18399 putc ('-', file);
18400 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18401 assemble_name (file, buf);
18402 putc ('\n', file);
18403 }
18404
18405 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18406 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18407
18408 if (DEFAULT_ABI == ABI_AIX)
18409 {
18410 const char *desc_name, *orig_name;
18411
18412 orig_name = (*targetm.strip_name_encoding) (name);
18413 desc_name = orig_name;
18414 while (*desc_name == '.')
18415 desc_name++;
18416
18417 if (TREE_PUBLIC (decl))
18418 fprintf (file, "\t.globl %s\n", desc_name);
18419
18420 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18421 fprintf (file, "%s:\n", desc_name);
18422 fprintf (file, "\t.long %s\n", orig_name);
18423 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18424 if (DEFAULT_ABI == ABI_AIX)
18425 fputs ("\t.long 0\n", file);
18426 fprintf (file, "\t.previous\n");
18427 }
18428 ASM_OUTPUT_LABEL (file, name);
18429 }
18430
18431 static void
rs6000_elf_end_indicate_exec_stack(void)18432 rs6000_elf_end_indicate_exec_stack (void)
18433 {
18434 if (TARGET_32BIT)
18435 file_end_indicate_exec_stack ();
18436 }
18437 #endif
18438
18439 #if TARGET_XCOFF
18440 static void
rs6000_xcoff_asm_output_anchor(rtx symbol)18441 rs6000_xcoff_asm_output_anchor (rtx symbol)
18442 {
18443 char buffer[100];
18444
18445 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
18446 SYMBOL_REF_BLOCK_OFFSET (symbol));
18447 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
18448 }
18449
18450 static void
rs6000_xcoff_asm_globalize_label(FILE * stream,const char * name)18451 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18452 {
18453 fputs (GLOBAL_ASM_OP, stream);
18454 RS6000_OUTPUT_BASENAME (stream, name);
18455 putc ('\n', stream);
18456 }
18457
18458 /* A get_unnamed_decl callback, used for read-only sections. PTR
18459 points to the section string variable. */
18460
18461 static void
rs6000_xcoff_output_readonly_section_asm_op(const void * directive)18462 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18463 {
18464 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18465 *(const char *const *) directive);
18466 }
18467
18468 /* Likewise for read-write sections. */
18469
18470 static void
rs6000_xcoff_output_readwrite_section_asm_op(const void * directive)18471 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18472 {
18473 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18474 *(const char *const *) directive);
18475 }
18476
18477 /* A get_unnamed_section callback, used for switching to toc_section. */
18478
18479 static void
rs6000_xcoff_output_toc_section_asm_op(const void * data ATTRIBUTE_UNUSED)18480 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18481 {
18482 if (TARGET_MINIMAL_TOC)
18483 {
18484 /* toc_section is always selected at least once from
18485 rs6000_xcoff_file_start, so this is guaranteed to
18486 always be defined once and only once in each file. */
18487 if (!toc_initialized)
18488 {
18489 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18490 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18491 toc_initialized = 1;
18492 }
18493 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18494 (TARGET_32BIT ? "" : ",3"));
18495 }
18496 else
18497 fputs ("\t.toc\n", asm_out_file);
18498 }
18499
18500 /* Implement TARGET_ASM_INIT_SECTIONS. */
18501
18502 static void
rs6000_xcoff_asm_init_sections(void)18503 rs6000_xcoff_asm_init_sections (void)
18504 {
18505 read_only_data_section
18506 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18507 &xcoff_read_only_section_name);
18508
18509 private_data_section
18510 = get_unnamed_section (SECTION_WRITE,
18511 rs6000_xcoff_output_readwrite_section_asm_op,
18512 &xcoff_private_data_section_name);
18513
18514 read_only_private_data_section
18515 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18516 &xcoff_private_data_section_name);
18517
18518 toc_section
18519 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18520
18521 readonly_data_section = read_only_data_section;
18522 exception_section = data_section;
18523 }
18524
18525 static int
rs6000_xcoff_reloc_rw_mask(void)18526 rs6000_xcoff_reloc_rw_mask (void)
18527 {
18528 return 3;
18529 }
18530
18531 static void
rs6000_xcoff_asm_named_section(const char * name,unsigned int flags,tree decl ATTRIBUTE_UNUSED)18532 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18533 tree decl ATTRIBUTE_UNUSED)
18534 {
18535 int smclass;
18536 static const char * const suffix[3] = { "PR", "RO", "RW" };
18537
18538 if (flags & SECTION_CODE)
18539 smclass = 0;
18540 else if (flags & SECTION_WRITE)
18541 smclass = 2;
18542 else
18543 smclass = 1;
18544
18545 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18546 (flags & SECTION_CODE) ? "." : "",
18547 name, suffix[smclass], flags & SECTION_ENTSIZE);
18548 }
18549
18550 static section *
rs6000_xcoff_select_section(tree decl,int reloc,unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)18551 rs6000_xcoff_select_section (tree decl, int reloc,
18552 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18553 {
18554 if (decl_readonly_section (decl, reloc))
18555 {
18556 if (TREE_PUBLIC (decl))
18557 return read_only_data_section;
18558 else
18559 return read_only_private_data_section;
18560 }
18561 else
18562 {
18563 if (TREE_PUBLIC (decl))
18564 return data_section;
18565 else
18566 return private_data_section;
18567 }
18568 }
18569
18570 static void
rs6000_xcoff_unique_section(tree decl,int reloc ATTRIBUTE_UNUSED)18571 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18572 {
18573 const char *name;
18574
18575 /* Use select_section for private and uninitialized data. */
18576 if (!TREE_PUBLIC (decl)
18577 || DECL_COMMON (decl)
18578 || DECL_INITIAL (decl) == NULL_TREE
18579 || DECL_INITIAL (decl) == error_mark_node
18580 || (flag_zero_initialized_in_bss
18581 && initializer_zerop (DECL_INITIAL (decl))))
18582 return;
18583
18584 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18585 name = (*targetm.strip_name_encoding) (name);
18586 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18587 }
18588
18589 /* Select section for constant in constant pool.
18590
18591 On RS/6000, all constants are in the private read-only data area.
18592 However, if this is being placed in the TOC it must be output as a
18593 toc entry. */
18594
18595 static section *
rs6000_xcoff_select_rtx_section(enum machine_mode mode,rtx x,unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)18596 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18597 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18598 {
18599 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18600 return toc_section;
18601 else
18602 return read_only_private_data_section;
18603 }
18604
18605 /* Remove any trailing [DS] or the like from the symbol name. */
18606
18607 static const char *
rs6000_xcoff_strip_name_encoding(const char * name)18608 rs6000_xcoff_strip_name_encoding (const char *name)
18609 {
18610 size_t len;
18611 if (*name == '*')
18612 name++;
18613 len = strlen (name);
18614 if (name[len - 1] == ']')
18615 return ggc_alloc_string (name, len - 4);
18616 else
18617 return name;
18618 }
18619
18620 /* Section attributes. AIX is always PIC. */
18621
18622 static unsigned int
rs6000_xcoff_section_type_flags(tree decl,const char * name,int reloc)18623 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18624 {
18625 unsigned int align;
18626 unsigned int flags = default_section_type_flags (decl, name, reloc);
18627
18628 /* Align to at least UNIT size. */
18629 if (flags & SECTION_CODE)
18630 align = MIN_UNITS_PER_WORD;
18631 else
18632 /* Increase alignment of large objects if not already stricter. */
18633 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18634 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18635 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18636
18637 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18638 }
18639
18640 /* Output at beginning of assembler file.
18641
18642 Initialize the section names for the RS/6000 at this point.
18643
18644 Specify filename, including full path, to assembler.
18645
18646 We want to go into the TOC section so at least one .toc will be emitted.
18647 Also, in order to output proper .bs/.es pairs, we need at least one static
18648 [RW] section emitted.
18649
18650 Finally, declare mcount when profiling to make the assembler happy. */
18651
18652 static void
rs6000_xcoff_file_start(void)18653 rs6000_xcoff_file_start (void)
18654 {
18655 rs6000_gen_section_name (&xcoff_bss_section_name,
18656 main_input_filename, ".bss_");
18657 rs6000_gen_section_name (&xcoff_private_data_section_name,
18658 main_input_filename, ".rw_");
18659 rs6000_gen_section_name (&xcoff_read_only_section_name,
18660 main_input_filename, ".ro_");
18661
18662 fputs ("\t.file\t", asm_out_file);
18663 output_quoted_string (asm_out_file, main_input_filename);
18664 fputc ('\n', asm_out_file);
18665 if (write_symbols != NO_DEBUG)
18666 switch_to_section (private_data_section);
18667 switch_to_section (text_section);
18668 if (profile_flag)
18669 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18670 rs6000_file_start ();
18671 }
18672
18673 /* Output at end of assembler file.
18674 On the RS/6000, referencing data should automatically pull in text. */
18675
18676 static void
rs6000_xcoff_file_end(void)18677 rs6000_xcoff_file_end (void)
18678 {
18679 switch_to_section (text_section);
18680 fputs ("_section_.text:\n", asm_out_file);
18681 switch_to_section (data_section);
18682 fputs (TARGET_32BIT
18683 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18684 asm_out_file);
18685 }
18686 #endif /* TARGET_XCOFF */
18687
18688 /* Compute a (partial) cost for rtx X. Return true if the complete
18689 cost has been computed, and false if subexpressions should be
18690 scanned. In either case, *TOTAL contains the cost result. */
18691
18692 static bool
rs6000_rtx_costs(rtx x,int code,int outer_code,int * total)18693 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18694 {
18695 enum machine_mode mode = GET_MODE (x);
18696
18697 switch (code)
18698 {
18699 /* On the RS/6000, if it is valid in the insn, it is free. */
18700 case CONST_INT:
18701 if (((outer_code == SET
18702 || outer_code == PLUS
18703 || outer_code == MINUS)
18704 && (satisfies_constraint_I (x)
18705 || satisfies_constraint_L (x)))
18706 || (outer_code == AND
18707 && (satisfies_constraint_K (x)
18708 || (mode == SImode
18709 ? satisfies_constraint_L (x)
18710 : satisfies_constraint_J (x))
18711 || mask_operand (x, mode)
18712 || (mode == DImode
18713 && mask64_operand (x, DImode))))
18714 || ((outer_code == IOR || outer_code == XOR)
18715 && (satisfies_constraint_K (x)
18716 || (mode == SImode
18717 ? satisfies_constraint_L (x)
18718 : satisfies_constraint_J (x))))
18719 || outer_code == ASHIFT
18720 || outer_code == ASHIFTRT
18721 || outer_code == LSHIFTRT
18722 || outer_code == ROTATE
18723 || outer_code == ROTATERT
18724 || outer_code == ZERO_EXTRACT
18725 || (outer_code == MULT
18726 && satisfies_constraint_I (x))
18727 || ((outer_code == DIV || outer_code == UDIV
18728 || outer_code == MOD || outer_code == UMOD)
18729 && exact_log2 (INTVAL (x)) >= 0)
18730 || (outer_code == COMPARE
18731 && (satisfies_constraint_I (x)
18732 || satisfies_constraint_K (x)))
18733 || (outer_code == EQ
18734 && (satisfies_constraint_I (x)
18735 || satisfies_constraint_K (x)
18736 || (mode == SImode
18737 ? satisfies_constraint_L (x)
18738 : satisfies_constraint_J (x))))
18739 || (outer_code == GTU
18740 && satisfies_constraint_I (x))
18741 || (outer_code == LTU
18742 && satisfies_constraint_P (x)))
18743 {
18744 *total = 0;
18745 return true;
18746 }
18747 else if ((outer_code == PLUS
18748 && reg_or_add_cint_operand (x, VOIDmode))
18749 || (outer_code == MINUS
18750 && reg_or_sub_cint_operand (x, VOIDmode))
18751 || ((outer_code == SET
18752 || outer_code == IOR
18753 || outer_code == XOR)
18754 && (INTVAL (x)
18755 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18756 {
18757 *total = COSTS_N_INSNS (1);
18758 return true;
18759 }
18760 /* FALLTHRU */
18761
18762 case CONST_DOUBLE:
18763 if (mode == DImode && code == CONST_DOUBLE)
18764 {
18765 if ((outer_code == IOR || outer_code == XOR)
18766 && CONST_DOUBLE_HIGH (x) == 0
18767 && (CONST_DOUBLE_LOW (x)
18768 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
18769 {
18770 *total = 0;
18771 return true;
18772 }
18773 else if ((outer_code == AND && and64_2_operand (x, DImode))
18774 || ((outer_code == SET
18775 || outer_code == IOR
18776 || outer_code == XOR)
18777 && CONST_DOUBLE_HIGH (x) == 0))
18778 {
18779 *total = COSTS_N_INSNS (1);
18780 return true;
18781 }
18782 }
18783 /* FALLTHRU */
18784
18785 case CONST:
18786 case HIGH:
18787 case SYMBOL_REF:
18788 case MEM:
18789 /* When optimizing for size, MEM should be slightly more expensive
18790 than generating address, e.g., (plus (reg) (const)).
18791 L1 cache latency is about two instructions. */
18792 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18793 return true;
18794
18795 case LABEL_REF:
18796 *total = 0;
18797 return true;
18798
18799 case PLUS:
18800 if (mode == DFmode)
18801 {
18802 if (GET_CODE (XEXP (x, 0)) == MULT)
18803 {
18804 /* FNMA accounted in outer NEG. */
18805 if (outer_code == NEG)
18806 *total = rs6000_cost->dmul - rs6000_cost->fp;
18807 else
18808 *total = rs6000_cost->dmul;
18809 }
18810 else
18811 *total = rs6000_cost->fp;
18812 }
18813 else if (mode == SFmode)
18814 {
18815 /* FNMA accounted in outer NEG. */
18816 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18817 *total = 0;
18818 else
18819 *total = rs6000_cost->fp;
18820 }
18821 else
18822 *total = COSTS_N_INSNS (1);
18823 return false;
18824
18825 case MINUS:
18826 if (mode == DFmode)
18827 {
18828 if (GET_CODE (XEXP (x, 0)) == MULT)
18829 {
18830 /* FNMA accounted in outer NEG. */
18831 if (outer_code == NEG)
18832 *total = 0;
18833 else
18834 *total = rs6000_cost->dmul;
18835 }
18836 else
18837 *total = rs6000_cost->fp;
18838 }
18839 else if (mode == SFmode)
18840 {
18841 /* FNMA accounted in outer NEG. */
18842 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18843 *total = 0;
18844 else
18845 *total = rs6000_cost->fp;
18846 }
18847 else
18848 *total = COSTS_N_INSNS (1);
18849 return false;
18850
18851 case MULT:
18852 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18853 && satisfies_constraint_I (XEXP (x, 1)))
18854 {
18855 if (INTVAL (XEXP (x, 1)) >= -256
18856 && INTVAL (XEXP (x, 1)) <= 255)
18857 *total = rs6000_cost->mulsi_const9;
18858 else
18859 *total = rs6000_cost->mulsi_const;
18860 }
18861 /* FMA accounted in outer PLUS/MINUS. */
18862 else if ((mode == DFmode || mode == SFmode)
18863 && (outer_code == PLUS || outer_code == MINUS))
18864 *total = 0;
18865 else if (mode == DFmode)
18866 *total = rs6000_cost->dmul;
18867 else if (mode == SFmode)
18868 *total = rs6000_cost->fp;
18869 else if (mode == DImode)
18870 *total = rs6000_cost->muldi;
18871 else
18872 *total = rs6000_cost->mulsi;
18873 return false;
18874
18875 case DIV:
18876 case MOD:
18877 if (FLOAT_MODE_P (mode))
18878 {
18879 *total = mode == DFmode ? rs6000_cost->ddiv
18880 : rs6000_cost->sdiv;
18881 return false;
18882 }
18883 /* FALLTHRU */
18884
18885 case UDIV:
18886 case UMOD:
18887 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18888 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18889 {
18890 if (code == DIV || code == MOD)
18891 /* Shift, addze */
18892 *total = COSTS_N_INSNS (2);
18893 else
18894 /* Shift */
18895 *total = COSTS_N_INSNS (1);
18896 }
18897 else
18898 {
18899 if (GET_MODE (XEXP (x, 1)) == DImode)
18900 *total = rs6000_cost->divdi;
18901 else
18902 *total = rs6000_cost->divsi;
18903 }
18904 /* Add in shift and subtract for MOD. */
18905 if (code == MOD || code == UMOD)
18906 *total += COSTS_N_INSNS (2);
18907 return false;
18908
18909 case FFS:
18910 *total = COSTS_N_INSNS (4);
18911 return false;
18912
18913 case NOT:
18914 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18915 {
18916 *total = 0;
18917 return false;
18918 }
18919 /* FALLTHRU */
18920
18921 case AND:
18922 case IOR:
18923 case XOR:
18924 case ZERO_EXTRACT:
18925 *total = COSTS_N_INSNS (1);
18926 return false;
18927
18928 case ASHIFT:
18929 case ASHIFTRT:
18930 case LSHIFTRT:
18931 case ROTATE:
18932 case ROTATERT:
18933 /* Handle mul_highpart. */
18934 if (outer_code == TRUNCATE
18935 && GET_CODE (XEXP (x, 0)) == MULT)
18936 {
18937 if (mode == DImode)
18938 *total = rs6000_cost->muldi;
18939 else
18940 *total = rs6000_cost->mulsi;
18941 return true;
18942 }
18943 else if (outer_code == AND)
18944 *total = 0;
18945 else
18946 *total = COSTS_N_INSNS (1);
18947 return false;
18948
18949 case SIGN_EXTEND:
18950 case ZERO_EXTEND:
18951 if (GET_CODE (XEXP (x, 0)) == MEM)
18952 *total = 0;
18953 else
18954 *total = COSTS_N_INSNS (1);
18955 return false;
18956
18957 case COMPARE:
18958 case NEG:
18959 case ABS:
18960 if (!FLOAT_MODE_P (mode))
18961 {
18962 *total = COSTS_N_INSNS (1);
18963 return false;
18964 }
18965 /* FALLTHRU */
18966
18967 case FLOAT:
18968 case UNSIGNED_FLOAT:
18969 case FIX:
18970 case UNSIGNED_FIX:
18971 case FLOAT_TRUNCATE:
18972 *total = rs6000_cost->fp;
18973 return false;
18974
18975 case FLOAT_EXTEND:
18976 if (mode == DFmode)
18977 *total = 0;
18978 else
18979 *total = rs6000_cost->fp;
18980 return false;
18981
18982 case UNSPEC:
18983 switch (XINT (x, 1))
18984 {
18985 case UNSPEC_FRSP:
18986 *total = rs6000_cost->fp;
18987 return true;
18988
18989 default:
18990 break;
18991 }
18992 break;
18993
18994 case CALL:
18995 case IF_THEN_ELSE:
18996 if (optimize_size)
18997 {
18998 *total = COSTS_N_INSNS (1);
18999 return true;
19000 }
19001 else if (FLOAT_MODE_P (mode)
19002 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
19003 {
19004 *total = rs6000_cost->fp;
19005 return false;
19006 }
19007 break;
19008
19009 case EQ:
19010 case GTU:
19011 case LTU:
19012 /* Carry bit requires mode == Pmode.
19013 NEG or PLUS already counted so only add one. */
19014 if (mode == Pmode
19015 && (outer_code == NEG || outer_code == PLUS))
19016 {
19017 *total = COSTS_N_INSNS (1);
19018 return true;
19019 }
19020 if (outer_code == SET)
19021 {
19022 if (XEXP (x, 1) == const0_rtx)
19023 {
19024 *total = COSTS_N_INSNS (2);
19025 return true;
19026 }
19027 else if (mode == Pmode)
19028 {
19029 *total = COSTS_N_INSNS (3);
19030 return false;
19031 }
19032 }
19033 /* FALLTHRU */
19034
19035 case GT:
19036 case LT:
19037 case UNORDERED:
19038 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
19039 {
19040 *total = COSTS_N_INSNS (2);
19041 return true;
19042 }
19043 /* CC COMPARE. */
19044 if (outer_code == COMPARE)
19045 {
19046 *total = 0;
19047 return true;
19048 }
19049 break;
19050
19051 default:
19052 break;
19053 }
19054
19055 return false;
19056 }
19057
19058 /* A C expression returning the cost of moving data from a register of class
19059 CLASS1 to one of CLASS2. */
19060
19061 int
rs6000_register_move_cost(enum machine_mode mode,enum reg_class from,enum reg_class to)19062 rs6000_register_move_cost (enum machine_mode mode,
19063 enum reg_class from, enum reg_class to)
19064 {
19065 /* Moves from/to GENERAL_REGS. */
19066 if (reg_classes_intersect_p (to, GENERAL_REGS)
19067 || reg_classes_intersect_p (from, GENERAL_REGS))
19068 {
19069 if (! reg_classes_intersect_p (to, GENERAL_REGS))
19070 from = to;
19071
19072 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
19073 return (rs6000_memory_move_cost (mode, from, 0)
19074 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
19075
19076 /* It's more expensive to move CR_REGS than CR0_REGS because of the
19077 shift. */
19078 else if (from == CR_REGS)
19079 return 4;
19080
19081 else
19082 /* A move will cost one instruction per GPR moved. */
19083 return 2 * hard_regno_nregs[0][mode];
19084 }
19085
19086 /* Moving between two similar registers is just one instruction. */
19087 else if (reg_classes_intersect_p (to, from))
19088 return mode == TFmode ? 4 : 2;
19089
19090 /* Everything else has to go through GENERAL_REGS. */
19091 else
19092 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
19093 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
19094 }
19095
19096 /* A C expressions returning the cost of moving data of MODE from a register to
19097 or from memory. */
19098
19099 int
rs6000_memory_move_cost(enum machine_mode mode,enum reg_class class,int in ATTRIBUTE_UNUSED)19100 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
19101 int in ATTRIBUTE_UNUSED)
19102 {
19103 if (reg_classes_intersect_p (class, GENERAL_REGS))
19104 return 4 * hard_regno_nregs[0][mode];
19105 else if (reg_classes_intersect_p (class, FLOAT_REGS))
19106 return 4 * hard_regno_nregs[32][mode];
19107 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
19108 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
19109 else
19110 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
19111 }
19112
19113 /* Newton-Raphson approximation of single-precision floating point divide n/d.
19114 Assumes no trapping math and finite arguments. */
19115
19116 void
rs6000_emit_swdivsf(rtx res,rtx n,rtx d)19117 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
19118 {
19119 rtx x0, e0, e1, y1, u0, v0, one;
19120
19121 x0 = gen_reg_rtx (SFmode);
19122 e0 = gen_reg_rtx (SFmode);
19123 e1 = gen_reg_rtx (SFmode);
19124 y1 = gen_reg_rtx (SFmode);
19125 u0 = gen_reg_rtx (SFmode);
19126 v0 = gen_reg_rtx (SFmode);
19127 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
19128
19129 /* x0 = 1./d estimate */
19130 emit_insn (gen_rtx_SET (VOIDmode, x0,
19131 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
19132 UNSPEC_FRES)));
19133 /* e0 = 1. - d * x0 */
19134 emit_insn (gen_rtx_SET (VOIDmode, e0,
19135 gen_rtx_MINUS (SFmode, one,
19136 gen_rtx_MULT (SFmode, d, x0))));
19137 /* e1 = e0 + e0 * e0 */
19138 emit_insn (gen_rtx_SET (VOIDmode, e1,
19139 gen_rtx_PLUS (SFmode,
19140 gen_rtx_MULT (SFmode, e0, e0), e0)));
19141 /* y1 = x0 + e1 * x0 */
19142 emit_insn (gen_rtx_SET (VOIDmode, y1,
19143 gen_rtx_PLUS (SFmode,
19144 gen_rtx_MULT (SFmode, e1, x0), x0)));
19145 /* u0 = n * y1 */
19146 emit_insn (gen_rtx_SET (VOIDmode, u0,
19147 gen_rtx_MULT (SFmode, n, y1)));
19148 /* v0 = n - d * u0 */
19149 emit_insn (gen_rtx_SET (VOIDmode, v0,
19150 gen_rtx_MINUS (SFmode, n,
19151 gen_rtx_MULT (SFmode, d, u0))));
19152 /* res = u0 + v0 * y1 */
19153 emit_insn (gen_rtx_SET (VOIDmode, res,
19154 gen_rtx_PLUS (SFmode,
19155 gen_rtx_MULT (SFmode, v0, y1), u0)));
19156 }
19157
19158 /* Newton-Raphson approximation of double-precision floating point divide n/d.
19159 Assumes no trapping math and finite arguments. */
19160
19161 void
rs6000_emit_swdivdf(rtx res,rtx n,rtx d)19162 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
19163 {
19164 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
19165
19166 x0 = gen_reg_rtx (DFmode);
19167 e0 = gen_reg_rtx (DFmode);
19168 e1 = gen_reg_rtx (DFmode);
19169 e2 = gen_reg_rtx (DFmode);
19170 y1 = gen_reg_rtx (DFmode);
19171 y2 = gen_reg_rtx (DFmode);
19172 y3 = gen_reg_rtx (DFmode);
19173 u0 = gen_reg_rtx (DFmode);
19174 v0 = gen_reg_rtx (DFmode);
19175 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
19176
19177 /* x0 = 1./d estimate */
19178 emit_insn (gen_rtx_SET (VOIDmode, x0,
19179 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
19180 UNSPEC_FRES)));
19181 /* e0 = 1. - d * x0 */
19182 emit_insn (gen_rtx_SET (VOIDmode, e0,
19183 gen_rtx_MINUS (DFmode, one,
19184 gen_rtx_MULT (SFmode, d, x0))));
19185 /* y1 = x0 + e0 * x0 */
19186 emit_insn (gen_rtx_SET (VOIDmode, y1,
19187 gen_rtx_PLUS (DFmode,
19188 gen_rtx_MULT (DFmode, e0, x0), x0)));
19189 /* e1 = e0 * e0 */
19190 emit_insn (gen_rtx_SET (VOIDmode, e1,
19191 gen_rtx_MULT (DFmode, e0, e0)));
19192 /* y2 = y1 + e1 * y1 */
19193 emit_insn (gen_rtx_SET (VOIDmode, y2,
19194 gen_rtx_PLUS (DFmode,
19195 gen_rtx_MULT (DFmode, e1, y1), y1)));
19196 /* e2 = e1 * e1 */
19197 emit_insn (gen_rtx_SET (VOIDmode, e2,
19198 gen_rtx_MULT (DFmode, e1, e1)));
19199 /* y3 = y2 + e2 * y2 */
19200 emit_insn (gen_rtx_SET (VOIDmode, y3,
19201 gen_rtx_PLUS (DFmode,
19202 gen_rtx_MULT (DFmode, e2, y2), y2)));
19203 /* u0 = n * y3 */
19204 emit_insn (gen_rtx_SET (VOIDmode, u0,
19205 gen_rtx_MULT (DFmode, n, y3)));
19206 /* v0 = n - d * u0 */
19207 emit_insn (gen_rtx_SET (VOIDmode, v0,
19208 gen_rtx_MINUS (DFmode, n,
19209 gen_rtx_MULT (DFmode, d, u0))));
19210 /* res = u0 + v0 * y3 */
19211 emit_insn (gen_rtx_SET (VOIDmode, res,
19212 gen_rtx_PLUS (DFmode,
19213 gen_rtx_MULT (DFmode, v0, y3), u0)));
19214 }
19215
19216 /* Return an RTX representing where to find the function value of a
19217 function returning MODE. */
19218 static rtx
rs6000_complex_function_value(enum machine_mode mode)19219 rs6000_complex_function_value (enum machine_mode mode)
19220 {
19221 unsigned int regno;
19222 rtx r1, r2;
19223 enum machine_mode inner = GET_MODE_INNER (mode);
19224 unsigned int inner_bytes = GET_MODE_SIZE (inner);
19225
19226 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
19227 regno = FP_ARG_RETURN;
19228 else
19229 {
19230 regno = GP_ARG_RETURN;
19231
19232 /* 32-bit is OK since it'll go in r3/r4. */
19233 if (TARGET_32BIT && inner_bytes >= 4)
19234 return gen_rtx_REG (mode, regno);
19235 }
19236
19237 if (inner_bytes >= 8)
19238 return gen_rtx_REG (mode, regno);
19239
19240 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
19241 const0_rtx);
19242 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
19243 GEN_INT (inner_bytes));
19244 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
19245 }
19246
19247 /* Define how to find the value returned by a function.
19248 VALTYPE is the data type of the value (as a tree).
19249 If the precise function being called is known, FUNC is its FUNCTION_DECL;
19250 otherwise, FUNC is 0.
19251
19252 On the SPE, both FPs and vectors are returned in r3.
19253
19254 On RS/6000 an integer value is in r3 and a floating-point value is in
19255 fp1, unless -msoft-float. */
19256
19257 rtx
rs6000_function_value(tree valtype,tree func ATTRIBUTE_UNUSED)19258 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
19259 {
19260 enum machine_mode mode;
19261 unsigned int regno;
19262
19263 /* Special handling for structs in darwin64. */
19264 if (rs6000_darwin64_abi
19265 && TYPE_MODE (valtype) == BLKmode
19266 && TREE_CODE (valtype) == RECORD_TYPE
19267 && int_size_in_bytes (valtype) > 0)
19268 {
19269 CUMULATIVE_ARGS valcum;
19270 rtx valret;
19271
19272 valcum.words = 0;
19273 valcum.fregno = FP_ARG_MIN_REG;
19274 valcum.vregno = ALTIVEC_ARG_MIN_REG;
19275 /* Do a trial code generation as if this were going to be passed as
19276 an argument; if any part goes in memory, we return NULL. */
19277 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
19278 if (valret)
19279 return valret;
19280 /* Otherwise fall through to standard ABI rules. */
19281 }
19282
19283 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
19284 {
19285 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19286 return gen_rtx_PARALLEL (DImode,
19287 gen_rtvec (2,
19288 gen_rtx_EXPR_LIST (VOIDmode,
19289 gen_rtx_REG (SImode, GP_ARG_RETURN),
19290 const0_rtx),
19291 gen_rtx_EXPR_LIST (VOIDmode,
19292 gen_rtx_REG (SImode,
19293 GP_ARG_RETURN + 1),
19294 GEN_INT (4))));
19295 }
19296 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
19297 {
19298 return gen_rtx_PARALLEL (DCmode,
19299 gen_rtvec (4,
19300 gen_rtx_EXPR_LIST (VOIDmode,
19301 gen_rtx_REG (SImode, GP_ARG_RETURN),
19302 const0_rtx),
19303 gen_rtx_EXPR_LIST (VOIDmode,
19304 gen_rtx_REG (SImode,
19305 GP_ARG_RETURN + 1),
19306 GEN_INT (4)),
19307 gen_rtx_EXPR_LIST (VOIDmode,
19308 gen_rtx_REG (SImode,
19309 GP_ARG_RETURN + 2),
19310 GEN_INT (8)),
19311 gen_rtx_EXPR_LIST (VOIDmode,
19312 gen_rtx_REG (SImode,
19313 GP_ARG_RETURN + 3),
19314 GEN_INT (12))));
19315 }
19316
19317 mode = TYPE_MODE (valtype);
19318 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
19319 || POINTER_TYPE_P (valtype))
19320 mode = TARGET_32BIT ? SImode : DImode;
19321
19322 if (DECIMAL_FLOAT_MODE_P (mode))
19323 regno = GP_ARG_RETURN;
19324 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
19325 regno = FP_ARG_RETURN;
19326 else if (TREE_CODE (valtype) == COMPLEX_TYPE
19327 && targetm.calls.split_complex_arg)
19328 return rs6000_complex_function_value (mode);
19329 else if (TREE_CODE (valtype) == VECTOR_TYPE
19330 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
19331 && ALTIVEC_VECTOR_MODE (mode))
19332 regno = ALTIVEC_ARG_RETURN;
19333 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19334 && (mode == DFmode || mode == DCmode))
19335 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19336 else
19337 regno = GP_ARG_RETURN;
19338
19339 return gen_rtx_REG (mode, regno);
19340 }
19341
19342 /* Define how to find the value returned by a library function
19343 assuming the value has mode MODE. */
19344 rtx
rs6000_libcall_value(enum machine_mode mode)19345 rs6000_libcall_value (enum machine_mode mode)
19346 {
19347 unsigned int regno;
19348
19349 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
19350 {
19351 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19352 return gen_rtx_PARALLEL (DImode,
19353 gen_rtvec (2,
19354 gen_rtx_EXPR_LIST (VOIDmode,
19355 gen_rtx_REG (SImode, GP_ARG_RETURN),
19356 const0_rtx),
19357 gen_rtx_EXPR_LIST (VOIDmode,
19358 gen_rtx_REG (SImode,
19359 GP_ARG_RETURN + 1),
19360 GEN_INT (4))));
19361 }
19362
19363 if (DECIMAL_FLOAT_MODE_P (mode))
19364 regno = GP_ARG_RETURN;
19365 else if (SCALAR_FLOAT_MODE_P (mode)
19366 && TARGET_HARD_FLOAT && TARGET_FPRS)
19367 regno = FP_ARG_RETURN;
19368 else if (ALTIVEC_VECTOR_MODE (mode)
19369 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
19370 regno = ALTIVEC_ARG_RETURN;
19371 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
19372 return rs6000_complex_function_value (mode);
19373 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19374 && (mode == DFmode || mode == DCmode))
19375 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19376 else
19377 regno = GP_ARG_RETURN;
19378
19379 return gen_rtx_REG (mode, regno);
19380 }
19381
19382 /* Define the offset between two registers, FROM to be eliminated and its
19383 replacement TO, at the start of a routine. */
19384 HOST_WIDE_INT
rs6000_initial_elimination_offset(int from,int to)19385 rs6000_initial_elimination_offset (int from, int to)
19386 {
19387 rs6000_stack_t *info = rs6000_stack_info ();
19388 HOST_WIDE_INT offset;
19389
19390 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19391 offset = info->push_p ? 0 : -info->total_size;
19392 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19393 {
19394 offset = info->push_p ? 0 : -info->total_size;
19395 if (FRAME_GROWS_DOWNWARD)
19396 offset += info->fixed_size + info->vars_size + info->parm_size;
19397 }
19398 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19399 offset = FRAME_GROWS_DOWNWARD
19400 ? info->fixed_size + info->vars_size + info->parm_size
19401 : 0;
19402 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19403 offset = info->total_size;
19404 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19405 offset = info->push_p ? info->total_size : 0;
19406 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19407 offset = 0;
19408 else
19409 gcc_unreachable ();
19410
19411 return offset;
19412 }
19413
19414 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19415
19416 static bool
rs6000_is_opaque_type(tree type)19417 rs6000_is_opaque_type (tree type)
19418 {
19419 return (type == opaque_V2SI_type_node
19420 || type == opaque_V2SF_type_node
19421 || type == opaque_p_V2SI_type_node
19422 || type == opaque_V4SI_type_node);
19423 }
19424
19425 static rtx
rs6000_dwarf_register_span(rtx reg)19426 rs6000_dwarf_register_span (rtx reg)
19427 {
19428 unsigned regno;
19429
19430 if (TARGET_SPE
19431 && (SPE_VECTOR_MODE (GET_MODE (reg))
19432 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19433 ;
19434 else
19435 return NULL_RTX;
19436
19437 regno = REGNO (reg);
19438
19439 /* The duality of the SPE register size wreaks all kinds of havoc.
19440 This is a way of distinguishing r0 in 32-bits from r0 in
19441 64-bits. */
19442 return
19443 gen_rtx_PARALLEL (VOIDmode,
19444 BYTES_BIG_ENDIAN
19445 ? gen_rtvec (2,
19446 gen_rtx_REG (SImode, regno + 1200),
19447 gen_rtx_REG (SImode, regno))
19448 : gen_rtvec (2,
19449 gen_rtx_REG (SImode, regno),
19450 gen_rtx_REG (SImode, regno + 1200)));
19451 }
19452
19453 /* Map internal gcc register numbers to DWARF2 register numbers. */
19454
19455 unsigned int
rs6000_dbx_register_number(unsigned int regno)19456 rs6000_dbx_register_number (unsigned int regno)
19457 {
19458 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19459 return regno;
19460 if (regno == MQ_REGNO)
19461 return 100;
19462 if (regno == LINK_REGISTER_REGNUM)
19463 return 108;
19464 if (regno == COUNT_REGISTER_REGNUM)
19465 return 109;
19466 if (CR_REGNO_P (regno))
19467 return regno - CR0_REGNO + 86;
19468 if (regno == XER_REGNO)
19469 return 101;
19470 if (ALTIVEC_REGNO_P (regno))
19471 return regno - FIRST_ALTIVEC_REGNO + 1124;
19472 if (regno == VRSAVE_REGNO)
19473 return 356;
19474 if (regno == VSCR_REGNO)
19475 return 67;
19476 if (regno == SPE_ACC_REGNO)
19477 return 99;
19478 if (regno == SPEFSCR_REGNO)
19479 return 612;
19480 /* SPE high reg number. We get these values of regno from
19481 rs6000_dwarf_register_span. */
19482 gcc_assert (regno >= 1200 && regno < 1232);
19483 return regno;
19484 }
19485
19486 /* target hook eh_return_filter_mode */
19487 static enum machine_mode
rs6000_eh_return_filter_mode(void)19488 rs6000_eh_return_filter_mode (void)
19489 {
19490 return TARGET_32BIT ? SImode : word_mode;
19491 }
19492
19493 /* Target hook for scalar_mode_supported_p. */
19494 static bool
rs6000_scalar_mode_supported_p(enum machine_mode mode)19495 rs6000_scalar_mode_supported_p (enum machine_mode mode)
19496 {
19497 if (DECIMAL_FLOAT_MODE_P (mode))
19498 return true;
19499 else
19500 return default_scalar_mode_supported_p (mode);
19501 }
19502
19503 /* Target hook for vector_mode_supported_p. */
19504 static bool
rs6000_vector_mode_supported_p(enum machine_mode mode)19505 rs6000_vector_mode_supported_p (enum machine_mode mode)
19506 {
19507
19508 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19509 return true;
19510
19511 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19512 return true;
19513
19514 else
19515 return false;
19516 }
19517
19518 /* Target hook for invalid_arg_for_unprototyped_fn. */
19519 static const char *
invalid_arg_for_unprototyped_fn(tree typelist,tree funcdecl,tree val)19520 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19521 {
19522 return (!rs6000_darwin64_abi
19523 && typelist == 0
19524 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19525 && (funcdecl == NULL_TREE
19526 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19527 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19528 ? N_("AltiVec argument passed to unprototyped function")
19529 : NULL;
19530 }
19531
19532 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19533 setup by using __stack_chk_fail_local hidden function instead of
19534 calling __stack_chk_fail directly. Otherwise it is better to call
19535 __stack_chk_fail directly. */
19536
19537 static tree
rs6000_stack_protect_fail(void)19538 rs6000_stack_protect_fail (void)
19539 {
19540 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19541 ? default_hidden_stack_protect_fail ()
19542 : default_external_stack_protect_fail ();
19543 }
19544
19545 #include "gt-rs6000.h"
19546