Searched refs:Control1 (Results 1 – 1 of 1) sorted by relevance
42 Control1 = 0x2c>>2, enumerator201 r[Control0], r[Control1], r[Control2]); in emmcinit()202 WR(Control1, Srsthc); in emmcinit()204 while(r[Control1] & Srsthc) in emmcinit()229 WR(Control1, clkdiv(emmc.extclk/Initfreq - 1) | in emmcenable()233 if(r[Control1] & Clkstable) in emmcenable()256 WR(Control1, r[Control1] | Srstcmd); in emmccmd()257 while(r[Control1] & Srstcmd) in emmccmd()266 WR(Control1, r[Control1] | Srstdata); in emmccmd()267 while(r[Control1] & Srstdata) in emmccmd()[all …]