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Searched refs:uint8_t (Results 1 – 25 of 3058) sorted by relevance

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/openbsd-src/usr.sbin/unbound/testcode/
H A Dunitdname.c105 unit_assert(query_dname_compare((uint8_t*)"", (uint8_t*)"") == 0); in dname_test_query_dname_compare()
106 unit_assert(query_dname_compare((uint8_t*)"\001a", in dname_test_query_dname_compare()
107 (uint8_t*)"\001a") == 0); in dname_test_query_dname_compare()
108 unit_assert(query_dname_compare((uint8_t*)"\003abc\001a", in dname_test_query_dname_compare()
109 (uint8_t*)"\003abc\001a") == 0); in dname_test_query_dname_compare()
110 unit_assert(query_dname_compare((uint8_t*)"\003aBc\001a", in dname_test_query_dname_compare()
111 (uint8_t*)"\003AbC\001A") == 0); in dname_test_query_dname_compare()
112 unit_assert(query_dname_compare((uint8_t*)"\003abc", in dname_test_query_dname_compare()
113 (uint8_t*)"\003abc\001a") == -1); in dname_test_query_dname_compare()
114 unit_assert(query_dname_compare((uint8_t*)"\003abc\001a", in dname_test_query_dname_compare()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/
H A Ddc_dp_types.h153 uint8_t link_rate_set;
158 uint8_t level : 4;
159 uint8_t reserved : 1;
160 uint8_t no_preshoot : 1;
161 uint8_t no_deemphasis : 1;
162 uint8_t method2 : 1;
164 uint8_t raw;
194 uint8_t VC_PAYLOAD_TABLE_UPDATED:1;
195 uint8_t ACT_HANDLED:1;
197 uint8_t raw;
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/openbsd-src/sys/dev/pci/drm/amd/include/
H A Datomfirmware.h52 #ifndef uint8_t
53 typedef unsigned char uint8_t; typedef
235 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
236 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
245 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
448 uint8_t h_border;
449 uint8_t v_border;
451 uint8_t atom_mode_id;
452 uint8_t refreshrate;
491 uint8_t mem_module_i
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/openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dsmu7_fusion.h45 uint8_t DisplayPhy1Config;
46 uint8_t DisplayPhy2Config;
47 uint8_t DisplayPhy3Config;
48 uint8_t DisplayPhy4Config;
50 uint8_t DisplayPhy5Config;
51 uint8_t DisplayPhy6Config;
52 uint8_t DisplayPhy7Config;
53 uint8_t DisplayPhy8Config;
59 uint8_t SClkDpmEnabledLevels;
60 uint8_t MClkDpmEnabledLevels;
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H A Dsmu74_discrete.h44 uint8_t vco_setting;
45 uint8_t postdiv;
55 uint8_t Smio;
56 uint8_t padding;
72 uint8_t PllRange;
73 uint8_t SSc_En;
85 uint8_t pcieDpmLevel;
86 uint8_t DeepSleepDivId;
92 uint8_t SclkDid;
93 uint8_t padding;
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H A Dsmu73_discrete.h32 uint8_t Smio;
33 uint8_t padding;
49 uint8_t pcieDpmLevel;
50 uint8_t DeepSleepDivId;
58 uint8_t SclkDid;
59 uint8_t DisplayWatermark;
60 uint8_t EnabledForActivity;
61 uint8_t EnabledForThrottle;
62 uint8_t UpHyst;
63 uint8_t DownHyst;
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H A Dsmu71_discrete.h41 uint8_t Smio;
42 uint8_t padding;
54 uint8_t pcieDpmLevel;
55 uint8_t DeepSleepDivId;
64 uint8_t SclkDid;
65 uint8_t DisplayWatermark;
66 uint8_t EnabledForActivity;
67 uint8_t EnabledForThrottle;
68 uint8_t UpHyst;
69 uint8_t DownHyst;
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H A Dsmu75_discrete.h43 uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */
44 uint8_t postdiv; /* divide by 2^n */
53 uint8_t Smio;
54 uint8_t padding;
70 uint8_t PllRange;
71 uint8_t SSc_En;
84 uint8_t pcieDpmLevel;
85 uint8_t DeepSleepDivId;
93 uint8_t SclkDid;
94 uint8_t padding;
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H A Dsmu7_discrete.h55 uint8_t DisplayPhy1Config;
56 uint8_t DisplayPhy2Config;
57 uint8_t DisplayPhy3Config;
58 uint8_t DisplayPhy4Config;
60 uint8_t DisplayPhy5Config;
61 uint8_t DisplayPhy6Config;
62 uint8_t DisplayPhy7Config;
63 uint8_t DisplayPhy8Config;
69 uint8_t SClkDpmEnabledLevels;
70 uint8_t MClkDpmEnabledLevels;
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H A Dsmu72_discrete.h35 uint8_t Smio;
36 uint8_t padding;
52 uint8_t pcieDpmLevel;
53 uint8_t DeepSleepDivId;
62 uint8_t SclkDid;
63 uint8_t DisplayWatermark;
64 uint8_t EnabledForActivity;
65 uint8_t EnabledForThrottle;
66 uint8_t UpHyst;
67 uint8_t DownHyst;
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H A Dsmu9_driver_if.h84 uint8_t SsOn;
85 uint8_t Did; /* DID */
93 uint8_t a0_shift;
94 uint8_t a1_shift;
95 uint8_t a2_shift;
96 uint8_t padding;
104 uint8_t m1_shift;
105 uint8_t m2_shift;
106 uint8_t b_shift;
107 uint8_t padding;
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/openbsd-src/sys/dev/pci/drm/radeon/
H A Dsmu7_fusion.h46 uint8_t DisplayPhy1Config;
47 uint8_t DisplayPhy2Config;
48 uint8_t DisplayPhy3Config;
49 uint8_t DisplayPhy4Config;
51 uint8_t DisplayPhy5Config;
52 uint8_t DisplayPhy6Config;
53 uint8_t DisplayPhy7Config;
54 uint8_t DisplayPhy8Config;
60 uint8_t SClkDpmEnabledLevels;
61 uint8_t MClkDpmEnabledLevels;
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H A Dsmu7_discrete.h55 uint8_t DisplayPhy1Config;
56 uint8_t DisplayPhy2Config;
57 uint8_t DisplayPhy3Config;
58 uint8_t DisplayPhy4Config;
60 uint8_t DisplayPhy5Config;
61 uint8_t DisplayPhy6Config;
62 uint8_t DisplayPhy7Config;
63 uint8_t DisplayPhy8Config;
69 uint8_t SClkDpmEnabledLevels;
70 uint8_t MClkDpmEnabledLevels;
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/openbsd-src/sys/arch/powerpc64/include/
H A Dsmbiosvar.h44 uint8_t mjr;
45 uint8_t min;
46 uint8_t *addr;
53 uint8_t checksum; /* Entry point checksum */
54 uint8_t len; /* Entry point structure length */
55 uint8_t majrev; /* Specification major revision */
56 uint8_t minrev; /* Specification minor revision */
58 uint8_t epr; /* Entry Point Revision */
59 uint8_t fa[5]; /* value determined by EPR */
60 uint8_t sasig[5]; /* Secondary Anchor "_DMI_" */
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/openbsd-src/sys/arch/i386/include/
H A Dsmbiosvar.h47 uint8_t mjr;
48 uint8_t min;
49 uint8_t *addr;
56 uint8_t checksum; /* Entry point checksum */
57 uint8_t len; /* Entry point structure length */
58 uint8_t majrev; /* Specification major revision */
59 uint8_t minrev; /* Specification minor revision */
61 uint8_t epr; /* Entry Point Revision */
62 uint8_t fa[5]; /* value determined by EPR */
63 uint8_t sasig[5]; /* Secondary Anchor "_DMI_" */
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/openbsd-src/sys/arch/amd64/include/
H A Dsmbiosvar.h47 uint8_t mjr;
48 uint8_t min;
49 uint8_t *addr;
56 uint8_t checksum; /* Entry point checksum */
57 uint8_t len; /* Entry point structure length */
58 uint8_t majrev; /* Specification major revision */
59 uint8_t minrev; /* Specification minor revision */
61 uint8_t epr; /* Entry Point Revision */
62 uint8_t fa[5]; /* value determined by EPR */
63 uint8_t sasig[5]; /* Secondary Anchor "_DMI_" */
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/openbsd-src/sys/arch/arm64/include/
H A Dsmbiosvar.h44 uint8_t mjr;
45 uint8_t min;
46 uint8_t *addr;
53 uint8_t checksum; /* Entry point checksum */
54 uint8_t len; /* Entry point structure length */
55 uint8_t majrev; /* Specification major revision */
56 uint8_t minrev; /* Specification minor revision */
58 uint8_t epr; /* Entry Point Revision */
59 uint8_t fa[5]; /* value determined by EPR */
60 uint8_t sasig[5]; /* Secondary Anchor "_DMI_" */
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/openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dppatomfwctrl.h47 uint8_t psi0_enable;
48 uint8_t psi1_enable;
49 uint8_t max_vid_step;
50 uint8_t telemetry_offset;
51 uint8_t telemetry_slope;
57 uint8_t uc_gpio_pin_bit_shift;
66 uint8_t ucPll_ss_enable;
67 uint8_t ucReserve;
96 uint8_t ucEnableGbVdroopTableCkson;
97 uint8_t ucEnableGbFuseTableCkson;
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/openbsd-src/sys/dev/pci/
H A Dif_iwireg.h93 uint8_t oldvermaj;
94 uint8_t oldvermin;
95 uint8_t vermaj;
96 uint8_t vermin;
103 uint8_t type;
109 uint8_t seq;
110 uint8_t flags;
113 uint8_t reserved;
118 uint8_t type;
129 uint8_t flags;
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/openbsd-src/sys/dev/acpi/
H A Dacpireg.h24 uint8_t signature[8];
27 uint8_t checksum; /* make sum == 0 */
29 uint8_t oemid[6];
31 uint8_t revision; /* 0 for 1, 2 for 2 */
45 uint8_t rsdp_extchecksum; /* entire table */
46 uint8_t rsdp_reserved[3]; /* must be zero */
50 uint8_t signature[4];
54 uint8_t revision;
56 uint8_t checksum;
58 uint8_t oemi
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/openbsd-src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h343 uint8_t Enabled;
344 uint8_t Speed;
345 uint8_t SlaveAddress;
346 uint8_t ControllerPort;
347 uint8_t ControllerName;
348 uint8_t ThermalThrotter;
349 uint8_t I2cProtocol;
350 uint8_t PaddingConfig;
388 uint8_t ReadWriteData; //Return data for read. Data to send for write
389 …uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, an…
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/openbsd-src/sys/dev/pci/drm/amd/display/modules/hdcp/
H A Dhdcp.h42 uint8_t bksv_read;
43 uint8_t bksv_validation;
44 uint8_t create_session;
45 uint8_t an_write;
46 uint8_t aksv_write;
47 uint8_t ainfo_write;
48 uint8_t bcaps_read;
49 uint8_t r0p_read;
50 uint8_t rx_validation;
51 uint8_t encryption;
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/openbsd-src/sys/dev/pci/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h455 uint8_t psr;
456 uint8_t fw_assisted_mclk_switch;
457 uint8_t reserved[4];
458 uint8_t subvp_psr_support;
459 uint8_t gecc_enable;
507 uint8_t dal_fw; /**< 1 if the firmware is DAL */
508 uint8_t reserved[3]; /**< padding bits */
516 uint8_t reserved[64]; /**< padding bits */
1167 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
1200 uint8_t hubp_inst : 4; /**< HUBP instance */
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/openbsd-src/gnu/llvm/llvm/lib/Support/BLAKE3/
H A Dblake3_impl.h81 static const uint8_t MSG_SCHEDULE[7][16] = {
149 const uint8_t *p = (const uint8_t *)src; in load32()
154 INLINE void load_key_words(const uint8_t key[BLAKE3_KEY_LEN], in load_key_words()
167 uint8_t *p = (uint8_t *)dst; in store32()
168 p[0] = (uint8_t)(w >> 0); in store32()
169 p[1] = (uint8_t)(w >> 8); in store32()
170 p[2] = (uint8_t)(w >> 16); in store32()
171 p[3] = (uint8_t)(w >> 24); in store32()
174 INLINE void store_cv_words(uint8_t bytes_out[32], uint32_t cv_words[8]) { in store_cv_words()
187 const uint8_t block[BLAKE3_BLOCK_LEN],
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/openbsd-src/lib/libcrypto/ec/
H A Dec_curve.c87 uint8_t seed[20];
88 uint8_t p[28];
89 uint8_t a[28];
90 uint8_t b[28];
91 uint8_t x[28];
92 uint8_t y[28];
93 uint8_t order[28];
132 uint8_t seed[20];
133 uint8_t p[48];
134 uint8_t
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