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Searched refs:timing (Results 1 – 25 of 197) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/amd/display/dc/link/
H A Dlink_validation.c38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) in get_tmds_output_pixel_clock_100hz() argument
41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz()
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz()
48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz()
50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
66 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) in dp_active_dongle_validate_timing()
77 switch (timing->pixel_encoding) { in dp_active_dongle_validate_timing()
94 switch (timing->display_color_depth) { in dp_active_dongle_validate_timing()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.c42 bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) in optc201_is_two_pixels_per_containter() argument
44 return optc1_is_two_pixels_per_containter(timing); in optc201_is_two_pixels_per_containter()
76 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
83 ASSERT(timing != NULL); in optc201_validate_timing()
85 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
86 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
88 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
89 timing->h_border_right - in optc201_validate_timing()
90 timing->h_border_left); in optc201_validate_timing()
92 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && in optc201_validate_timing()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dsc/
H A Ddc_dsc.c56 const struct dc_crtc_timing *timing, const uint32_t kbps) in apply_128b_132b_stream_overhead() argument
63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
68 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
73 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
88 const struct dc_crtc_timing *timing, in dc_bandwidth_in_kbps_from_timing() argument
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
95 return dc_dsc_stream_bandwidth_in_kbps(timing, in dc_bandwidth_in_kbps_from_timing()
96 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
97 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
98 timing in dc_bandwidth_in_kbps_from_timing()
443 dc_dsc_compute_bandwidth_range(const struct display_stream_compressor * dsc,uint32_t dsc_min_slice_height_override,uint32_t min_bpp_x16,uint32_t max_bpp_x16,const struct dsc_dec_dpcd_caps * dsc_sink_caps,const struct dc_crtc_timing * timing,const enum dc_link_encoding_format link_encoding,struct dc_dsc_bw_range * range) dc_dsc_compute_bandwidth_range() argument
571 compute_bpp_x16_from_target_bandwidth(const uint32_t bandwidth_in_kbps,const struct dc_crtc_timing * timing,const uint32_t num_slices_h,const uint32_t bpp_increment_div,const bool is_dp) compute_bpp_x16_from_target_bandwidth() argument
603 decide_dsc_bandwidth_range(const uint32_t min_bpp_x16,const uint32_t max_bpp_x16,const uint32_t num_slices_h,const struct dsc_enc_caps * dsc_caps,const struct dc_crtc_timing * timing,const enum dc_link_encoding_format link_encoding,struct dc_dsc_bw_range * range) decide_dsc_bandwidth_range() argument
658 decide_dsc_target_bpp_x16(const struct dc_dsc_policy * policy,const struct dsc_enc_caps * dsc_common_caps,const int target_bandwidth_kbps,const struct dc_crtc_timing * timing,const int num_slices_h,const enum dc_link_encoding_format link_encoding,int * target_bpp_x16) decide_dsc_target_bpp_x16() argument
843 setup_dsc_config(const struct dsc_dec_dpcd_caps * dsc_sink_caps,const struct dsc_enc_caps * dsc_enc_caps,int target_bandwidth_kbps,const struct dc_crtc_timing * timing,const struct dc_dsc_config_options * options,const enum dc_link_encoding_format link_encoding,struct dc_dsc_config * dsc_cfg) setup_dsc_config() argument
1078 dc_dsc_compute_config(const struct display_stream_compressor * dsc,const struct dsc_dec_dpcd_caps * dsc_sink_caps,const struct dc_dsc_config_options * options,uint32_t target_bandwidth_kbps,const struct dc_crtc_timing * timing,const enum dc_link_encoding_format link_encoding,struct dc_dsc_config * dsc_cfg) dc_dsc_compute_config() argument
1093 dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing * timing,uint32_t bpp_x16,uint32_t num_slices_h,bool is_dp) dc_dsc_stream_bandwidth_in_kbps() argument
1110 dc_dsc_stream_bandwidth_overhead_in_kbps(const struct dc_crtc_timing * timing,const int num_slices_h,const bool is_dp) dc_dsc_stream_bandwidth_overhead_in_kbps() argument
1135 dc_dsc_get_policy_for_timing(const struct dc_crtc_timing * timing,uint32_t max_target_bpp_limit_override_x16,struct dc_dsc_policy * policy) dc_dsc_get_policy_for_timing() argument
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator_v.c243 const struct dc_crtc_timing *timing) in dce110_timing_generator_v_program_blanking() argument
245 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_v_program_blanking()
246 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
247 uint32_t v_sync_start = timing->v_addressable + vsync_offset; in dce110_timing_generator_v_program_blanking()
249 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
250 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
251 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
262 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
271 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
279 tmp = timing->h_total - in dce110_timing_generator_v_program_blanking()
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H A Ddce110_timing_generator.c67 struct dc_crtc_timing *timing) in dce110_timing_generator_apply_front_porch_workaround() argument
69 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()
70 if (timing->v_front_porch < 2) in dce110_timing_generator_apply_front_porch_workaround()
71 timing->v_front_porch = 2; in dce110_timing_generator_apply_front_porch_workaround()
73 if (timing->v_front_porch < 1) in dce110_timing_generator_apply_front_porch_workaround()
74 timing->v_front_porch = 1; in dce110_timing_generator_apply_front_porch_workaround()
256 const struct dc_crtc_timing *timing) in program_horz_count_by_2() argument
267 if (timing->flags.HORZ_COUNT_BY_TWO) in program_horz_count_by_2()
602 const struct dc_crtc_timing *timing) in dce110_timing_generator_program_blanking() argument
604 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_program_blanking()
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H A Ddce110_timing_generator.h129 const struct dc_crtc_timing *timing,
203 const struct dc_crtc_timing *timing);
247 const struct dc_crtc_timing *timing);
259 const struct dc_crtc_timing *timing,
273 const struct dc_crtc_timing *timing);
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c232 if (pipe->stream->timing.v_addressable != pipe->stream->dst.height || in dcn32_is_center_timing()
233 pipe->stream->timing.v_addressable != pipe->stream->src.height) { in dcn32_is_center_timing()
239 if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height && in dcn32_is_center_timing()
240 pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) { in dcn32_is_center_timing()
465 struct dc_crtc_timing *timing = NULL; in get_frame_rate_at_max_stretch_100hz() local
479 timing = &fpo_candidate_stream->timing; in get_frame_rate_at_max_stretch_100hz()
480 if (timing == NULL) in get_frame_rate_at_max_stretch_100hz()
485 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1; in get_frame_rate_at_max_stretch_100hz()
487 curr_v_blank = timing->v_total - timing->v_addressable; in get_frame_rate_at_max_stretch_100hz()
489 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total; in get_frame_rate_at_max_stretch_100hz()
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H A Ddcn32_dio_stream_encoder.c235 static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) in is_two_pixels_per_containter() argument
237 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; in is_two_pixels_per_containter()
239 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 in is_two_pixels_per_containter()
240 && !timing->dsc_cfg.ycbcr422_simple); in is_two_pixels_per_containter()
244 static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing) in is_h_timing_divisible_by_2() argument
254 if (timing) { in is_h_timing_divisible_by_2()
255 h_blank_start = timing->h_total - timing->h_front_porch; in is_h_timing_divisible_by_2()
256 h_blank_end = h_blank_start - timing->h_addressable; in is_h_timing_divisible_by_2()
262 divisible = (timing->h_total % 2 == 0) && in is_h_timing_divisible_by_2()
265 (timing->h_sync_width % 2 == 0); in is_h_timing_divisible_by_2()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/core/
H A Ddc_stream.c49 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && in update_stream_signal()
104 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; in dc_stream_construct()
106 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); in dc_stream_construct()
107 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
108 stream->timing.dsc_cfg.num_slices_v = 0; in dc_stream_construct()
109 stream->timing.dsc_cfg.bits_per_pixel = 128; in dc_stream_construct()
110 stream->timing.dsc_cfg.block_pred_enable = 1; in dc_stream_construct()
111 stream->timing.dsc_cfg.linebuf_depth = 9; in dc_stream_construct()
112 stream->timing.dsc_cfg.version_minor = 2; in dc_stream_construct()
113 stream->timing.dsc_cfg.ycbcr422_simple = 0; in dc_stream_construct()
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H A Ddc_resource.c80 * relatively the same independent from timing used.
529 stream1->timing.flags.VBLANK_SYNCHRONIZABLE && in resource_are_vblanks_synchronizable()
530 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) { in resource_are_vblanks_synchronizable()
532 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ in resource_are_vblanks_synchronizable()
533 stream1->timing.v_total > 60) in resource_are_vblanks_synchronizable()
535 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ in resource_are_vblanks_synchronizable()
536 stream2->timing.v_total > 60) in resource_are_vblanks_synchronizable()
539 stream1->timing in resource_are_vblanks_synchronizable()
1391 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; resource_build_scaling_params() local
2549 get_norm_pix_clk(const struct dc_crtc_timing * timing) get_norm_pix_clk() argument
3534 adaptive_sync_override_dp_info_packets_sdp_line_num(const struct dc_crtc_timing * timing,struct enc_sdp_line_num * sdp_line_num,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dlg_param) adaptive_sync_override_dp_info_packets_sdp_line_num() argument
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
115 timing, in dce120_timing_generator_validate_timing()
121 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()
122 timing->v_sync_width < tg110->min_v_sync_width) in dce120_timing_generator_validate_timing()
129 const struct dc_crtc_timing *timing) in dce120_tg_validate_timing() argument
131 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
430 const struct dc_crtc_timing *timing) in dce120_timing_generator_program_blanking() argument
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c284 static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) in micro_sec_to_vert_lines() argument
288 (((float)timing->h_total * 1000.0) / in micro_sec_to_vert_lines()
289 ((float)timing->pix_clk_100hz / 10.0)); in micro_sec_to_vert_lines()
296 static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing) in get_vertical_back_porch() argument
300 v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom; in get_vertical_back_porch()
301 v_blank = timing->v_total - v_active; in get_vertical_back_porch()
302 v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width; in get_vertical_back_porch()
322 struct dc_crtc_timing *timing; in dcn314_populate_dml_pipes_from_context_fpu() local
329 timing = &pipe->stream->timing; in dcn314_populate_dml_pipes_from_context_fpu()
331 num_lines = micro_sec_to_vert_lines(dcn3_14_ip.VBlankNomDefaultUS, timing); in dcn314_populate_dml_pipes_from_context_fpu()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_hwseq.c75 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); in calc_mpc_flow_ctrl_cnt()
81 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - in calc_mpc_flow_ctrl_cnt()
82 stream->timing.h_border_left - in calc_mpc_flow_ctrl_cnt()
83 stream->timing.h_border_right; in calc_mpc_flow_ctrl_cnt()
112 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
113 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in update_dsc_on_stream()
114 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in update_dsc_on_stream()
115 dsc_cfg.color_depth = stream->timing.display_color_depth; in update_dsc_on_stream()
117 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in update_dsc_on_stream()
186 …rol_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pip… in dcn314_update_odm()
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/openbsd-src/sys/dev/pci/drm/amd/display/modules/freesync/
H A Dfreesync.c117 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
118 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
135 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
136 stream->timing.h_total) + 500000, 1000000); in mod_freesync_calc_v_total_from_refresh()
139 if (v_total < stream->timing.v_total) { in mod_freesync_calc_v_total_from_refresh()
140 ASSERT(v_total < stream->timing.v_total); in mod_freesync_calc_v_total_from_refresh()
141 v_total = stream->timing.v_total; in mod_freesync_calc_v_total_from_refresh()
163 h_total_up_scaled = stream->timing.h_total * 10000; in calc_v_total_from_duration()
165 * stream->timing.pix_clk_100hz + (h_total_up_scaled - 1), in calc_v_total_from_duration()
169 duration_in_us) * (stream->timing in calc_v_total_from_duration()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c52 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) in apply_front_porch_workaround() argument
54 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()
55 if (timing->v_front_porch < 2) in apply_front_porch_workaround()
56 timing->v_front_porch = 2; in apply_front_porch_workaround()
58 if (timing->v_front_porch < 1) in apply_front_porch_workaround()
59 timing->v_front_porch = 1; in apply_front_porch_workaround()
587 const struct dc_crtc_timing *timing) in optc1_validate_timing() argument
594 ASSERT(timing != NULL); in optc1_validate_timing()
596 v_blank = (timing->v_total - timing->v_addressable - in optc1_validate_timing()
597 timing->v_border_top - timing->v_border_bottom); in optc1_validate_timing()
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H A Ddcn10_opp.c312 const struct dc_crtc_timing *timing) in opp1_program_stereo() argument
316 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; in opp1_program_stereo()
317 uint32_t space1_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
319 uint32_t space2_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
337 if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE) in opp1_program_stereo()
/openbsd-src/sys/dev/pci/drm/amd/display/modules/info_packet/
H A Dinfo_packet.c144 …if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FOR… in mod_build_vsc_infopacket()
250 switch (stream->timing.timing_3d_format) { in mod_build_vsc_infopacket()
343 switch (stream->timing.pixel_encoding) { in mod_build_vsc_infopacket()
362 switch (stream->timing.pixel_encoding) { in mod_build_vsc_infopacket()
401 switch (stream->timing.display_color_depth) { in mod_build_vsc_infopacket()
461 format = stream->timing.timing_3d_format; in mod_build_hf_vsif_infopacket()
465 if (stream->timing.hdmi_vic != 0 in mod_build_hf_vsif_infopacket()
466 && stream->timing.h_total >= 3840 in mod_build_hf_vsif_infopacket()
467 && stream->timing.v_total >= 2160 in mod_build_hf_vsif_infopacket()
506 info_packet->sb[5] = stream->timing.hdmi_vic; in mod_build_hf_vsif_infopacket()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c101 uint32_t vertical_total_min = stream->timing.v_total; in dce110_get_min_vblank_time_us()
106 vertical_blank_in_pixels = stream->timing.h_total * in dce110_get_min_vblank_time_us()
108 - stream->timing.v_addressable); in dce110_get_min_vblank_time_us()
110 * 10000 / stream->timing.pix_clk_100hz; in dce110_get_min_vblank_time_us()
163 cfg->v_refresh = stream->timing.pix_clk_100hz * 100; in dce110_fill_display_configs()
164 cfg->v_refresh /= stream->timing.h_total; in dce110_fill_display_configs()
165 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) in dce110_fill_display_configs()
166 / stream->timing.v_total; in dce110_fill_display_configs()
237 const struct dc_crtc_timing *timing = in dce11_pplib_apply_display_requirements() local
238 &context->streams[0]->timing; in dce11_pplib_apply_display_requirements()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/
H A Ddc_dsc.h75 const struct dc_crtc_timing *timing,
84 const struct dc_crtc_timing *timing,
88 uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
92 const struct dc_crtc_timing *timing,
101 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce80/
H A Ddce80_timing_generator.c109 const struct dc_crtc_timing *timing, in program_timing() argument
118 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
120 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); in program_timing()
126 const struct dc_crtc_timing *timing) in dce80_timing_generator_enable_advanced_request() argument
146 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce80_timing_generator_enable_advanced_request()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_hpo_dp.c52 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; in set_hpo_dp_hblank_min_symbol_width()
61 timing->h_total - timing->h_addressable), in set_hpo_dp_hblank_min_symbol_width()
62 dc_fixpt_from_fraction(timing->pix_clk_100hz, 10)); in set_hpo_dp_hblank_min_symbol_width()
98 &stream->timing, in setup_hpo_dp_stream_attribute()
101 stream->timing.flags.DSC, in setup_hpo_dp_stream_attribute()
50 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; set_hpo_dp_hblank_min_symbol_width() local
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c109 const struct dc_crtc_timing *timing, in program_timing() argument
118 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
120 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); in program_timing()
126 const struct dc_crtc_timing *timing) in dce60_timing_generator_enable_advanced_request() argument
138 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce60_timing_generator_enable_advanced_request()
/openbsd-src/sys/dev/sdmmc/
H A Dsdmmcchip.h68 #define sdmmc_chip_bus_clock(tag, handle, freq, timing) \ argument
69 ((tag)->bus_clock((handle), (freq), (timing)))
83 #define sdmmc_chip_execute_tuning(tag, handle, timing) \ argument
84 ((tag)->execute_tuning((handle), (timing)))
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c422 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top in pipe_ctx_to_e2e_pipe_params()
423 + pipe->stream->timing.v_border_bottom; in pipe_ctx_to_e2e_pipe_params()
431 input->dest.htotal = pipe->stream->timing.h_total; in pipe_ctx_to_e2e_pipe_params()
432 input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; in pipe_ctx_to_e2e_pipe_params()
434 - pipe->stream->timing.h_addressable in pipe_ctx_to_e2e_pipe_params()
435 - pipe->stream->timing.h_border_left in pipe_ctx_to_e2e_pipe_params()
436 - pipe->stream->timing.h_border_right; in pipe_ctx_to_e2e_pipe_params()
438 input->dest.vtotal = pipe->stream->timing.v_total; in pipe_ctx_to_e2e_pipe_params()
439 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing in pipe_ctx_to_e2e_pipe_params()
[all...]
/openbsd-src/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c782 struct dc_crtc_timing *timing;
831 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); in set_dsc_configs_from_fairness_vars()
837 params[i].timing, in set_dsc_configs_from_fairness_vars()
839 &params[i].timing->dsc_cfg)) { in set_dsc_configs_from_fairness_vars()
840 params[i].timing->flags.DSC = 1; in set_dsc_configs_from_fairness_vars()
843 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; in set_dsc_configs_from_fairness_vars()
845 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; in set_dsc_configs_from_fairness_vars()
848 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; in set_dsc_configs_from_fairness_vars()
851 params[i].timing in set_dsc_configs_from_fairness_vars()
778 struct dc_crtc_timing *timing; global() member
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