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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td290 def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
291 (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
294 def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
295 (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
408 def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
409 (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
410 def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
411 (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
412 def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
413 (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
20 IntRegsLow8:$src3),
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
39 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
40 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
42 HvxVR:$src3),
43 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
54 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
55 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
[all …]
H A DHexagonIntrinsicsV60.td171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
175 IntRegs:$src3),
176 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
184 IntRegs:$src3),
185 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
[all …]
H A DHexagonIntrinsics.td145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
207 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
208 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
212 HvxVR:$src3),
213 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
310 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
311 (MI HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>,
315 u3_0ImmPred:$src3),
317 u3_0ImmPred:$src3)>,
[all …]
H A DHexagonIntrinsicsV5.td178 u2_0ImmPred:$src3),
179 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrXOP.td172 (ins VR128:$src1, VR128:$src2, VR128:$src3),
174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
176 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V,
179 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
184 VR128:$src3))]>, XOP_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
218 (v8i16 VR128:$src3))),
219 (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>;
221 (v4i32 VR128:$src3))),
222 (VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
[all …]
H A DX86InstrAMX.td57 opaquemem:$src3), []>;
61 opaquemem:$src3), []>;
64 GR16:$src2, opaquemem:$src3,
92 (ins TILE:$src1, TILE:$src2, TILE:$src3),
93 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
96 (ins TILE:$src1, TILE:$src2, TILE:$src3),
97 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
100 (ins TILE:$src1, TILE:$src2, TILE:$src3),
101 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
104 (ins TILE:$src1, TILE:$src2, TILE:$src3),
[all …]
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
52 (MemFrag addr:$src3))))]>,
61 (ins RC:$src1, RC:$src2, RC:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrSSE.td2069 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2071 (i8 timm:$src3))))], d>,
2075 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2077 (i8 timm:$src3))))], d>,
2083 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2087 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2091 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2095 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2101 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2104 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrFragmentsSIMD.td201 def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3),
202 [(X86strict_cmpp node:$src1, node:$src2, node:$src3),
203 (X86cmpp node:$src1, node:$src2, node:$src3)]>;
220 def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3),
221 [(X86strict_cmpm node:$src1, node:$src2, node:$src3),
222 (X86cmpm node:$src1, node:$src2, node:$src3)]>;
542 def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3),
543 [(X86strict_Fnmadd node:$src1, node:$src2, node:$src3),
544 (X86Fnmadd node:$src1, node:$src2, node:$src3)]>;
547 def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3),
[all …]
H A DX86InstrAVX512.td560 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
562 "$src3, $src2, $src1", "$src1, $src2, $src3",
563 (vinsert_insert:$src3 (To.VT To.RC:$src1),
566 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
572 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
574 "$src3, $src2, $src1", "$src1, $src2, $src3",
575 (vinsert_insert:$src3 (To.VT To.RC:$src1),
578 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
835 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
836 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[all …]
H A DX86InstrShiftRotate.td706 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
707 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
709 (i8 imm:$src3)))]>,
713 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
714 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
716 (i8 imm:$src3)))]>,
720 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
721 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
723 (i8 imm:$src3)))]>,
727 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
[all …]
H A DX86InstrMMX.td111 (ins VR64:$src1, VR64:$src2, u8imm:$src3),
112 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
113 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
116 (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
119 (i8 timm:$src3)))]>,
526 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
527 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
529 GR32orGR64:$src2, timm:$src3))]>,
534 (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
37 : EXPCommon<0, done, "exp$tgt $src0, $src1, $src2, $src3"
45 : EXPCommon<row, done, "exp$tgt $src0, $src1, $src2, $src3"
131 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
134 ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
140 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
143 ExpSrc2:$src2, ExpSrc3:$src3, 0, 0, timm:$en)
H A DSIInstrFormats.td419 bits<8> src3;
428 let Inst{63-56} = src3;
/openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/lib/
H A Dcompat.exp144 regsub "_main" $src1 "_y" src3
207 compat-obj "$src3" "$obj3_alt" $alt_options $optstr
214 compat-obj "$src3" "$obj3_tst" $tst_options $optstr
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td654 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
655 (add (mul node:$src1, node:$src2), node:$src3)>;
684 def any_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
685 (any_fma node:$src1, node:$src2, (fneg node:$src3))>;
689 def z_any_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
690 (any_fma node:$src2, node:$src3, node:$src1)>;
691 def z_any_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
692 (any_fma node:$src2, node:$src3, (fneg node:$src1))>;
695 def any_fnma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
696 (fneg (any_fma node:$src1, node:$src2, node:$src3))>;
[all …]
/openbsd-src/gnu/llvm/llvm/docs/AMDGPU/
H A Dgfx8_vsrc_ba3116.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
H A Dgfx1030_vsrc_ba3116.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
H A Dgfx10_vsrc_ba3116.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
H A Dgfx7_vsrc_ba3116.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
H A Dgfx9_vsrc_ba3116.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
/openbsd-src/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td460 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
461 "crc32 $dst, $src2, $src3",
464 GRRegs:$src3))]>;
503 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
504 "ladd $dst2, $dst1, $src1, $src2, $src3",
508 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
509 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
512 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
513 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt256 v ← bfp_MULTIPLY_ADD(src1, src3, src2)
261 v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
266 v ← bfp_MULTIPLY_ADD(src1,src3,src2)
271 v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
/openbsd-src/gnu/gcc/gcc/
H A Dpostreload.c1332 rtx src3 = XEXP (SET_SRC (set), 1); in reload_cse_move2add() local
1333 HOST_WIDE_INT added_offset = INTVAL (src3); in reload_cse_move2add()
1348 < COSTS_N_INSNS (1) + rtx_cost (src3, SET)) in reload_cse_move2add()

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