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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
21 (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
22 def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),
23 (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
24 def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2),
25 (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
26 def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2),
27 (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
28 def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2),
29 (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
116 (MI HvxWR:$src1, IntRegs:$src2)>;
118 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
119 (MI HvxWR:$src1, IntRegs:$src2)>;
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
124 (MI HvxVR:$src1, IntRegs:$src2)>;
126 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
127 (MI HvxVR:$src1, IntRegs:$src2)>;
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132 (MI HvxWR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsics.td127 def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred_timm:$src2),
128 (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>;
130 def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred_timm:$src2),
131 (C2_tfrpr (C2_cmpgtui I32:$src1, (UDEC1 u32_0ImmPred:$src2)))>;
135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
136 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
138 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrXOP.td97 (ins VR128:$src1, VR128:$src2),
98 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
103 (ins VR128:$src1, i128mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
107 (vt128 (load addr:$src2)))))]>,
110 (ins i128mem:$src1, VR128:$src2),
111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
114 (vt128 VR128:$src2))))]>,
119 (ins VR128:$src1, VR128:$src2),
[all …]
H A DX86InstrAMX.td56 GR16:$src2,
60 GR16:$src2,
64 GR16:$src2, opaquemem:$src3,
68 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
70 GR16:$src1, GR16:$src2))]>;
76 def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
79 sibmem:$src2), []>;
92 (ins TILE:$src1, TILE:$src2, TILE:$src3),
93 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
96 (ins TILE:$src1, TILE:$src2, TILE:$src3),
[all …]
H A DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
33 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
35 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
36 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
37 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>,
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
51 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
[all …]
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
61 (ins RC:$src1, RC:$src2, RC:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrShiftRotate.td35 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
36 "shl{b}\t{$src2, $dst|$dst, $src2}",
37 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>,
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
44 "shl{l}\t{$src2, $dst|$dst, $src2}",
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>,
48 (ins GR64:$src1, u8imm:$src2),
[all …]
H A DX86InstrKL.td20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
21 "loadiwkey\t{$src2, $src1|$src1, $src2}",
22 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
40 def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
41 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
43 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
46 def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
47 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
49 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
52 def AESENC256KL : I<0xDE, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
[all …]
H A DX86InstrCMovSetCC.td20 : I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond),
21 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
26 : I<0x40, MRMSrcRegCC, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, ccode:$cond),
27 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
32 :RI<0x40, MRMSrcRegCC, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, ccode:$cond),
33 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
35 (X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
41 : I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond),
[all …]
H A DX86InstrCompiler.td714 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
716 "{$src2, $dst|$dst, $src2}"),
717 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;
721 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
723 "{$src2, $dst|$dst, $src2}"),
724 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,
729 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
731 "{$src2, $dst|$dst, $src2}"),
732 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,
737 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
[all …]
H A DX86InstrArithmetic.td154 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
155 "imul{w}\t{$src2, $dst|$dst, $src2}",
157 (X86smul_flag GR16:$src1, GR16:$src2))]>,
159 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
160 "imul{l}\t{$src2, $dst|$dst, $src2}",
162 (X86smul_flag GR32:$src1, GR32:$src2))]>,
165 (ins GR64:$src1, GR64:$src2),
166 "imul{q}\t{$src2, $dst|$dst, $src2}",
168 (X86smul_flag GR64:$src1, GR64:$src2))]>,
174 (ins GR16:$src1, i16mem:$src2),
[all …]
H A DX86InstrMMX.td38 (ins VR64:$src1, VR64:$src2),
39 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
40 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
45 (ins VR64:$src1, OType:$src2),
46 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
47 [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2)))]>,
56 (ins VR64:$src1, VR64:$src2),
57 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
58 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
61 (ins VR64:$src1, i64mem:$src2),
[all …]
H A DX86InstrAVX512.td193 def vselect_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2),
194 (vselect node:$mask, node:$src1, node:$src2), [{
198 def X86selects_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2),
199 (X86selects node:$mask, node:$src1, node:$src2), [{
560 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
562 "$src3, $src2, $src1", "$src1, $src2, $src3",
564 (From.VT From.RC:$src2),
567 (From.VT From.RC:$src2),
572 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
574 "$src3, $src2, $src1", "$src1, $src2, $src3",
[all …]
H A DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
27 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
28 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
30 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
H A DX86InstrVecCompiler.td416 def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))),
417 (ANDPSrm VR128:$src1, f128mem:$src2)>;
419 def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
420 (ANDPSrr VR128:$src1, VR128:$src2)>;
422 def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))),
423 (ORPSrm VR128:$src1, f128mem:$src2)>;
425 def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)),
426 (ORPSrr VR128:$src1, VR128:$src2)>;
428 def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))),
429 (XORPSrm VR128:$src1, f128mem:$src2)>;
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/cpu/
H A Dm32r.cpu248 ((src1 INT -1) (src2 INT -1)) ; inputs
255 ((src1 INT -1) (src2 INT -1)) ; inputs
278 ((src1 INT) (src2 INT)) ; inputs
314 ((src1 INT -1) (src2 INT -1)) ; inputs
321 ((src1 INT -1) (src2 INT -1)) ; inputs
342 ((src1 INT) (src2 INT)) ; inputs
367 ((src1 INT -1) (src2 INT -1)) ; inputs
374 ((src1 INT -1) (src2 INT -1)) ; inputs
395 ((src1 INT) (src2 INT)) ; inputs
659 (dnop src2 "source register 2" () h-gr f-r2)
[all …]
/openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/execute/
H A Dstring-opt-7.c18 const char *src2; in main() local
44 dst2 = dst; src2 = src; in main()
45 if (strncpy (++dst2, ++src2, 0) != dst+1 || strcmp (dst2, "") in main()
46 || dst2 != dst+1 || src2 != src+1) in main()
50 dst2 = dst; src2 = src; in main()
51 if (strncpy (++dst2+5, ++src2+5, 0) != dst+6 || strcmp (dst2+5, "") in main()
52 || dst2 != dst+1 || src2 != src+1) in main()
/openbsd-src/gnu/llvm/clang/lib/Headers/
H A Damxintrin.h255 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbssd_internal() argument
256 return __builtin_ia32_tdpbssd_internal(m, n, k, dst, src1, src2); in _tile_dpbssd_internal()
262 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbsud_internal() argument
263 return __builtin_ia32_tdpbsud_internal(m, n, k, dst, src1, src2); in _tile_dpbsud_internal()
269 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbusd_internal() argument
270 return __builtin_ia32_tdpbusd_internal(m, n, k, dst, src1, src2); in _tile_dpbusd_internal()
276 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbuud_internal() argument
277 return __builtin_ia32_tdpbuud_internal(m, n, k, dst, src1, src2); in _tile_dpbuud_internal()
291 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbf16ps_internal() argument
292 return __builtin_ia32_tdpbf16ps_internal(m, n, k, dst, src1, src2); in _tile_dpbf16ps_internal()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td225 // src1 = Denominator, src2 = Numerator).
231 // Denominator, src2 = Numerator).
327 SDTCisSameAs<4, 2>, // f32 src2
393 def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
394 [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
395 (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
397 def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
398 [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
399 (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
433 def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td619 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
620 (or (and node:$src1, -256), node:$src2)>;
621 def insertll : PatFrag<(ops node:$src1, node:$src2),
622 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
623 def insertlh : PatFrag<(ops node:$src1, node:$src2),
624 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
625 def inserthl : PatFrag<(ops node:$src1, node:$src2),
626 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
627 def inserthh : PatFrag<(ops node:$src1, node:$src2),
628 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
[all …]
/openbsd-src/gnu/llvm/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst66 …id_gfx906_src_1>`::ref:`f16x2<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
67 …id_gfx906_src_4>`::ref:`i16x2<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
68 …id_gfx906_src_4>`::ref:`u16x2<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
69 …id_gfx906_src_1>`::ref:`i8x4<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
70 …id_gfx906_src_1>`::ref:`u8x4<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
71 …id_gfx906_src_1>`::ref:`i4x8<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
72 …id_gfx906_src_1>`::ref:`u4x8<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
73 …amdgpu_synid_gfx906_m>`::ref:`fx<amdgpu_synid_gfx906_fx_operand>`, :ref:`src2<amdgpu_synid_gfx906…
74 …amdgpu_synid_gfx906_m>`::ref:`fx<amdgpu_synid_gfx906_fx_operand>`, :ref:`src2<amdgpu_synid_gfx906…
75 …amdgpu_synid_gfx906_m>`::ref:`fx<amdgpu_synid_gfx906_fx_operand>`, :ref:`src2<amdgpu_synid_gfx906…
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DGenericOpcodes.td99 let InOperandList = (ins unknown:$src2);
247 let InOperandList = (ins type0:$src1, type0:$src2);
255 let InOperandList = (ins type0:$src1, type0:$src2);
263 let InOperandList = (ins type0:$src1, type0:$src2);
271 let InOperandList = (ins type0:$src1, type0:$src2);
279 let InOperandList = (ins type0:$src1, type0:$src2);
287 let InOperandList = (ins type0:$src1, type0:$src2);
295 let InOperandList = (ins type0:$src1, type0:$src2);
303 let InOperandList = (ins type0:$src1, type0:$src2);
311 let InOperandList = (ins type0:$src1, type0:$src2);
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td189 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
192 (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>;
193 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
196 (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>;
449 let Constraints = "$src2 = $rd" in {
451 def 8rr : I8rr<opcode, (outs GR8:$rd), (ins GR8:$src2, GR8:$rs),
453 [(set GR8:$rd, (node GR8:$src2, GR8:$rs)),
455 def 16rr : I16rr<opcode, (outs GR16:$rd), (ins GR16:$src2, GR16:$rs),
457 [(set GR16:$rd, (node GR16:$src2, GR16:$rs)),
460 def 8rm : I8rm<opcode, (outs GR8:$rd), (ins GR8:$src2, memsrc:$src),
[all …]

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