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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_A2_abs IntRegs:$src1),
15 (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;
16 def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1),
17 (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>;
18 def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),
19 (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>;
20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
21 (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
22 def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),
23 (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
28 def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
H A DHexagonIntrinsics.td127 def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred_timm:$src2),
128 (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>;
130 def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred_timm:$src2),
131 (C2_tfrpr (C2_cmpgtui I32:$src1, (UDEC1 u32_0ImmPred:$src2)))>;
135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
136 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
138 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
[all …]
/openbsd-src/gnu/llvm/clang/lib/Headers/
H A Damxintrin.h153 #define _tile_dpbssd(dst, src0, src1) \ argument
154 __builtin_ia32_tdpbssd((dst), (src0), (src1))
172 #define _tile_dpbsud(dst, src0, src1) \ argument
173 __builtin_ia32_tdpbsud((dst), (src0), (src1))
191 #define _tile_dpbusd(dst, src0, src1) \ argument
192 __builtin_ia32_tdpbusd((dst), (src0), (src1))
210 #define _tile_dpbuud(dst, src0, src1) \ argument
211 __builtin_ia32_tdpbuud((dst), (src0), (src1))
228 #define _tile_dpbf16ps(dst, src0, src1) \ argument
229 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrXOP.td97 (ins VR128:$src1, VR128:$src2),
98 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
103 (ins VR128:$src1, i128mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
106 (vt128 (OpNode (vt128 VR128:$src1),
110 (ins i128mem:$src1, VR128:$src2),
111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
119 (ins VR128:$src1, VR128:$src2),
[all …]
H A DX86InstrShiftRotate.td17 let Constraints = "$src1 = $dst" in {
19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16;
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
35 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
[all …]
H A DX86InstrAMX.td55 def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
59 def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
63 def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
68 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
70 GR16:$src1, GR16:$src2))]>;
76 def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
78 def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
90 let Constraints = "$src1 = $dst" in {
92 (ins TILE:$src1, TILE:$src2, TILE:$src3),
96 (ins TILE:$src1, TILE:$src2, TILE:$src3),
[all …]
H A DX86InstrKL.td20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
21 "loadiwkey\t{$src2, $src1|$src1, $src2}",
22 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
38 let Constraints = "$src1 = $dst",
40 def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
41 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
43 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
46 def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
47 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
49 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
[all …]
H A DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
33 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
36 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
37 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>,
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
52 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
53 [(set RC:$dst, (VT (OpNode RC:$src1, RC:$src2)))], d>,
56 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
[all …]
H A DX86InstrCompiler.td900 def 16m : Ii8<0xBA, Form, (outs), (ins i16mem:$src1, i8imm:$src2),
901 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"),
902 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 16)))]>,
904 def 32m : Ii8<0xBA, Form, (outs), (ins i32mem:$src1, i8imm:$src2),
905 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"),
906 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 32)))]>,
908 def 64m : RIi8<0xBA, Form, (outs), (ins i64mem:$src1, i8imm:$src2),
909 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"),
910 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 64)))]>,
918 def 16rm : I<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
[all …]
H A DX86InstrArithmetic.td149 let Constraints = "$src1 = $dst" in {
154 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
157 (X86smul_flag GR16:$src1, GR16:$src2))]>,
159 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
162 (X86smul_flag GR32:$src1, GR32:$src2))]>,
165 (ins GR64:$src1, GR64:$src2),
168 (X86smul_flag GR64:$src1, GR64:$src2))]>,
174 (ins GR16:$src1, i16mem:$src2),
177 (X86smul_flag GR16:$src1, (loadi16 addr:$src2)))]>,
180 (ins GR32:$src1, i32mem:$src2),
[all …]
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
61 (ins RC:$src1, RC:$src2, RC:$src3),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
72 RC:$src1)))]>,
81 (ins RC:$src1, RC:$src2, RC:$src3),
90 (ins RC:$src1, RC:$src2, x86memop:$src3),
93 [(set RC:$dst, (VT (Op (MemFrag addr:$src3), RC:$src1,
[all …]
H A DX86InstrAVX512.td193 def vselect_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2),
194 (vselect node:$mask, node:$src1, node:$src2), [{
198 def X86selects_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2),
199 (X86selects node:$mask, node:$src1, node:$src2), [{
325 // ($src1) is already tied to $dst so we just use that for the preserved
327 // $src1.
337 !con((ins _.RC:$src1), NonTiedIns),
338 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
339 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
342 (Select _.KRCWM:$mask, RHS, _.RC:$src1),
[all …]
H A DX86InstrCMovSetCC.td17 let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
20 : I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond),
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
26 : I<0x40, MRMSrcRegCC, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, ccode:$cond),
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
32 :RI<0x40, MRMSrcRegCC, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, ccode:$cond),
35 (X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
38 let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
41 : I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond),
43 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
[all …]
H A DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
27 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
28 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
30 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td185 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
188 // out = (src1 > src0) ? 1 : 0
225 // src1 = Denominator, src2 = Numerator).
230 // Special case divide fixup and flags(src0 = Quotient, src1 =
250 // src1: dst - rat offset (aka pointer) in dwords
326 SDTCisSameAs<3, 2>, // f32 src1
385 def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
386 [(int_amdgcn_ldexp node:$src0, node:$src1),
387 (AMDGPUldexp_impl node:$src0, node:$src1)]>;
389 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
[all …]
H A DAMDGPUInstructions.td175 (ops node:$src0, node:$src1),
176 (op $src0, $src1),
184 (ops node:$src0, node:$src1, node:$src2),
185 (op $src0, $src1, $src2),
193 (ops node:$src0, node:$src1),
194 (op $src0, $src1),
269 def cshl_#width : PatFrags<(ops node:$src0, node:$src1),
270 [(shl node:$src0, node:$src1), (shl node:$src0, (csh_mask node:$src1))]>;
273 def clshl_rev_#width : PatFrag <(ops node:$src0, node:$src1),
274 (cshl $src1, $src0)>;
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/
H A Dbfin-dis.c471 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf) in decode_multfunc() argument
481 s1 = dregs_hi (src1); in decode_multfunc()
483 s1 = dregs_lo (src1); in decode_multfunc()
492 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf) in decode_macfunc() argument
520 decode_multfunc (h0, h1, src0, src1, outf); in decode_macfunc()
1435 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask); in decode_COMP3op_0() local
1437 if (opc == 5 && src1 == src0) in decode_COMP3op_0()
1450 OUTS (outf, dregs (src1)); in decode_COMP3op_0()
1458 OUTS (outf, dregs (src1)); in decode_COMP3op_0()
1466 OUTS (outf, dregs (src1)); in decode_COMP3op_0()
[all …]
/openbsd-src/gnu/llvm/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX90a.rst973 …_gfx90a_src_d578c4>`::ref:`m<amdgpu_synid_gfx90a_m_28b494>`, :ref:`src1<amdgpu_synid_gfx90a…
976 …_gfx90a_src_d578c4>`::ref:`m<amdgpu_synid_gfx90a_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx90a…
979 …_gfx90a_src_d578c4>`::ref:`m<amdgpu_synid_gfx90a_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx90a…
982 …_gfx90a_src_d95796>`::ref:`m<amdgpu_synid_gfx90a_m_28b494>`, :ref:`src1<amdgpu_synid_gfx90a…
985 …_gfx90a_src_d578c4>`::ref:`m<amdgpu_synid_gfx90a_m_28b494>`, :ref:`src1<amdgpu_synid_gfx90a…
988 …_gfx90a_src_d578c4>`::ref:`m<amdgpu_synid_gfx90a_m_28b494>`, :ref:`src1<amdgpu_synid_gfx90a…
991 …_gfx90a_src_d578c4>`::ref:`m<amdgpu_synid_gfx90a_m_28b494>`, :ref:`src1<amdgpu_synid_gfx90a…
994 …fx90a_m_28b494>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a…
997 …fx90a_m_28b494>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a…
1000 …_gfx90a_src_d578c4>`::ref:`m<amdgpu_synid_gfx90a_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx90a…
[all …]
H A DAMDGPUAsmGFX7.rst784 …0<amdgpu_synid_gfx7_src_d56c56>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src1<amdgpu_synid_gfx7_s…
785 …0<amdgpu_synid_gfx7_src_3865f6>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src1<amdgpu_synid_gfx7_s…
786 …sdst_9172f3>`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`, :ref:`src1<amdgpu_synid_gfx7_s…
787 …sdst_9172f3>`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`, :ref:`src1<amdgpu_synid_gfx7_s…
788 …`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`, :ref:`src1<amdgpu_synid_gfx7_s…
789 …`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`, :ref:`src1<amdgpu_synid_gfx7_s…
790 …`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`, :ref:`src1<amdgpu_synid_gfx7_s…
791 …`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`, :ref:`src1<amdgpu_synid_gfx7_s…
792 …`, :ref:`src0<amdgpu_synid_gfx7_src_3865f6>`, :ref:`src1<amdgpu_synid_gfx7_s…
793 …d_gfx7_src_8e54a0>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`src1<amdgpu_synid_gfx7_s…
[all …]
H A DAMDGPUAsmGFX9.rst1063 …u_synid_gfx9_src_d578c4>`::ref:`m<amdgpu_synid_gfx9_m_28b494>`, :ref:`src1<amdgpu_synid_gfx9_s…
1066 …u_synid_gfx9_src_d578c4>`::ref:`m<amdgpu_synid_gfx9_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx9_s…
1069 …u_synid_gfx9_src_d578c4>`::ref:`m<amdgpu_synid_gfx9_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx9_s…
1072 …u_synid_gfx9_src_d95796>`::ref:`m<amdgpu_synid_gfx9_m_28b494>`, :ref:`src1<amdgpu_synid_gfx9_s…
1075 …u_synid_gfx9_src_d578c4>`::ref:`m<amdgpu_synid_gfx9_m_28b494>`, :ref:`src1<amdgpu_synid_gfx9_s…
1078 …u_synid_gfx9_src_d578c4>`::ref:`m<amdgpu_synid_gfx9_m_28b494>`, :ref:`src1<amdgpu_synid_gfx9_s…
1081 …u_synid_gfx9_src_d578c4>`::ref:`m<amdgpu_synid_gfx9_m_28b494>`, :ref:`src1<amdgpu_synid_gfx9_s…
1084 …synid_gfx9_m_28b494>`::ref:`u16<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_s…
1087 …synid_gfx9_m_28b494>`::ref:`u32<amdgpu_synid_gfx9_type_deviation>`, :ref:`src1<amdgpu_synid_gfx9_s…
1090 …u_synid_gfx9_src_d578c4>`::ref:`m<amdgpu_synid_gfx9_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx9_s…
[all …]
H A DAMDGPUAsmGFX940.rst969 …_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_28b494>`, :ref:`src1<amdgpu_synid_gfx940…
972 …_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx940…
975 …_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx940…
978 …_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_28b494>`, :ref:`src1<amdgpu_synid_gfx940…
981 …_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_28b494>`, :ref:`src1<amdgpu_synid_gfx940…
984 …_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_28b494>`, :ref:`src1<amdgpu_synid_gfx940…
987 …_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_28b494>`, :ref:`src1<amdgpu_synid_gfx940…
990 …fx940_m_28b494>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940…
993 …fx940_m_28b494>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940…
996 …_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx940…
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DGenericOpcodes.td247 let InOperandList = (ins type0:$src1, type0:$src2);
255 let InOperandList = (ins type0:$src1, type0:$src2);
263 let InOperandList = (ins type0:$src1, type0:$src2);
271 let InOperandList = (ins type0:$src1, type0:$src2);
279 let InOperandList = (ins type0:$src1, type0:$src2);
287 let InOperandList = (ins type0:$src1, type0:$src2);
295 let InOperandList = (ins type0:$src1, type0:$src2);
303 let InOperandList = (ins type0:$src1, type0:$src2);
311 let InOperandList = (ins type0:$src1, type0:$src2);
319 let InOperandList = (ins type0:$src1, type0:$src2);
[all …]
/openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/lib/
H A Dcompat.exp117 proc compat-execute { src1 use_alt } {
129 set tmp [grep $src1 "{\[ \t\]\*dg-options.*\[ \t\]\+}"]
141 regsub "_main.*" $src1 "" base
143 regsub "_main" $src1 "_x" src2
144 regsub "_main" $src1 "_y" src3
154 regsub "^$srcdir/?" $src1 "" testcase
164 set testcase "[file tail [file dirname $src1]]/[file tail $src1]"
212 compat-obj "$src1" "$obj1" $tst_options $optstr

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