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Searched refs:set_reg (Results 1 – 6 of 6) sorted by relevance

/openbsd-src/sys/dev/pci/drm/radeon/
H A Dradeon_asic.c236 .set_reg = r100_set_surface_reg,
304 .set_reg = r100_set_surface_reg,
400 .set_reg = r100_set_surface_reg,
468 .set_reg = r100_set_surface_reg,
536 .set_reg = r100_set_surface_reg,
604 .set_reg = r100_set_surface_reg,
672 .set_reg = r100_set_surface_reg,
740 .set_reg = r100_set_surface_reg,
808 .set_reg = r100_set_surface_reg,
876 .set_reg = r100_set_surface_reg,
[all …]
H A Dradeon.h1943 int (*set_reg)(struct radeon_device *rdev, int reg, member
2792 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
/openbsd-src/gnu/usr.bin/gcc/gcc/config/ia64/
H A Dunwind-ia64.c462 set_reg (struct unw_reg_info *reg, enum unw_where where, in set_reg() function
607 set_reg (sr->curr.reg + save_order[i], UNW_WHERE_GR, in desc_prologue()
639 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_GR, in desc_br_gr()
654 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_SPILL_HOME, in desc_br_mem()
672 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, in desc_frgr_mem()
683 set_reg (sr->curr.reg + base + i, UNW_WHERE_SPILL_HOME, in desc_frgr_mem()
700 set_reg (sr->curr.reg + UNW_REG_F2 + i, UNW_WHERE_SPILL_HOME, in desc_fr_mem()
717 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_GR, in desc_gr_gr()
732 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, in desc_gr_mem()
743 set_reg (sr->curr.reg + UNW_REG_PSP, UNW_WHERE_NONE, in desc_mem_stack_f()
[all …]
/openbsd-src/gnu/gcc/gcc/config/ia64/
H A Dunwind-ia64.c467 set_reg (struct unw_reg_info *reg, enum unw_where where, in set_reg() function
612 set_reg (sr->curr.reg + save_order[i], UNW_WHERE_GR, in desc_prologue()
644 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_GR, in desc_br_gr()
659 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_SPILL_HOME, in desc_br_mem()
677 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, in desc_frgr_mem()
688 set_reg (sr->curr.reg + base + i, UNW_WHERE_SPILL_HOME, in desc_frgr_mem()
705 set_reg (sr->curr.reg + UNW_REG_F2 + i, UNW_WHERE_SPILL_HOME, in desc_fr_mem()
722 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_GR, in desc_gr_gr()
737 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, in desc_gr_mem()
748 set_reg (sr->curr.reg + UNW_REG_PSP, UNW_WHERE_NONE, in desc_mem_stack_f()
[all …]
/openbsd-src/gnu/gcc/gcc/config/iq2000/
H A Diq2000.c333 rtx set_reg; in iq2000_fill_delay_slot() local
358 || (set_reg = operands[0]) == 0) in iq2000_fill_delay_slot()
369 set_reg = operands[0]; in iq2000_fill_delay_slot()
370 if (set_reg == 0) in iq2000_fill_delay_slot()
373 while (GET_CODE (set_reg) == SUBREG) in iq2000_fill_delay_slot()
374 set_reg = SUBREG_REG (set_reg); in iq2000_fill_delay_slot()
376 mode = GET_MODE (set_reg); in iq2000_fill_delay_slot()
378 iq2000_load_reg = set_reg; in iq2000_fill_delay_slot()
381 iq2000_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1); in iq2000_fill_delay_slot()
/openbsd-src/gnu/usr.bin/gcc/gcc/config/mips/
H A Dmips.c1817 register rtx set_reg; local
1844 || (set_reg = operands[0]) == 0)
1854 set_reg = operands[0];
1855 if (set_reg == 0)
1858 while (GET_CODE (set_reg) == SUBREG)
1859 set_reg = SUBREG_REG (set_reg);
1861 mode = GET_MODE (set_reg);
1863 mips_load_reg = set_reg;
1865 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1866 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);