Home
last modified time | relevance | path

Searched refs:setRegClass (Results 1 – 25 of 29) sorted by relevance

12

/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp183 MRI.setRegClass(Reg, &SPIRV::IDRegClass); in propagateSPIRVType()
205 MRI.setRegClass(NewReg, RC); in insertAssignInstr()
220 MRI.setRegClass(Reg, &SPIRV::ANYIDRegClass); in insertAssignInstr()
326 MRI.setRegClass(IdReg, DstClass); in createNewIdReg()
377 MRI.setRegClass(DstReg, &SPIRV::IDRegClass); in processInstrsWithTypeFolding()
459 MRI.setRegClass(Dst, &SPIRV::IDRegClass); in processSwitches()
H A DSPIRVCallLowering.cpp306 MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass); in lowerFormalArguments()
326 MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass); in lowerFormalArguments()
H A DSPIRVGlobalRegistry.cpp65 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
71 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp57 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
79 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
141 setRegClass(Reg, NewRC); in recomputeRegClass()
H A DRegisterBankInfo.cpp143 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
H A DTailDuplicator.cpp425 MRI->setRegClass(VI->second.Reg, ConstrRC); in duplicateInstruction()
H A DMachineLICM.cpp1359 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
H A DRegisterCoalescer.cpp1443 MRI->setRegClass(DstReg, NewRC); in reMaterializeTrivialDef()
2083 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); in joinCopy()
H A DModuloSchedule.cpp1920 MRI.setRegClass(R, MRI.getRegClass(PhiR)); in rewriteUsesOf()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp411 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1314 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1318 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1331 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1340 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2427 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2429 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
H A DPPCMIPeephole.cpp997 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp179 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp240 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
292 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
812 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
H A DSILowerI1Copies.cpp564 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
694 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
H A DSIFoldOperands.cpp1720 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
1722 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
1728 MRI->setRegClass(Reg, TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg))); in tryFoldLoad()
H A DAMDGPUInstructionSelector.cpp172 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
446 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass); in selectG_UADDO_USUBO_UADDE_USUBE()
1077 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1508 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectEndCfIntrinsic()
2094 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
2762 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
H A DAMDGPULegalizerInfo.cpp1848 MRI.setRegClass(Dst, &AMDGPU::SReg_64RegClass); in getSegmentAperture()
2482 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
5613 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
5614 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
5649 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
H A DSIISelLowering.cpp12138 MRI.setRegClass(Op.getReg(), NewRC); in AdjustInstrPostInstrSelection()
12147 MRI.setRegClass(Src2->getReg(), NewRC); in AdjustInstrPostInstrSelection()
12149 MRI.setRegClass(MI.getOperand(0).getReg(), NewRC); in AdjustInstrPostInstrSelection()
12587 MRI.setRegClass(Reg, TRI->getRegClass(NewClassID)); in finalizeLowering()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1320 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass); in foldMemoryOperandImpl()
1322 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass); in foldMemoryOperandImpl()
1324 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass); in foldMemoryOperandImpl()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp508 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h700 void setRegClass(Register Reg, const TargetRegisterClass *RC);
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1015 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
1037 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp688 MRI.setRegClass(Reg, Info.D.RC); in setupRegisterInfo()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp659 MRI->setRegClass(NewVReg, SRC); in EmitRegSequence()

12