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Searched refs:regClass (Results 1 – 5 of 5) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td155 class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
158 RegisterOperand vdata_op = getLdStRegisterOperand<regClass>.ret> : FLAT_Pseudo<
201 multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
203 def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
205 def _SADDR : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1>,
210 class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
213 (outs regClass:$vdst),
216 !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
231 multiclass FLAT_Global_Load_AddTid_Pseudo<string opName, RegisterClass regClass,
233 def "" : FLAT_Global_Load_AddTid_Pseudo<opName, regClass, HasTiedOutput>,
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H A DSIWholeQuadMode.cpp1499 const TargetRegisterClass *regClass = in lowerCopyInstrs() local
1501 if (TRI->isVGPRClass(regClass)) { in lowerCopyInstrs()
1502 const unsigned MovOp = TII->getMovOpcode(regClass); in lowerCopyInstrs()
H A DSIInstrInfo.cpp8436 const TargetRegisterClass *regClass = RI.getPhysRegBaseClass(srcOp.getReg()); in getInstructionUniformity() local
8437 return RI.isSGPRClass(regClass) ? InstructionUniformity::AlwaysUniform in getInstructionUniformity()
8466 const TargetRegisterClass *regClass = RI.getPhysRegBaseClass(srcOp.getReg()); in getInstructionUniformity() local
8467 if (RI.isVGPRClass(regClass)) in getInstructionUniformity()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h797 int16_t regClass = Desc.operands()[OpNo].RegClass; in getRegNumForOperand() local
798 switch (regClass) { in getRegNumForOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td131 class MemOperand<RegisterClass regClass> : RegisterOperand<regClass>{