offset0 (reference) in projects: openbsd-src

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Searched refs:offset0 (Results 1 – 17 of 17) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A D	DSInstructions.td	43 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1 84 bits<8> offset0; 88 let offset0 = !if(ps.has_offset, offset{7-0}, ?); 162 offset0:$offset0, offset1:$offset1, gds:$gds), 163 " $addr, $data0, $data1$offset0$offset1$gds"> { 261 (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset0:$offset0, offset1:$offset1, gds:$gds), 262 " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> { 322 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds), 323 " $vdst, $addr$offset0$offset1$gds"> { 856 (vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))), [all …]
H A D	SIInstrInfo.td	`1234 def offset0 : NamedIntOperand<i8, "offset0", "Offset0">;`
H A D	SIInstrInfo.cpp	`328 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandsWithOffsetWidth()`
/openbsd-src/gnu/usr.bin/binutils/gdb/
H A D	go32-nat.c	`1275 unsigned short offset0 __attribute__((packed)); member 1413 gate.selector, gate.offset1, gate.offset0); in display_descriptor() 1425 gate.selector, gate.offset1, gate.offset0); in display_descriptor() 1437 gate.selector, gate.offset1, gate.offset0); in display_descriptor() 1445 gate.selector, gate.offset1, gate.offset0); in display_descriptor()`
/openbsd-src/gnu/llvm/llvm/docs/
H A D	AMDGPUModifierSyntax.rst	`30 offset0 subsection 40 offset0:{0..0xFF} Specifies an unsigned 8-bit offset as a positive 49 offset0:0xff 50 offset0:2-x 51 offset0:-x-y`
H A D	AMDGPUUsage.rst	`14416 ds_write_src2_b64 v2 offset0:4 offset1:8`
/openbsd-src/gnu/llvm/llvm/docs/AMDGPU/
H A D	AMDGPUAsmGFX7.rst	130 …addr<amdgpu_synid_gfx7_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 131 …addr<amdgpu_synid_gfx7_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 132 …addr<amdgpu_synid_gfx7_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 133 …addr<amdgpu_synid_gfx7_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 154 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx7_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 155 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx7_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 156 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx7_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 157 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx7_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 166 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx7_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 167 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx7_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… [all …]
H A D	AMDGPUAsmGFX8.rst	135 …addr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 136 …addr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 137 …addr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 138 …addr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 161 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx8_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 162 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx8_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 163 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx8_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 164 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx8_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 173 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx8_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 174 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx8_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… [all …]
H A D	AMDGPUAsmGFX11.rst	81 …ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 82 …ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 83 …ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 84 …ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 135 …ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 136 …ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 137 …ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 138 …ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 158 …ta0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx11_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 159 …ta0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx11_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… [all …]
H A D	AMDGPUAsmGFX9.rst	135 …addr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 136 …addr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 137 …addr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 138 …addr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 168 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 169 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 170 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 171 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 183 …6802ce>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 184 …fd235e>`, :ref:`vdata1<amdgpu_synid_gfx9_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… [all …]
H A D	AMDGPUAsmGFX90a.rst	113 …dr<amdgpu_synid_gfx90a_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 114 …dr<amdgpu_synid_gfx90a_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 115 …dr<amdgpu_synid_gfx90a_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 116 …dr<amdgpu_synid_gfx90a_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 142 …4895>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_o… 143 …d749>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_o… 144 …4895>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_o… 145 …d749>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_o… 155 …4895>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_o… 156 …d749>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_o… [all …]
H A D	AMDGPUAsmGFX1030.rst	330 …r<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 331 …r<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 332 …r<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 333 …r<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 359 …2ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 360 …35e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 361 …2ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 362 …35e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 372 …2ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 373 …35e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… [all …]
H A D	AMDGPUAsmGFX10.rst	349 …ddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 350 …ddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 351 …ddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 352 …ddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 382 …802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 383 …d235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 384 …802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 385 …d235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… 397 …802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_o… 398 …d235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_o… [all …]
H A D	AMDGPUAsmGFX940.rst	117 …dr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 118 …dr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 119 …dr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 120 …dr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_o… 146 …4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_o… 147 …d749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_o… 148 …4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_o… 149 …d749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_o… 159 …4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_o… 160 …d749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_o… [all …]
/openbsd-src/gnu/usr.bin/gcc/gcc/config/d30v/
H A D	d30v.c	`2719 int offset0 = 0; local 2723 offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)), 2742 fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix);`
/openbsd-src/sys/dev/pci/drm/amd/amdkfd/
H A D	cwsr_trap_handler_gfx9.asm	`560 ds_read2_b32 v[0:1], v2 offset0:0 offset1:0x40`
/openbsd-src/gnu/gcc/gcc/
H A D	fold-const.c	`8029 tree base0, offset0, base1, offset1; in fold_comparison() local 8031 if (extract_array_ref (arg0, &base0, &offset0) in fold_comparison() 8043 if (offset0 == NULL_TREE) in fold_comparison() 8044 offset0 = build_int_cst (signed_size_type_node, 0); in fold_comparison() 8046 offset0 = fold_convert (signed_size_type_node, offset0); in fold_comparison() 8052 return fold_build2 (code, type, offset0, offset1); in fold_comparison()`