| /openbsd-src/gnu/llvm/llvm/docs/ |
| H A D | Atomics.rst | 95 Note that speculative loads are allowed; a load which is part of a race returns 101 For cases where simple loads and stores are not sufficient, LLVM provides 106 non-atomic loads and stores, but provide additional guarantees in situations 144 location, loads from that location return undef. 152 The rule is essentially that all memory accessed with basic loads and stores 156 variable. Note that NotAtomic volatile loads and stores are not properly 162 Introducing loads to shared variables along a codepath where they would not 193 platforms for loads of a native width, but can be expensive or unavailable for 194 wider loads, like a 64-bit store on ARM. (A frontend for Java or other "safe" 200 single load into multiple loads, transforms a store into multiple stores, [all …]
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| H A D | SpeculativeLoadHardening.md | 54 branches and/or loads inside especially risky software (most notably various OS 63 The specific technique we propose is to cause loads to be checked using 66 predicate guarding potentially invalid loads: 153 * To achieve reasonable performance, many loads may not be checked, such as 160 * [Hardened loads](#hardening-the-address-of-the-load) may still load data from 167 block misspeculated loads was developed as part of a HACS 2018 discussion 231 use that validation to check that loads cannot leak information along 267 *implicitly* loads the return address off the stack. However, the 302 Mitigating this requires hardening loads from these locations, or mitigating 329 checking the loads, and checking control transfers between procedures. [all …]
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| H A D | BigEndianNEON.rst | 11 Generating code for big endian ARM processors is for the most part straightforward. NEON loads and … 13 The aim of this document is to explain the problem with NEON loads and stores, and the solution tha… 71 It may seem that ``LD1`` should suffice to peform vector loads on a big endian machine. However the… 84 … throughout this section we only mention loads. Stores have exactly the same problems as their ass… 159 …ructions so that they are never allowed to be selected to generate vector loads and stores. The ex…
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| /openbsd-src/gnu/llvm/llvm/lib/Analysis/models/ |
| H A D | log_reader.py | 81 header = json.loads(f.readline()) 87 event = json.loads(event_str) 98 score_header = json.loads(f.readline())
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrAtomics.td | 118 // Atomic loads 129 // Select loads 133 // Extending loads. Note that there are only zero-extending atomic loads, no 134 // sign-extending loads. 141 // Fragments for extending loads. These are different from regular loads because 146 // Unlike regular loads, extension to i64 is handled differently than i32. 149 // Extension to i32 is elided by SelectionDAG as our atomic loads are 161 // We don't have single sext atomic load instructions. So for sext loads, we 162 // match bare subword loads (for 32-bit results) and anyext loads (for 64-bit 170 // Select zero-extending loads [all …]
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| /openbsd-src/distrib/notes/i386/ |
| H A D | contents | 26 cdbr First-stage CD bootstrap (boot sector), which loads 33 then loads the bsd.rd installation ramdisk kernel.
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonShuffler.cpp | 374 if (Summary.loads == 1 && Summary.loads == Summary.memory && in restrictStoreLoadOrder() 390 else if (Summary.loads >= 1 && isMemReorderDisabled()) { // }:mem_noshuf in restrictStoreLoadOrder() 414 (Summary.loads == 0) || in restrictStoreLoadOrder() 497 ++Summary.loads; in GetPacketSummary() 523 ++Summary.loads; in GetPacketSummary() 535 ++Summary.loads; in GetPacketSummary()
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| /openbsd-src/distrib/notes/amd64/ |
| H A D | contents | 26 cdbr First-stage CD bootstrap (boot sector), which loads 33 then loads the bsd.rd installation ramdisk kernel.
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrAtomics.td | 22 // Atomic loads 53 // 8-bit loads 55 // 16-bit loads 57 // 32-bit loads 59 // 64-bit loads 63 // 8-bit loads 79 // 16-bit loads 95 // 32-bit loads 111 // 64-bit loads 127 // FP 32-bit loads [all …]
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| /openbsd-src/gnu/llvm/lldb/bindings/python/ |
| H A D | lldb-python | 12 info = json.loads(info_json)
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| /openbsd-src/gnu/llvm/llvm/utils/ |
| H A D | merge-stats.py | 22 data = json.loads(text)
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| /openbsd-src/gnu/usr.bin/perl/cpan/Math-BigInt/t/ |
| H A D | use_lib1.t | |
| H A D | use_lib6.t | |
| H A D | use_lib5.t | |
| H A D | use_lib2.t | |
| H A D | use_lib4.t | |
| /openbsd-src/gnu/llvm/lldb/source/Plugins/DynamicLoader/Darwin-Kernel/ |
| H A D | DynamicLoaderDarwinKernelProperties.td | 7 Desc<"Automatically loads kext images when attaching to a kernel.">;
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| /openbsd-src/gnu/llvm/llvm/docs/Frontend/ |
| H A D | PerformanceTips.rst | 67 Avoid loads and stores of large aggregate type 70 LLVM currently does not optimize well loads and stores of large :ref:`aggregate 103 ARM ISAs) then the hardware does not handle unaligned loads and stores, and 106 sequence of loads, shifts and masks (or load-right + load-left on MIPS) for 120 Note that if your loads and stores are atomic, the backend will be unable to 122 As a result, alignment is mandatory for atomic loads and stores. 153 be limited for loads not in the header. (This is due to the fact that LLVM
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| /openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/execute/ |
| H A D | 20020720-1.x | 6 # insn performs abs, 1 insn loads 0.0, 1 insn sets CCmode flags based
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM55.td | 29 // loads) actually take 1 cycle (amazingly). 41 // But a sequence of VLDR;VLDRB;VADD;VSTR because the loads cannot overlap, 314 // Normal loads 316 // Pre/post inc loads 318 // Gather loads 322 // Interleaving loads 324 // Interleaving loads with wb
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | Relocation.txt | 81 "lw" loads a 32 bit value from memory. On MIPS64, "lw" loads a 32 bit
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| /openbsd-src/gnu/llvm/llvm/include/llvm/IR/ |
| H A D | IntrinsicsBPF.td | 13 // Specialized loads from packet
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| /openbsd-src/gnu/llvm/llvm/include/llvm/Target/GlobalISel/ |
| H A D | SelectionDAGCompat.td | 32 // SelectionDAG has one node for all loads and uses predicates to 166 // G_LOAD handles both atomic and non-atomic loads where as SelectionDAG had 167 // separate nodes for them. This GINodeEquiv maps the non-atomic loads to
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| /openbsd-src/gnu/llvm/clang/docs/HLSL/ |
| H A D | ResourceTypes.rst | 23 specifies the expected return type of resource loads, and the expected parameter
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| /openbsd-src/gnu/llvm/llvm/utils/llvm-locstats/ |
| H A D | llvm-locstats.py | 12 from json import loads 210 json_parsed = loads(cmd_stdout)
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