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Searched refs:isVirtual (Results 1 – 25 of 264) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp138 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
186 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
207 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
238 if (Reg0.isVirtual()) { in runOnMachineFunction()
H A DHexagonGenPredicate.cpp138 if (!R.isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
216 if (RD.R.isVirtual()) in collectPredicateGPR()
248 assert(Reg.R.isVirtual()); in getPredRegFor()
474 if (!DR.R.isVirtual()) in eliminatePredCopies()
476 if (!SR.R.isVirtual()) in eliminatePredCopies()
/openbsd-src/gnu/llvm/clang/lib/AST/
H A DInheritViz.cpp100 if (!Base.isVirtual()) in WriteNode()
104 WriteNode(Base.getType(), Base.isVirtual()); in WriteNode()
110 WriteNodeReference(Base.getType(), Base.isVirtual()); in WriteNode()
113 if (Base.isVirtual()) { in WriteNode()
H A DVTTBuilder.cpp64 if (I.isVirtual()) in LayoutSecondaryVTTs()
109 if (I.isVirtual()) { in LayoutSecondaryVirtualPointers()
161 if (I.isVirtual()) { in LayoutVirtualVTTs()
H A DCXXInheritance.cpp186 if (BaseSpec.isVirtual()) { in lookupInBases()
203 if (BaseSpec.isVirtual()) in lookupInBases()
331 if (!PE.Base->isVirtual()) in lookupInBases()
376 return Specifier->isVirtual() && in FindVirtualBaseClass()
525 if (Overriders.empty() && !Base.isVirtual()) { in Collect()
539 if (Base.isVirtual()) { in Collect()
569 if (!M->isVirtual()) in Collect()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DVirtRegMap.h106 assert(virtReg.isVirtual()); in getPhys()
121 assert(virtReg.isVirtual()); in getShape()
132 assert(virtReg.isVirtual()); in clearVirt()
188 assert(virtReg.isVirtual()); in getStackSlot()
H A DMachineRegisterInfo.h114 if (RegNo.isVirtual()) in getRegUseDefListHead()
120 if (RegNo.isVirtual()) in getRegUseDefListHead()
230 assert(VReg.isVirtual() && "Must pass a VReg"); in shouldTrackSubRegLiveness()
760 if (Reg.isVirtual() && VRegToType.inBounds(Reg)) in getType()
793 assert(VReg.isVirtual()); in setRegAllocationHint()
802 assert(VReg.isVirtual()); in addRegAllocationHint()
823 assert(VReg.isVirtual()); in getRegAllocationHint()
833 assert(VReg.isVirtual()); in getSimpleHint()
842 assert(VReg.isVirtual()); in getRegAllocationHints()
1242 if (RegUnit.isVirtual()) { in PSetIterator()
H A DRegister.h78 assert(Reg.isVirtual() && "Not a virtual register"); in virtReg2Index()
91 bool isVirtual() const { in isVirtual() function
/openbsd-src/gnu/llvm/clang/lib/CodeGen/
H A DCGCall.h174 if (isVirtual()) in getAbstractInfo()
189 bool isVirtual() const { in isVirtual() function
193 assert(isVirtual()); in getVirtualCallExpr()
197 assert(isVirtual()); in getVirtualMethodDecl()
201 assert(isVirtual()); in getThisAddress()
205 assert(isVirtual()); in getVirtualFunctionType()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DMachineCSE.cpp182 if (!Reg.isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
189 if (!SrcReg.isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
300 if (Reg.isVirtual()) in hasLivePhysRegDefUses()
320 if (Reg.isVirtual()) in hasLivePhysRegDefUses()
395 if (MOReg.isVirtual()) in PhysRegDefsReach()
451 if (CSReg.isVirtual() && Reg.isVirtual()) { in isProfitableToCSE()
487 if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual()) { in isProfitableToCSE()
651 assert(OldReg.isVirtual() && NewReg.isVirtual() && in ProcessBlockCSE()
814 if (MO.isReg() && !MO.getReg().isVirtual()) { in isPRECandidate()
H A DDetectDeadLanes.cpp192 if (!MOReg.isVirtual()) in addUsedLanesOnOperand()
216 if (!MO.isReg() || !MO.getReg().isVirtual()) in transferUsedLanesStep()
283 if (!DefReg.isVirtual()) in transferDefinedLanesStep()
384 assert(MOReg.isVirtual()); in determineInitialDefinedLanes()
428 if (DefReg.isVirtual()) { in determineInitialUsedLanes()
468 if (!DefReg.isVirtual()) in isUndefInput()
480 if (MOReg.isVirtual()) { in isUndefInput()
537 if (!Reg.isVirtual()) in runOnce()
H A DRegAllocFast.cpp305 assert(Reg.isVirtual()); in shouldAllocateRegister()
728 assert(Reg.isVirtual()); in traceCopyChain()
852 assert(VirtReg.isVirtual() && "Expected virtreg"); in allocVirtRegUndef()
914 assert(VirtReg.isVirtual() && "Not a virtual register"); in defineVirtReg()
966 assert(VirtReg.isVirtual() && "Not a virtual register"); in useVirtReg()
993 if (Hint.isVirtual()) { in useVirtReg()
1088 assert(VirtReg.isVirtual() && "Bad map key"); in dumpState()
1106 if (Reg.isVirtual()) { in addRegClassDefCounts()
1167 if (Reg.isVirtual()) { in allocateInstruction()
1233 if (Reg.isVirtual() && shouldAllocateRegister(Reg)) in allocateInstruction()
[all …]
H A DMIRCanonicalizerPass.cpp158 if (MO.getReg().isVirtual()) in rescheduleCanonically()
175 if (!MO.isReg() || !MO.getReg().isVirtual()) in rescheduleCanonically()
188 if (!II->getOperand(i).getReg().isVirtual()) in rescheduleCanonically()
310 if (!Dst.isVirtual()) in propagateLocalCopies()
312 if (!Src.isVirtual()) in propagateLocalCopies()
H A DMachineUniformityAnalysis.cpp41 if (!op.getReg().isVirtual()) in markDefsDivergent()
92 if (op.isReg() && op.isDef() && op.getReg().isVirtual()) in pushUsers()
105 assert(Reg.isVirtual()); in usesValueFromCycle()
H A DVirtRegMap.cpp86 assert(virtReg.isVirtual() && Register::isPhysicalRegister(physReg)); in assignVirt2Phys()
113 if (Hint.isVirtual()) in hasPreferredPhys()
128 assert(virtReg.isVirtual()); in assignVirt2StackSlot()
136 assert(virtReg.isVirtual()); in assignVirt2StackSlot()
417 if (DstReg.isVirtual()) in handleIdentityCopy()
550 if (!MO.isReg() || !MO.getReg().isVirtual()) in rewrite()
H A DMachineCombiner.cpp154 if (MO.isReg() && MO.getReg().isVirtual()) in getOperandDef()
185 if (Src.isVirtual() && Dst.isVirtual()) { in isTransientMI()
191 if (Src.isVirtual()) in isTransientMI()
219 if (!(MO.isReg() && MO.getReg().isVirtual())) in getDepth()
272 if (!(MO.isReg() && MO.getReg().isVirtual())) in getLatency()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp138 if (Reg.isVirtual()) in usesRegClass()
193 if (!Reg.isVirtual()) in eraseInstrWithNoUses()
215 if (!DefReg.isVirtual()) { in eraseInstrWithNoUses()
249 if (DPRReg.isVirtual() && SPRReg.isVirtual()) { in optimizeSDPattern()
299 if (!OpReg.isVirtual()) in optimizeSDPattern()
343 if (!MI->getOperand(1).getReg().isVirtual()) in elideCopies()
369 if (!Reg.isVirtual()) { in elideCopiesAndPHIs()
378 if (!MI->getOperand(1).getReg().isVirtual()) in elideCopiesAndPHIs()
H A DMLxExpansionPass.cpp100 if (Reg.isVirtual()) { in getAccDefMI()
106 if (Reg.isVirtual()) { in getAccDefMI()
156 if (SrcReg.isVirtual()) { in hasLoopHazard()
164 if (Reg.isVirtual()) { in hasLoopHazard()
170 if (Reg.isVirtual()) { in hasLoopHazard()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp167 if (!Reg.isVirtual()) in getVRegDefOrNull()
296 if (!RegOp.isVirtual()) in collectUnprimedAccPHIs()
304 if (!Reg.isVirtual() || MRI->getRegClass(Reg) != &PPC::ACCRCRegClass) in collectUnprimedAccPHIs()
456 if (!Src.isVirtual() || !Dst.isVirtual()) in simplifyCode()
534 if (!(TrueReg1 == TrueReg2 && TrueReg1.isVirtual())) in simplifyCode()
553 if (FeedReg1.isVirtual()) { in simplifyCode()
586 if (!(FeedReg1 == FeedReg2 && FeedReg1.isVirtual())) in simplifyCode()
654 if (!TrueReg.isVirtual()) in simplifyCode()
664 if (!ConvReg.isVirtual()) in simplifyCode()
718 if (!TrueReg.isVirtual()) in simplifyCode()
[all …]
H A DPPCMacroFusion.cpp109 return RA.getReg().isVirtual() || in checkOpConstraints()
119 if (!RT.getReg().isVirtual()) in checkOpConstraints()
172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
183 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
/openbsd-src/gnu/llvm/clang/lib/AST/Interp/
H A DFunction.cpp42 bool Function::isVirtual() const { in isVirtual() function in Function
44 return M->isVirtual(); in isVirtual()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp40 assert(Reg.isVirtual()); in getRegKind()
160 assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual()); in getDefRegMask()
173 assert(MO.isUse() && MO.isReg() && MO.getReg().isVirtual()); in getUsedRegMask()
194 if (!MO.isReg() || !MO.getReg().isVirtual()) in collectVirtualRegUses()
290 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual() || MO.isDead()) in recede()
374 if (!Reg.isVirtual()) in advanceToNext()
H A DSIShrinkInstructions.cpp100 if (Reg.isVirtual()) { in foldImmediates()
152 assert(!Reg.isVirtual() && "Prior checks should ensure we only shrink " in shouldShrinkTrue16()
524 if (Dest->getReg().isVirtual() && SrcReg->isReg()) { in shrinkScalarLogicOp()
563 } else if (MO.getReg() == Reg && Reg.isVirtual()) { in instAccessReg()
730 if (T.isVirtual() && MRI->use_nodbg_empty(T)) { in matchSwap()
830 if (Dest->getReg().isVirtual() && Src0->isReg()) { in runOnMachineFunction()
924 if (DstReg.isVirtual()) { in runOnMachineFunction()
950 if (SReg.isVirtual()) { in runOnMachineFunction()
966 if (SDst->getReg().isVirtual()) in runOnMachineFunction()
976 if (Src2->getReg().isVirtual()) in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp80 if (DstReg.isVirtual() && in visitMBB()
90 else if (SrcReg.isVirtual() && in visitMBB()
/openbsd-src/gnu/llvm/llvm/tools/llvm-reduce/deltas/
H A DReduceRegisterDefs.cpp55 if (!RegPair.Reg.isVirtual()) in removeDefsFromFunction()
77 if (!RegPair.Reg.isVirtual()) in removeDefsFromFunction()

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