Searched refs:isInsertSubreg (Results 1 – 17 of 17) sorted by relevance
104 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()168 } else if (DefMI->isInsertSubreg()) { in hasLoopHazard()
245 if (MI->isInsertSubreg()) { in optimizeSDPattern()328 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), in hasPartialWrite()394 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
4395 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() || in getOperandLatency()4734 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getPredicationCost()4755 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getInstrLatency()
1835 let isInsertSubreg = 1 in
6538 let isInsertSubreg = 1;
71 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
243 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()926 assert(MI.isInsertSubreg() && "Invalid instruction"); in InsertSubregRewriter()1937 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()2080 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
1455 assert((MI.isInsertSubreg() || in getInsertSubregInputs()1458 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
276 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { in isCopyToReg()1832 if (mi->isInsertSubreg()) { in runOnMachineFunction()
137 FLAG(isInsertSubreg) in EmitInstrDocs()
287 bool isInsertSubreg : 1; variable
465 isInsertSubreg = R->getValueAsBit("isInsertSubreg"); in CodeGenInstruction()
1165 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; in emitRecord()
616 if (isInsertSubreg() && OpIdx == 3)1328 bool isInsertSubreg() const {
592 bit isInsertSubreg = false; // Is this instruction a kind of insert subreg?
1952 bit isInsertSubreg = 0;
148 if (MI.isCopyLike() || MI.isInsertSubreg()) in isDataInvariant()