| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 600 bool isAdd = true; in EncodeAddrModeOpValues() local
605 isAdd = false; in EncodeAddrModeOpValues()
611 isAdd = false; in EncodeAddrModeOpValues()
615 return isAdd; in EncodeAddrModeOpValues()
981 bool isAdd = true; in getAddrModeImm12OpValue() local
987 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
992 isAdd = false; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
998 isAdd = false; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
1012 isAdd = false; in getAddrModeImm12OpValue()
1015 isAdd = false; in getAddrModeImm12OpValue()
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| H A D | ARMAsmBackend.cpp | 501 bool isAdd = true; in adjustFixupValue() local
504 isAdd = false; in adjustFixupValue()
510 Value |= isAdd << 23; in adjustFixupValue()
730 bool isAdd = true; in adjustFixupValue() local
733 isAdd = false; in adjustFixupValue()
741 return Value | (isAdd << 23); in adjustFixupValue()
750 bool isAdd = true; in adjustFixupValue() local
753 isAdd = false; in adjustFixupValue()
761 Value |= isAdd << 23; in adjustFixupValue()
777 bool isAdd = true; in adjustFixupValue() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo16Instr.td | 59 let isCommutable = 1, isAdd = 1 in
64 let isCommutable = 1, isAdd = 1 in
69 let isAdd = 1 in
94 let isAdd = 1, Pattern = [(set mGPR:$rz, (add mGPR:$rZ, oimm8:$imm8))] in
100 let isAdd = 1 in
104 let isAdd = 1 in
114 let isAdd = 1 in
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| H A D | CSKYInstrInfo.td | 469 let isAdd = 1 in
493 let isAdd = 1 in
548 let isCommutable = 1, isAdd = 1 in
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| /openbsd-src/gnu/llvm/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 111 FLAG(isAdd) in EmitInstrDocs()
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| H A D | CodeGenInstruction.h | 259 bool isAdd : 1; variable
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| H A D | CodeGenInstruction.cpp | 449 isAdd = R->getValueAsBit("isAdd"); in CodeGenInstruction()
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| H A D | InstrInfoEmitter.cpp | 1137 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)"; in emitRecord()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 283 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 871 bool isAdd; member
3038 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
3284 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3286 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
3295 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3298 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
3305 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3313 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
3831 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
3835 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 2900 // {12} isAdd
2918 // {12} isAdd
3010 // {12} isAdd
3029 // {12} isAdd
3046 // {12} isAdd
3065 // {12} isAdd
3182 // {12} isAdd
3200 // {12} isAdd
3344 // {12} isAdd
3363 // {12} isAdd
[all …]
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| H A D | ARMInstrFormats.td | 802 // {12} isAdd
820 // {12} isAdd
841 // {12} isAdd
894 // {8} isAdd
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| H A D | ARMInstrThumb.td | 966 let isAdd = 1 in {
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| H A D | ARMInstrThumb2.td | 2345 let isAdd = 1 in
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 444 if (DI->getDesc().isAdd()) { in findInductionRegister()
1627 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
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| H A D | HexagonDepInstrInfo.td | 220 let isAdd = 1;
236 let isAdd = 1;
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| /openbsd-src/gnu/llvm/llvm/include/llvm/Target/ |
| H A D | Target.td | 555 bit isAdd = false; // Is this instruction an add instruction?
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| /openbsd-src/gnu/llvm/llvm/docs/TableGen/ |
| H A D | ProgRef.rst | 1927 bit isAdd = 0;
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 47335 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
47340 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
47345 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
47350 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
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