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/openbsd-src/gnu/llvm/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h30 constexpr RxC DecodeCR_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; } in DecodeCR_RD() argument
31 constexpr RxC DecodeCI_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; } in DecodeCI_RD() argument
32 constexpr RxC DecodeCR_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; } in DecodeCR_RS1() argument
33 constexpr RxC DecodeCI_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; } in DecodeCI_RS1() argument
34 constexpr RxC DecodeCR_RS2(uint32_t inst) { in DecodeCR_RS2() argument
35 return RxC{(inst & 0x7C) >> 2, false}; in DecodeCR_RS2()
38 constexpr RxC DecodeCIW_RD(uint32_t inst) { return RxC{(inst & 0x1C) >> 2}; } in DecodeCIW_RD() argument
39 constexpr RxC DecodeCL_RD(uint32_t inst) { return RxC{DecodeCIW_RD(inst)}; } in DecodeCL_RD() argument
40 constexpr RxC DecodeCA_RD(uint32_t inst) { return RxC{(inst & 0x380) >> 7}; } in DecodeCA_RD() argument
41 constexpr RxC DecodeCB_RD(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; } in DecodeCB_RD() argument
[all …]
H A DEmulateInstructionRISCV.cpp70 constexpr uint32_t DecodeJImm(uint32_t inst) { in DecodeJImm() argument
71 return (uint64_t(int64_t(int32_t(inst & 0x80000000)) >> 11)) // imm[20] in DecodeJImm()
72 | (inst & 0xff000) // imm[19:12] in DecodeJImm()
73 | ((inst >> 9) & 0x800) // imm[11] in DecodeJImm()
74 | ((inst >> 20) & 0x7fe); // imm[10:1] in DecodeJImm()
77 constexpr uint32_t DecodeIImm(uint32_t inst) { in DecodeIImm() argument
78 return int64_t(int32_t(inst)) >> 20; // imm[11:0] in DecodeIImm()
81 constexpr uint32_t DecodeBImm(uint32_t inst) { in DecodeBImm() argument
82 return (uint64_t(int64_t(int32_t(inst & 0x80000000)) >> 19)) // imm[12] in DecodeBImm()
83 | ((inst & 0x80) << 4) // imm[11] in DecodeBImm()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_mpc.h34 #define MPC_REG_LIST_DCN3_2(inst) \ argument
35 MPC_REG_LIST_DCN3_0(inst),\
36 SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\
37 SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
38 SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
39 SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
40 SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
41 SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
42 SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
43 SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
[all …]
H A Ddcn32_resource.h691 #define MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst) \ argument
693 SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst), \
694 SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst), \
695 SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst), \
696 SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst), \
697 SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst), \
698 SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst), \
699 SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst), \
700 SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst), \
701 SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst), \
[all …]
H A Ddcn32_mmhubbub.h32 #define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \ argument
33 SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
34 SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
35 SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
36 SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
37 SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
38 SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
39 SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
40 SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
41 SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/config/
H A Dtc-arm.c293 static struct arm_it inst; variable
711 inst.error = _("immediate expression requires a # prefix"); in my_get_expression()
736 if (inst.error == NULL) in my_get_expression()
737 inst.error = _("bad expression"); in my_get_expression()
748 inst.error = _("bad segment"); in my_get_expression()
764 inst.error = _("invalid constant"); in my_get_expression()
1014 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); in parse_reg_list()
1024 inst.error = _("bad range in register list"); in parse_reg_list()
1055 inst.error = _("missing `}'"); in parse_reg_list()
1071 inst.error = _("invalid register mask"); in parse_reg_list()
[all …]
/openbsd-src/gnu/llvm/lldb/source/Plugins/Instruction/LoongArch/
H A DEmulateInstructionLoongArch.cpp36 EmulateInstructionLoongArch::GetOpcodeForInstruction(uint32_t inst) { in GetOpcodeForInstruction() argument
70 if ((g_opcodes[i].mask & inst) == g_opcodes[i].value) in GetOpcodeForInstruction()
75 bool EmulateInstructionLoongArch::TestExecute(uint32_t inst) { in TestExecute() argument
76 Opcode *opcode_data = GetOpcodeForInstruction(inst); in TestExecute()
80 if (!(this->*opcode_data->callback)(inst)) in TestExecute()
87 uint32_t inst = m_opcode.GetOpcode32(); in EvaluateInstruction() local
91 Opcode *opcode_data = GetOpcodeForInstruction(inst); in EvaluateInstruction()
103 if (!(this->*opcode_data->callback)(inst)) in EvaluateInstruction()
128 uint32_t inst = (uint32_t)ReadMemoryUnsigned(ctx, m_addr, 4, 0, &success); in ReadInstruction() local
129 m_opcode.SetOpcode32(inst, GetByteOrder()); in ReadInstruction()
[all …]
H A DEmulateInstructionLoongArch.h63 bool TestExecute(uint32_t inst);
74 Opcode *GetOpcodeForInstruction(uint32_t inst);
76 bool EmulateBEQZ(uint32_t inst);
77 bool EmulateBNEZ(uint32_t inst);
78 bool EmulateBCEQZ(uint32_t inst);
79 bool EmulateBCNEZ(uint32_t inst);
80 bool EmulateJIRL(uint32_t inst);
81 bool EmulateB(uint32_t inst);
82 bool EmulateBL(uint32_t inst);
83 bool EmulateBEQ(uint32_t inst);
[all …]
/openbsd-src/sys/arch/m88k/m88k/
H A Ddb_disasm.c323 oimmed(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) in oimmed() argument
325 int32_t Linst = inst & 0xffff; in oimmed()
326 u_int32_t H6inst = inst >> 26; in oimmed()
327 u_int32_t rs1 = (inst >> 16) & 0x1f; in oimmed()
328 u_int32_t rd = (inst >> 21) & 0x1f; in oimmed()
348 ctrlregs(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) in ctrlregs() argument
350 u_int32_t dir = (inst >> 14) & 0x03; in ctrlregs()
351 u_int32_t sfu = (inst >> 11) & 0x07; in ctrlregs()
352 u_int32_t creg = (inst >> 5) & 0x3f; in ctrlregs()
353 u_int32_t rd = (inst >> 21) & 0x1f; in ctrlregs()
[all …]
H A Ddb_sstep.c91 branch_taken(u_int inst, vaddr_t pc, db_regs_t *regs) in branch_taken() argument
100 switch (inst >> (32 - 5)) { in branch_taken()
104 inst = (inst & 0x03ffffff) << 2; in branch_taken()
106 if (inst & 0x08000000) in branch_taken()
107 inst |= 0xf0000000; in branch_taken()
108 return (pc + inst); in branch_taken()
114 inst = (inst & 0x0000ffff) << 2; in branch_taken()
116 if (inst & 0x00020000) in branch_taken()
117 inst |= 0xfffc0000; in branch_taken()
118 return (pc + inst); in branch_taken()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/amdgpu/
H A Dsoc15_common.h28 #define GET_INST(ip, inst) \ argument
30 adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst)
36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ argument
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
66 #define RREG32_SOC15(ip, inst, reg) \ argument
[all …]
H A Damdgpu_amdkfd_gfx_v9.c51 uint32_t queue, uint32_t vmid, uint32_t inst) in kgd_gfx_v9_lock_srbm() argument
54 soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst)); in kgd_gfx_v9_lock_srbm()
57 static void kgd_gfx_v9_unlock_srbm(struct amdgpu_device *adev, uint32_t inst) in kgd_gfx_v9_unlock_srbm() argument
59 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_unlock_srbm()
64 uint32_t queue_id, uint32_t inst) in kgd_gfx_v9_acquire_queue() argument
69 kgd_gfx_v9_lock_srbm(adev, mec, pipe, queue_id, 0, inst); in kgd_gfx_v9_acquire_queue()
81 void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst) in kgd_gfx_v9_release_queue() argument
83 kgd_gfx_v9_unlock_srbm(adev, inst); in kgd_gfx_v9_release_queue()
90 uint32_t sh_mem_bases, uint32_t inst) in kgd_gfx_v9_program_sh_mem_settings() argument
92 kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst); in kgd_gfx_v9_program_sh_mem_settings()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.h31 #define OPTC_COMMON_REG_LIST_DCN3_1(inst) \ argument
32 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
33 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
34 SRI(OTG_VREADY_PARAM, OTG, inst),\
35 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
36 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
40 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.h32 #define OPTC_COMMON_REG_LIST_DCN3_14(inst) \ argument
33 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
34 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
35 SRI(OTG_VREADY_PARAM, OTG, inst),\
36 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h34 #define MCIF_WB_COMMON_REG_LIST_DCN3_0(inst) \ argument
35 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
36 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
37 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
38 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
39 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
40 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
41 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
42 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
43 SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
[all …]
H A Ddcn30_optc.h31 #define V_TOTAL_REGS_DCN30_SRI(inst) argument
33 #define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \ argument
34 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
35 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
36 SRI(OTG_VREADY_PARAM, OTG, inst),\
37 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
41 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
[all …]
H A Ddcn30_mpc.h45 #define MPC_REG_LIST_DCN3_0(inst)\ argument
46 MPC_COMMON_REG_LIST_DCN1_0(inst),\
47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\
54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\
[all …]
/openbsd-src/gnu/usr.bin/binutils/gdb/
H A Dcris-tdep.c1855 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) in quick_mode_bdap_prefix() argument
1865 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; in quick_mode_bdap_prefix()
1866 inst_env->prefix_value += cris_get_bdap_quick_offset (inst); in quick_mode_bdap_prefix()
1879 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) in process_autoincrement() argument
1883 inst_env->reg[cris_get_operand1 (inst)] += 1; in process_autoincrement()
1887 if (cris_get_operand1 (inst) == REG_PC) in process_autoincrement()
1894 inst_env->reg[cris_get_operand1 (inst)] += 2; in process_autoincrement()
1898 inst_env->reg[cris_get_operand1 (inst)] += 4; in process_autoincrement()
1909 static unsigned long get_data_from_address (unsigned short *inst,
1916 bdap_prefix (unsigned short inst, inst_env_type *inst_env) in bdap_prefix() argument
[all …]
/openbsd-src/gnu/usr.bin/binutils/gas/config/
H A Dtc-arm.c256 struct arm_it inst; variable
2662 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) in add_to_lit_pool()
2663 && (inst.reloc.exp.X_op == O_constant) in add_to_lit_pool()
2665 == inst.reloc.exp.X_add_number) in add_to_lit_pool()
2667 == inst.reloc.exp.X_unsigned)) in add_to_lit_pool()
2670 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) in add_to_lit_pool()
2671 && (inst.reloc.exp.X_op == O_symbol) in add_to_lit_pool()
2673 == inst.reloc.exp.X_add_number) in add_to_lit_pool()
2675 == inst.reloc.exp.X_add_symbol) in add_to_lit_pool()
2677 == inst.reloc.exp.X_op_symbol)) in add_to_lit_pool()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.h33 #define MPC_REG_LIST_DCN2_0(inst)\ argument
34 MPC_COMMON_REG_LIST_DCN1_0(inst),\
35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
[all …]
/openbsd-src/sys/arch/alpha/alpha/
H A Dfp_complete.c146 alpha_instruction inst; in this_cannot_happen() local
149 inst.bits = bits; in this_cannot_happen()
152 alpha_shadow.uop |= 1UL << inst.generic_format.opcode; in this_cannot_happen()
237 alpha_instruction inst; in cvt_qs_ts_st_gf_qf() local
239 inst.bits = inst_bits; in cvt_qs_ts_st_gf_qf()
247 switch(inst.float_format.function) { in cvt_qs_ts_st_gf_qf()
250 sts(inst.float_detail.fb, &sfb, p); in cvt_qs_ts_st_gf_qf()
252 ldt(inst.float_detail.fc, &tfc, p); in cvt_qs_ts_st_gf_qf()
255 if(inst.float_detail.src == 2) { in cvt_qs_ts_st_gf_qf()
256 stt(inst.float_detail.fb, &tfb, p); in cvt_qs_ts_st_gf_qf()
[all …]
/openbsd-src/gnu/usr.bin/binutils/opcodes/
H A Dmcore-dis.c95 unsigned short inst; local
110 inst = (ibytes[0] << 8) | ibytes[1];
112 inst = (ibytes[1] << 8) | ibytes[0];
118 if (op->inst == (inst & imsk[op->opclass]))
122 fprintf (stream, ".short 0x%04x", inst);
125 const char *name = grname[inst & 0x0F];
135 fprintf (stream, "\t%d", inst & 0x3);
145 fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
154 fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
162 fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/
H A Dmcore-dis.c95 unsigned short inst; local
110 inst = (ibytes[0] << 8) | ibytes[1];
112 inst = (ibytes[1] << 8) | ibytes[0];
118 if (op->inst == (inst & imsk[op->opclass]))
122 fprintf (stream, ".short 0x%04x", inst);
125 const char *name = grname[inst & 0x0F];
135 fprintf (stream, "\t%d", inst & 0x3);
145 fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
154 fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
162 fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
[all …]
/openbsd-src/gnu/usr.bin/cvs/man/
H A DMakefile.in145 inst=`echo $$i | sed -e 's/\\.[0-9a-z]*$$//'`; \
146 inst=`echo $$inst | sed -e 's/^.*\///'`; \
147 inst=`echo $$inst | sed '$(transform)'`.$$ext; \
148 echo " $(INSTALL_DATA) $$file $(DESTDIR)$(man1dir)/$$inst"; \
149 $(INSTALL_DATA) $$file $(DESTDIR)$(man1dir)/$$inst; \
162 inst=`echo $$i | sed -e 's/\\.[0-9a-z]*$$//'`; \
163 inst=`echo $$inst | sed -e 's/^.*\///'`; \
164 inst=`echo $$inst | sed '$(transform)'`.$$ext; \
165 echo " rm -f $(DESTDIR)$(man1dir)/$$inst"; \
166 rm -f $(DESTDIR)$(man1dir)/$$inst; \
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h51 #define DWBC_COMMON_REG_LIST_DCN1_0(inst) \ argument
52 SRI(WB_ENABLE, CNV, inst),\
53 SRI(WB_EC_CONFIG, CNV, inst),\
54 SRI(CNV_MODE, CNV, inst),\
55 SRI(WB_SOFT_RESET, CNV, inst),\
56 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
57 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
58 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
59 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
60 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
[all …]

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